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Adam Teman
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2020 – today
- 2024
- [j40]Esteban Garzón
, Robert Hanhan
FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access 12: 13923-13943 (2024) - [j39]Yehuda Kra
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 223-236 (2024) - [j38]Inbal Stanger
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 987-999 (2024) - [c39]Yehuda Kra, Naama Kra, Adam Teman:
Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors. DATE 2024: 1-6 - [c38]Roman Golman, Avinoam Segev, Adam Teman:
A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications. PRIME 2024: 1-4 - [c37]Yehuda Kra, Yehuda Rudin, Alexander Fish, Adam Teman:
Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network. PRIME 2024: 1-4 - [c36]Noam Roknian, Yonatan Shoshan, Inbal Stanger, Menachem Goldzweig, Yoav Weizmann, Adam Teman, Edoardo Charbon, Alexander Fish:
Methodologies for Device Characterization in Cryogenic Temperatures. PRIME 2024: 1-4 - 2023
- [j37]Esteban Garzón
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access 11: 16812-16819 (2023) - [j36]Hanan Marinberg, Esteban Garzón
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access 11: 94885-94897 (2023) - [j35]Esteban Garzón
AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 408-421 (2023) - [j34]Esteban Garzón
A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3867-3871 (2023) - [c35]Esteban Garzón
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS 2023: 1-4 - [c34]Noam Roknian
Overview of Cryogenic Operation in Nanoscale Technology Nodes. LASCAS 2023: 1-4 - 2022
- [j33]Esteban Garzón
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access 10: 28080-28093 (2022) - [j32]Esteban Garzón
AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro 42(6): 67-75 (2022) - [c33]Yehuda Kra, Yoav Weizman, Adam Teman:
SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. DCIS 2022: 1-6 - [c32]Robert Hanhan
EDAM: edit distance tolerant approximate matching content addressable memory. ISCA 2022: 495-507 - [c31]Inbal Stanger, Noam Roknian
Evaluation of Dual Mode Logic Under Cryogenic Temperatures. ISCAS 2022: 361-364 - [c30]Yehuda Kra, Adam Teman:
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing. ISCAS 2022: 1138-1139 - [c29]Esteban Garzón
A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS 2022: 2614-2615 - [i3]Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza:
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR abs/2204.09395 (2022) - 2021
- [j31]Roman Golman
Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. IEEE Access 9: 105831-105840 (2021) - [j30]Esteban Garzón
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1319-1324 (2021) - [c28]Yehuda Kra, Tzachi Noy, Adam Teman
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining. DATE 2021: 1574-1579 - [c27]Einat Levy, Aharon Sfez, Roman Golman, Odem Harel, Adam Teman
4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality. ISCAS 2021: 1-4 - [i2]Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits:
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR abs/2111.09747 (2021) - 2020
- [j29]Or Maltabashi
Physically Aware Affinity-Driven Multiplier Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2886-2897 (2020) - [j28]Robert Giterman
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1207-1217 (2020) - [j27]Tzachi Noy
Design of a Refresh-Controller for GC-eDRAM Based FIFOs. IEEE Trans. Circuits Syst. 67-I(12): 4804-4817 (2020) - [j26]Andrea Bonetti
Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 646-659 (2020) - [c26]Yehuda Kra, Tzachi Noy
WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation. DATE 2020: 1291-1294 - [c25]Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS 2020: 1 - [c24]Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman:
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS 2020: 1 - [c23]Roman Golman, Robert Giterman, Odem Harel, Adam Teman:
Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j25]Robert Giterman
Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. IEEE Access 7: 27641-27649 (2019) - [j24]Robert Giterman
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2042-2046 (2019) - [c22]Tom Munk, Hillel Kugler
TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches. VLSI-DAT 2019: 1-4 - 2018
- [j23]Robert Giterman
An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. IEEE J. Solid State Circuits 53(7): 2136-2148 (2018) - [j22]Robert Giterman
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1245-1256 (2018) - [j21]Robert Giterman
Gain-Cell Embedded DRAM-Based Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4208-4218 (2018) - [j20]Reza Ghanaatian
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 329-340 (2018) - [c21]Amir Shalom, Robert Giterman, Adam Teman
High Density GC-eDRAM Design in 16nm FinFET. ICECS 2018: 585-588 - [c20]Roman Golman, Robert Giterman, Adam Teman
Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. ICECS 2018: 589-592 - [c19]Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish
Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. ISCAS 2018: 1- - [c18]Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. ISCAS 2018: 1-5 - 2017
- [j19]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j18]Andrea Bonetti
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2388-2400 (2017) - [j17]Robert Giterman
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1362-1366 (2017) - [j16]Andrea Bonetti, Nicholas Preyss, Adam Teman
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ACM Trans. Design Autom. Electr. Syst. 22(4): 62:1-62:20 (2017) - [j15]Robert Giterman
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 502-509 (2017) - [j14]Amit Kazimirsky, Adam Teman
A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2411-2418 (2017) - [c17]Robert Giterman
An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC 2017: 308-311 - [i1]Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg:
A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. CoRR abs/1703.05769 (2017) - 2016
- [j13]Lior Moyal, Itamar Levi, Adam Teman
Synthesis of Dual Mode Logic. Integr. 55: 246-253 (2016) - [j12]Noa Edri, Pascal Meinerzhagen, Adam Teman
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 222-232 (2016) - [j11]Adam Teman
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. 21(4): 59:1-59:25 (2016) - [j10]Robert Giterman
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 358-362 (2016) - [j9]Lior Atias, Adam Teman
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2622-2633 (2016) - [c16]Davide Rossi
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c15]Jeremy Constantin, Andrea Bonetti, Adam Teman
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC 2016: 261-264 - [c14]Robert Giterman
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS 2016: 1006-1009 - [c13]Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman
A low-power correlator for wakeup receivers with algorithm pruning through early termination. ISCAS 2016: 2667-2670 - 2015
- [j8]Adam Teman
A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2034-2042 (2015) - [c12]Adam Teman
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC 2015: 81-86 - [c11]Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman
Mitigating the impact of faults in unreliable memories for error-resilient applications. DAC 2015: 102:1-102:6 - [c10]Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE 2015: 489-494 - [c9]Andrea Bonetti, Adam Teman
An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ISCAS 2015: 1850-1853 - [c8]Shrikanth Ganapathy, Adam Teman
Approximate computing with unreliable dynamic memories. NEWCAS 2015: 1-4 - 2014
- [j7]Hadar Dagan, Aviv Shapira, Adam Teman
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory. IEEE J. Solid State Circuits 49(9): 1942-1957 (2014) - [j6]Adam Teman
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 259-263 (2014) - [c7]Robert Giterman
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS 2014: 2177-2180 - 2013
- [j5]Hadar Dagan, Adam Teman
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. IEEE J. Solid State Circuits 48(6): 1497-1510 (2013) - [j4]Adam Teman
Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell. Microelectron. J. 44(3): 236-247 (2013) - 2012
- [j3]Arthur Spivak, Adam Teman
Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel. Sensors 12(8): 10067-10085 (2012) - [j2]Adam Teman
A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 873-877 (2012) - [c6]Hadar Dagan, Adam Teman
A GIDL free tunneling gate driver for a low power non-volatile memory array. ISCAS 2012: 452-455 - [c5]Janna Mezhibovsky, Adam Teman
State space modeling for sub-threshold SRAM stability analysis. ISCAS 2012: 1823-1826 - [c4]Hadar Dagan, Adam Teman
A low-cost low-power non-volatile memory for RFID applications. ISCAS 2012: 1827-1830 - 2011
- [j1]Adam Teman
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). IEEE J. Solid State Circuits 46(11): 2713-2726 (2011) - [c3]Janna Mezhibovsky, Adam Teman
Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM. SoCC 2011: 136-141
2000 – 2009
- 2009
- [c2]Sagi Fisher, Adam Teman
Ultra-low Power Subthreshold Flip-flop Design. ISCAS 2009: 1573-1576 - 2008
- [c1]Adam Teman
Autonomous CMOS image sensor for real time target detection and tracking. ISCAS 2008: 2138-2141
Coauthor Index
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last updated on 2024-10-07 21:18 CEST by the dblp team
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