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Teerachot Siriburanon
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2020 – today
- 2024
- [j28]Pingda Guan
, Ruichang Ma, Haikun Jia
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits 59(10): 3123-3141 (2024) - [c32]Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski:
A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j27]Xi Chen
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits 58(7): 1945-1958 (2023) - [j26]Enis Kobal
A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1331-1335 (2023) - [j25]Ali Esmailiyan, Elena Blokhina
An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1861-1865 (2023) - 2022
- [j24]Jianglin Du
A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. IEEE J. Solid State Circuits 57(2): 452-464 (2022) - [j23]Yizhe Hu
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57(2): 518-534 (2022) - [j22]Xi Chen
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 973-984 (2022) - [j21]Enis Kobal
A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5007-5017 (2022) - [j20]Yizhe Hu
Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3030-3036 (2022) - [c31]Dennis Andrade-Miceli, Conor Power, Ali Esmailiyan, Teerachot Siriburanon, Imran Bashir, Mike Asker, Dirk Leipold, Robert Bogdan Staszewski, Elena Blokhina:
Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures. ICECS 2022 2022: 1-4 - 2021
- [j19]Suoping Hu
A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits 56(2): 427-439 (2021) - [j18]Jianglin Du
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56(11): 3445-3457 (2021) - [j17]Ali Esmailiyan
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. 2: 23-31 (2021) - [j16]Yizhe Hu
Oscillator Flicker Phase Noise: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 538-544 (2021) - [c30]Enis Kobal
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS. ESSCIRC 2021: 377-380 - [c29]Jianglin Du
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits 2021: 1-2 - 2020
- [c28]Pierre Bisiaux, Elena Blokhina
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. ECCTD 2020: 1-5 - [c27]Robert Bogdan Staszewski, Panagiotis Giounanlis, Ali Esmailiyan, Hongying Wang, Imran Bashir, Cagri Cetintepe, Dennis Andrade-Miceli, Mike Asker, Dirk Leipold, Teerachot Siriburanon, Andrii Sokolov
Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K. ISCAS 2020: 1-5 - [c26]Yizhe Hu, Xi Chen
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC 2020: 276-278
2010 – 2019
- 2019
- [j15]Jian Pang
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits 54(5): 1375-1390 (2019) - [j14]Peng Chen
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. IEEE J. Solid State Circuits 54(11): 3075-3085 (2019) - [j13]Hanli Liu
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits 54(12): 3478-3492 (2019) - [j12]Yizhe Hu
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1962-1966 (2019) - [c25]Vivek Govindaraj, Jianglin Du
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS 2019: 81-84 - [c24]Jianglin Du
A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. CICC 2019: 1-4 - [c23]Imran Bashir
A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip. ESSCIRC 2019: 125-128 - [c22]Hanli Liu, Zheng Sun, Hongye Huang
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC 2019: 256-258 - [c21]Zhong Gao
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. NEWCAS 2019: 1-4 - 2018
- [j11]Hanli Liu, Teerachot Siriburanon
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 187-196 (2018) - [j10]Yizhe Hu
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. IEEE J. Solid State Circuits 53(7): 1977-1987 (2018) - [j9]Naser Pourmousavian
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS. IEEE J. Solid State Circuits 53(9): 2572-2583 (2018) - 2017
- [j8]Rui Wu
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [c20]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c19]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - [c18]Peng Chen
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC 2017: 93-96 - [c17]Yizhe Hu
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner. ESSCIRC 2017: 87-90 - [c16]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC 2017: 424-425 - 2016
- [j7]Teerachot Siriburanon
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits 51(5): 1246-1260 (2016) - [j6]Teerachot Siriburanon
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [c15]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2 - [c14]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - [c13]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - 2015
- [j5]Teerachot Siriburanon
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. 98-C(6): 471-479 (2015) - [j4]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [c12]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c11]Teerachot Siriburanon
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43 - [c10]Teerachot Siriburanon
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC 2015: 76-79 - [c9]Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. ISSCC 2015: 1-3 - [c8]Teerachot Siriburanon
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - 2014
- [j3]Ahmed Musa, Wei Deng, Teerachot Siriburanon
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49(1): 50-60 (2014) - [c7]Wei Deng, Ahmed Musa, Teerachot Siriburanon
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22 - [c6]Teerachot Siriburanon
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC 2014: 25-26 - [c5]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267 - 2013
- [j2]Teerachot Siriburanon
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. 96-C(6): 804-812 (2013) - [j1]Wei Deng, Teerachot Siriburanon
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits 48(7): 1710-1720 (2013) - [c4]Teerachot Siriburanon
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC 2013: 97-98 - [c3]Teerachot Siriburanon
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC 2013: 403-406 - [c2]Wei Deng, Ahmed Musa, Teerachot Siriburanon
A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. ISSCC 2013: 248-249 - 2012
- [c1]Wei Deng, Teerachot Siriburanon
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC 2012: 201-204
Coauthor Index
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