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WO2024229870A1 - 阵列基板的制作方法及阵列基板 - Google Patents

阵列基板的制作方法及阵列基板 Download PDF

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Publication number
WO2024229870A1
WO2024229870A1 PCT/CN2023/093722 CN2023093722W WO2024229870A1 WO 2024229870 A1 WO2024229870 A1 WO 2024229870A1 CN 2023093722 W CN2023093722 W CN 2023093722W WO 2024229870 A1 WO2024229870 A1 WO 2024229870A1
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WO
WIPO (PCT)
Prior art keywords
layer
electrode
conductive portion
transparent conductive
array substrate
Prior art date
Application number
PCT/CN2023/093722
Other languages
English (en)
French (fr)
Inventor
钟德镇
张原豪
陶园
Original Assignee
昆山龙腾光电股份有限公司
Filing date
Publication date
Application filed by 昆山龙腾光电股份有限公司 filed Critical 昆山龙腾光电股份有限公司
Priority to CN202380009342.7A priority Critical patent/CN116941028A/zh
Publication of WO2024229870A1 publication Critical patent/WO2024229870A1/zh

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  • the present invention relates to the technical field of displays, and in particular to a method for manufacturing an array substrate and the array substrate.
  • thin and light display panels are very popular among consumers, especially thin and light display panels (liquid crystal display, LCD).
  • An existing display device includes a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), a color filter substrate (Color Filter Substrate, CF Substrate) and liquid crystal molecules filled between the thin film transistor array substrate and the color filter substrate.
  • a driving voltage is applied to the pixel electrode of the thin film transistor array substrate and the common electrode of the color filter substrate respectively, or a driving voltage is applied to the common electrode and the pixel electrode of the thin film transistor array substrate respectively, to control the rotation direction of the liquid crystal molecules between the two substrates to refract the backlight provided by the backlight module of the display device, thereby displaying a picture.
  • the manufacturing process of the thin film transistor array substrate in the prior art is relatively complicated.
  • the first mask process is required when manufacturing the scan line and the gate; the second mask process is required when manufacturing the active layer; the third mask process is required when manufacturing the pixel electrode; the fourth mask process is required when manufacturing the data line, the source electrode and the drain electrode; the fifth mask process is required when opening the insulating layer; and the sixth mask process is required when manufacturing the common electrode. Therefore, in the prior art, when manufacturing the thin film transistor array substrate, at least six mask processes are required, six types of mask plates are required, the manufacturing process is complicated, the manufacturing time is long, and the cost is high.
  • an object of the present invention is to provide a method for manufacturing an array substrate and an array substrate, so as to solve the problem of complex array substrate manufacturing process in the prior art.
  • the present invention provides a method for manufacturing an array substrate, comprising:
  • first metal layer Forming a first metal layer above the substrate, etching the first metal layer, forming a patterned scan line and a gate on the first metal layer, wherein the gate is conductively connected to the scan line;
  • a semiconductor layer and a positive photoresist layer are sequentially formed on the first insulating layer, the first metal layer is used as a mask, the positive photoresist layer is photolithographically processed from the side of the substrate away from the positive photoresist layer, the positive photoresist layer forms a patterned positive photoresist pattern layer, the positive photoresist pattern layer corresponds to the scan line and the gate, the semiconductor layer is etched with the positive photoresist pattern layer as a shield, and the semiconductor layer forms an active layer corresponding to the scan line and the gate;
  • a second metal layer and a photoresist layer are sequentially formed above the first transparent conductive layer and the semiconductor layer, and a half-tone mask is used as a shield to perform photolithography on the photoresist layer from a side of the half-tone mask away from the substrate, so that the photoresist layer forms a patterned first photoresist pattern layer, wherein the first photoresist pattern layer includes a non-photoresist pattern area that is completely photoetched, a half-photoresist pattern layer that is partially photoetched, and a full-photoresist pattern layer that is not photoetched;
  • the second metal layer is etched for the first time and the first transparent conductive layer is etched for the second time, the first transparent conductive layer forms a patterned first electrode and a first conductive portion, and the first conductive portion is conductively connected to the active layer;
  • the semi-photoresist pattern layer is removed by a photoresist ashing process, and the first photoresist pattern layer forms the second photoresist pattern layer.
  • the second metal layer is etched for the second time with the second photoresist pattern layer as a shield, and the second metal layer forms a data line, a source electrode and a second conductive portion, and the first electrode and the active layer in the channel region are exposed, the data line is conductively connected to the source electrode, at least one of the first conductive portion and the second conductive portion is a drain electrode, the first electrode and the channel region of the active layer both correspond to the semi-photoresist pattern region, and the data line, the source electrode and the second conductive portion all correspond to the full photoresist pattern layer.
  • the manufacturing method further comprises:
  • the doped semiconductor layer is etched for the second time with the second photoresist pattern layer as a shield, and the doped semiconductor layer forms a patterned doped semiconductor pattern layer, and the doped semiconductor pattern layer is disconnected in the channel region.
  • the manufacturing method further comprises:
  • the doped semiconductor layer is etched for the first time;
  • the doped semiconductor layer is etched for the second time with the second photoresist pattern layer as a shield, and the doped semiconductor layer forms a doped semiconductor pattern layer, the doped semiconductor pattern layer is disconnected in the channel region, and the first conductive part and the second conductive part are conductively connected.
  • the first electrode is a pixel electrode, and the first electrode and the first conductive portion are conductively connected.
  • the manufacturing method further comprises:
  • a second transparent conductive layer is formed above the second insulating layer, and the second transparent conductive layer is etched to form a patterned second electrode and a third conductive portion.
  • the second electrode is a common electrode.
  • the third conductive portion and the first electrode are insulated from each other.
  • the third conductive portion conductively connects the first electrode and the second conductive portion through the contact hole.
  • the first electrode is a common electrode, the first electrode and the first conductive portion are insulated from each other, and the manufacturing method further includes:
  • a second transparent conductive layer is formed above the second insulating layer, and the second transparent conductive layer is etched to form a patterned second electrode and a third conductive portion.
  • the second electrode is a pixel electrode, and the third conductive portion is conductively connected to the second electrode.
  • the second electrode and the first electrode are insulated from each other, and the third conductive portion is conductively connected to the second conductive portion through the contact hole.
  • the first transparent conductive layer is made of metal oxide semiconductor material, and the manufacturing method further includes:
  • the first transparent conductive layer is firstly subjected to a conductor treatment
  • a hydrogen channel treatment is performed on the active layer exposed in the channel region by using a hydrogen doping process.
  • the first transparent conductive layer is made of metal oxide semiconductor material, and the manufacturing method further includes:
  • the first transparent conductive layer is subjected to a conductor treatment.
  • the manufacturing method further comprises:
  • the first transparent conductive layer is subjected to a conductor treatment by a hydrogen doping process, and the active layer exposed in the channel region is subjected to a hydrogen channel treatment.
  • the present application also provides an array substrate, which is manufactured by the manufacturing method as described above, and the array substrate comprises:
  • a first metal layer is disposed above the substrate, the first metal layer comprises a scan line and a gate, and the gate is conductively connected to the scan line;
  • a first insulating layer disposed above the first metal layer, the first insulating layer covering the scan line and the gate;
  • a first transparent conductive layer and a semiconductor layer are disposed above the first insulating layer, the first transparent conductive layer includes a first electrode and a first conductive portion, the semiconductor layer includes an active layer, and the first conductive portion is conductively connected to the active layer;
  • a second metal layer is disposed above the first transparent conductive layer and the semiconductor layer, wherein the second metal layer includes a data line, a source electrode and a second conductive portion, wherein the data line is conductively connected to the source electrode, and at least one of the first conductive portion and the second conductive portion is a drain electrode.
  • the array substrate further comprises a doped semiconductor layer disposed between the semiconductor layer and the second metal layer, the doped semiconductor layer comprises a patterned doped semiconductor pattern layer, and the doped semiconductor pattern layer is disconnected in a channel region of the active layer.
  • the first electrode is a pixel electrode, and the first electrode and the first conductive portion are conductively connected.
  • the array substrate further includes:
  • a second transparent conductive layer is provided above the second insulating layer, the second transparent conductive layer includes a second electrode and a third conductive portion, the second electrode is a common electrode, the third conductive portion and the first electrode are insulated from each other, and the third conductive portion conductively connects the first electrode and the second conductive portion through the contact hole.
  • the second conductive part is conductively connected to the first conductive part.
  • the first electrode is a common electrode
  • the first electrode and the first conductive portion are insulated from each other
  • the array substrate further includes:
  • a second transparent conductive layer is arranged above the second insulating layer, the second transparent conductive layer includes a second electrode and a third conductive portion, the second electrode is a pixel electrode, the third conductive portion is conductively connected to the second electrode, the first electrode and the second electrode are insulated from each other, and the third conductive portion is conductively connected to the second conductive portion through the contact hole.
  • the first transparent conductive layer is etched for the first time and the semiconductor layer is etched respectively, and then using a half-tone mask, the first transparent conductive layer is etched for the second time and the second metal layer is etched twice, thereby reducing the number of masks, simplifying the manufacturing process, and reducing the manufacturing cost; and after etching the second metal layer twice, the first transparent conductive layer is still retained under the data line, the source electrode, and the second conductive part, thereby reducing the impedance of the data line, the source electrode, and the second conductive part.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in a first embodiment of the present invention.
  • FIGS. 2a to 2p are schematic diagrams of a method for manufacturing an array substrate in Embodiment 1 of the present invention.
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a display panel in the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the cross-sectional structure of an array substrate in Embodiment 2 of the present invention.
  • FIG. 5 is a schematic plan view of an array substrate in a second embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view of a method for manufacturing an array substrate in a second embodiment of the present invention.
  • FIG. 7 is a second cross-sectional schematic diagram of the method for manufacturing the array substrate in the second embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the cross-sectional structure of an array substrate in Embodiment 3 of the present invention.
  • 9a to 9b are schematic cross-sectional views of a method for manufacturing an array substrate in Embodiment 3 of the present invention.
  • FIG. 10 is a schematic diagram of the cross-sectional structure of an array substrate in Embodiment 4 of the present invention.
  • FIG. 11 is a plan view of an array substrate in Embodiment 4 of the present invention.
  • 12a to 12c are schematic diagrams of a method for manufacturing an array substrate in Embodiment 4 of the present invention.
  • FIG. 13 is a schematic diagram of the cross-sectional structure of a display panel in Embodiment 4 of the present invention.
  • Fig. 1 is a schematic cross-sectional view of an array substrate in Embodiment 1 of the present invention.
  • an array substrate which includes: a substrate 10, which can be made of materials such as glass, quartz, silicon, acrylic acid or polycarbonate, and can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.
  • PES polyethersulfone
  • PEN polyethylene naphthalate
  • PE polyethylene
  • PI polyimide
  • PVC polyvinyl chloride
  • PET polyethylene terephthalate
  • the first metal layer 11 is disposed above the substrate 10.
  • the first metal layer 11 is directly disposed on the upper surface of the substrate 10.
  • the first metal layer 11 includes a scan line 111 and a gate 112.
  • the gate 112 is conductively connected to the scan line 111.
  • a portion of the scan line 111 is used as the gate 112, that is, the gate 112 and the scan line 111 are located on the same straight line, so that the aperture ratio of the pixel can be increased.
  • the first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.
  • the gate 112 can also be not on the same straight line as the scan line 111, that is, the gate 112 is protruding from the scan line 111 for arrangement, which is not limited here.
  • a first insulating layer 101 is disposed above the first metal layer 11.
  • the first insulating layer 101 is directly disposed on the upper surface of the substrate 10 and the first metal layer 11 and covers the scan line 111 and the gate 112.
  • the first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • the first transparent conductive layer 12 and the semiconductor layer 13 are disposed on the first insulating layer 101.
  • the first transparent conductive layer 12 includes a first electrode 121 and a first conductive portion 122.
  • the semiconductor layer 13 includes an active layer 131.
  • the first conductive portion 122 is conductively connected to the active layer 131.
  • the semiconductor layer 13 is made of amorphous silicon (a-Si) material; the first transparent conductive layer 12 can be made of a metal oxide semiconductor material, but it is necessary to conduct a conductor treatment on the metal oxide semiconductor, such as plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, so that a part of the first transparent conductive layer 12 is conductorized.
  • a-Si amorphous silicon
  • the impedance of the first transparent conductive layer 12 after the conductorization treatment is lower than the impedance before the conductorization treatment, and is equivalent to the impedance of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the metal oxide semiconductor is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).
  • the first transparent conductive layer 12 can also be made of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO), so that there is no need for a conductor processing process.
  • the second metal layer 15 (FIG. 2h) is disposed above the first transparent conductive layer 12 and the semiconductor layer 13.
  • the second metal layer 15 includes a data line 151, a source electrode 152, and a second conductive portion 153.
  • the data line 151 is conductively connected to the source electrode 152.
  • At least one of the first conductive portion 122 and the second conductive portion 153 is a drain electrode.
  • the second metal layer 15 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.
  • the array substrate further includes a doped semiconductor layer 14 (FIG. 2h) disposed between the semiconductor layer 13 and the second metal layer 15, the doped semiconductor layer 14 includes a patterned doped semiconductor pattern layer 141, and the doped semiconductor pattern layer 141 is disconnected in the channel region 142 of the active layer 131.
  • the data line 151, the source electrode 152 and the second conductive portion 153 all correspond to the doped semiconductor pattern layer 141, that is, the projection of the data line 151, the source electrode 152 and the second conductive portion 153 on the substrate 10 overlaps with the doped semiconductor pattern layer 141.
  • the doped semiconductor layer 14 is made of doped amorphous silicon (N+a-Si) material, so that the source electrode 152 and the drain electrode can be better electrically connected to the active layer 131.
  • the first electrode 121 is a pixel electrode, and the first electrode 121 and the first conductive portion 122 are conductively connected.
  • the array substrate further includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second insulating layer 102 is provided with a contact hole H in the region corresponding to the first electrode 121 and the second conductive portion 153.
  • the second transparent conductive layer 16 includes a second electrode 161 and a third conductive portion 162, the second electrode 161 is a common electrode, the third conductive portion 162 and the first electrode 121 are both insulated from the second electrode 161, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the region corresponding to the first electrode 121, so as to facilitate the formation of a horizontal electric field between the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • the third conductive portion 162 conductively connects the first electrode 121 and the second conductive portion 153 through the contact hole H, that is, in this embodiment, the first conductive portion 122 and the second conductive portion 153 are both drains. By using both the first conductive portion 122 and the second conductive portion 153 as the drain, and conductively connecting the first electrode 121 and the second conductive portion 153 through the third conductive portion 162, the impedance of the drain can be reduced.
  • the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two; the second transparent conductive layer 16 is made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the common electrode may not be provided on the array substrate, and the common electrode is provided on the color film substrate 20 to form a TN or VA display mode.
  • the second transparent conductive layer 16 may not be provided, and the first conductive portion 122 may be directly used as the drain, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122.
  • the side of the substrate 10 facing the first metal layer 11 is an upper direction (or a front side), and the side of the substrate 10 away from the first metal layer 11 is a lower direction (or a back side).
  • Figures 2a to 2p are schematic diagrams of a method for manufacturing an array substrate in Embodiment 1 of the present invention.
  • this embodiment also provides a method for manufacturing an array substrate, which is used to manufacture the above-mentioned array substrate, and the manufacturing method comprises: as shown in Figures 2a-1 and 2a-2, providing a substrate 10, the substrate 10 can be made of materials such as glass, quartz, silicon, acrylic acid or polycarbonate, and the substrate 10 can also be a flexible substrate, and suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.
  • PES polyethersulfone
  • PEN polyethylene naphthalate
  • PE polyethylene
  • PI polyimide
  • PVC polyvinyl chloride
  • PET polyethylene terephthalate
  • a first metal layer 11 is formed above the substrate 10, and the first metal layer 11 is disposed directly on the upper surface of the substrate 10.
  • the first metal layer 11 is etched using a first mask process, and the first metal layer 11 forms a patterned scan line 111 and a gate 112, and the gate 112 is conductively connected to the scan line 111.
  • the first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.
  • a first insulating layer 101 covering the scanning line 111 and the gate 112 is formed above the substrate 10.
  • the first insulating layer 101 is directly disposed on the upper surface of the substrate 10 and the first metal layer 11 and covers the scanning line 111 and the gate 112.
  • the first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • a first transparent conductive layer 12 and a negative photoresist layer 100 are sequentially formed above the first insulating layer 101.
  • the negative photoresist layer 100 is subjected to photolithography (exposure, development) from the side of the substrate 10 away from the negative photoresist layer 100 (the back side of the substrate 10) to remove the negative photoresist layer 100 corresponding to the scanning line 111 and the gate 112, and the negative photoresist layer 100 forms a patterned negative photoresist pattern layer 110.
  • the first transparent conductive layer 12 is etched for the first time with the negative photoresist pattern layer 110 as a shield, and the first transparent conductive layer 12 corresponding to the scanning line 111 and the gate 112 is removed.
  • the first transparent conductive layer 12 is made of metal oxide semiconductor material, but it is necessary to conduct a conductor treatment on the metal oxide semiconductor, such as plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, so that part or all of the first transparent conductive layer 12 is conductorized.
  • a conductor treatment on the metal oxide semiconductor such as plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, so that part or all of the first transparent conductive layer 12 is conductorized.
  • the impedance of the first transparent conductive layer 12 after the conductorization treatment is lower than the impedance before the conductorization treatment, and is equivalent to the impedance of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the metal oxide semiconductor is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).
  • the first transparent conductive layer 12 can also be made of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO), so that there is no need for a conductor processing process.
  • a semiconductor layer 13 and a positive photoresist layer 200 are sequentially formed on the first insulating layer 101.
  • the positive photoresist layer 200 is subjected to photolithography (exposure, development) from the side of the substrate 10 away from the positive photoresist layer 200 (the back side of the substrate 10), and the positive photoresist layer 200 forms a patterned positive photoresist pattern layer 210, and the positive photoresist pattern layer 210 corresponds to the scanning line 111 and the gate 112, that is, the positive photoresist layer 200 corresponding to the scanning line 111 and the gate 112 is retained, and the projection of the scanning line 111 and the gate 112 on the substrate 10 coincides with the positive photoresist pattern layer 210.
  • the semiconductor layer 13 is etched with the positive photoresist pattern layer 210 as a shield, and the semiconductor layer 13 forms an active layer 131 corresponding to the scan line 111 and the gate 112, that is, the projection of the scan line 111 and the gate 112 on the substrate 10 coincides with the active layer 131.
  • the semiconductor layer 13 is made of amorphous silicon (a-Si) material.
  • the first transparent conductive layer 12 can be etched for the first time, and then the semiconductor layer 13 and the positive photoresist layer 200 are formed in sequence above the first insulating layer 101; or the semiconductor layer 13 can be etched first to form the active layer 131, and then the first transparent conductive layer 12 and the negative photoresist layer 100 are formed in sequence above the first insulating layer 101.
  • the order of the two etching processes can be adjusted.
  • the array substrate further includes a doped semiconductor layer 14 disposed between the semiconductor layer 13 and the second metal layer 15. As shown in FIGS. 2h-2i, the doped semiconductor layer 14, the second metal layer 15 and the photoresist layer 300 are sequentially formed above the first transparent conductive layer 12 and the semiconductor layer 13.
  • the second mask process uses a half-tone mask 400 (Half Tone Mask) as a shield, and performs photolithography on the photoresist layer 300 from the side of the half-tone mask 400 away from the substrate 10 (the front side of the substrate 10), and the photoresist layer 300 forms a patterned first photoresist pattern layer 310, and the first photoresist pattern layer 310 includes a completely photoetched non-photoresist pattern area 311, a partially photoetched half-photoresist pattern layer 312, and a non-photoetched full-photoresist pattern layer 313.
  • a half-tone mask 400 Hyf Tone Mask
  • the doped semiconductor layer 14 is made of doped amorphous silicon (N+a-Si) material
  • the second metal layer 15 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, Cu/Mo, etc.
  • the photoresist layer 300 adopts positive photoresist, and the halftone mask 400 includes a light-transmitting area 410, a semi-light-transmitting area 420 and a non-light-transmitting area 430.
  • the photoresist layer 300 is completely photoetched away in the area corresponding to the light-transmitting area 410, and a non-photoresist pattern area 311 is formed; the photoresist layer 300 is partially photoetched away in the area corresponding to the semi-light-transmitting area 420, and a half-photoresist pattern layer 312 is formed; the photoresist layer 300 is not photoetched away in the area corresponding to the non-light-transmitting area 430, and a full-photoresist pattern layer 313 is formed.
  • the photoresist layer 300 can also use negative photoresist, but the patterns of the light-transmitting area 410 and the opaque area 430 on the half-tone mask 400 are opposite.
  • the photoresist layer 300 is not photoetched in the area corresponding to the light-transmitting area 410, and a full photoresist pattern layer 313 is formed; the photoresist layer 300 is partially photoetched in the area corresponding to the semi-transmitting area 420, and a half photoresist pattern layer 312 is formed; the photoresist layer 300 is completely photoetched in the area corresponding to the non-light-transmitting area 430, and a non-photoresist pattern area 311 is formed.
  • the second metal layer 15 is etched for the first time
  • the doped semiconductor layer 14 is etched for the first time
  • the first transparent conductive layer 12 is etched for the second time in sequence.
  • the first transparent conductive layer 12 forms a patterned first electrode 121 and a first conductive portion 122
  • the first conductive portion 122 is conductively connected to the active layer 131.
  • the first electrode 121 is a pixel electrode
  • the first electrode 121 and the first conductive portion 122 are conductively connected, that is, the first conductive portion 122 serves as a drain.
  • a photoresist ashing process is used to remove the half photoresist pattern layer 312, and a portion of the full photoresist pattern layer 313 is retained, and the first photoresist pattern layer 310 forms a second photoresist pattern layer 320.
  • the second photoresist pattern layer 320 as a shield, the second metal layer 15 is etched for the second time and the doped semiconductor layer 14 is etched for the second time in sequence.
  • the second metal layer 15 forms a data line 151, a source electrode 152, and a second conductive portion 153, and the first electrode 121 and the active layer 131 of the channel region 142 are exposed, and the data line 151 is conductively connected to the source electrode 152.
  • the doped semiconductor layer 14 forms a patterned doped semiconductor pattern layer 141, the doped semiconductor pattern layer 141 is disconnected in the channel region 142, and the data line 151, the source electrode 152 and the second conductive portion 153 all correspond to the doped semiconductor pattern layer 141, that is, the projection of the data line 151, the source electrode 152 and the second conductive portion 153 on the substrate 10 overlaps with the doped semiconductor pattern layer 141.
  • the source electrode 152 and the drain electrode can be better electrically connected to the active layer 131, and the doped semiconductor layer 14 and the first transparent conductive layer 12 retained under the data line 151 can reduce the impedance of the data line 151.
  • the first electrode 121 and the channel region 142 of the active layer 131 all correspond to the semi-photoresist pattern region 312, and the data line 151, the source electrode 152 and the second conductive portion 153 all correspond to the full photoresist pattern layer 313.
  • the first transparent conductive layer 12 is made of a metal oxide semiconductor material.
  • the first transparent conductive layer 12 is then subjected to a conductor treatment, thereby conducting the first electrode 121.
  • a conductor treatment For example, plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping are used to conduct part or all of the first transparent conductive layer 12.
  • the first transparent conductive layer 12 is subjected to a conductor treatment by a hydrogen doping process, and the active layer 131 exposed in the channel region 142 can be subjected to a hydrogen channel treatment.
  • the hydrogen doping process can be used not only to perform hydrogen channel treatment on the active layer 131 exposed in the channel region 142, but also to perform conductor treatment on the first transparent conductive layer 12, so as to reduce the steps of the manufacturing process.
  • a second insulating layer 102 is formed on the top of the first insulating layer 101, and the second insulating layer 102 is etched by a third mask process.
  • the second insulating layer 102 forms a contact hole H in the region corresponding to the first electrode 121 and the second conductive portion 153.
  • the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • a second transparent conductive layer 16 is formed on the top of the second insulating layer 102, and the second transparent conductive layer 16 is etched by a fourth mask process.
  • the second transparent conductive layer 16 forms a patterned second electrode 161 and a third conductive portion 162, the second electrode 161 is a common electrode, and the third conductive portion 162 and the first electrode 121 are both insulated from the second electrode 161, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 has a comb-like structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe Field Switching
  • the third conductive part 162 conductively connects the first electrode 121 and the second conductive part 153 through the contact hole H, that is, in this embodiment, the first conductive part 122 and the second conductive part 153 are both used as drains.
  • the impedance of the drain can be reduced.
  • the second transparent conductive layer 16 is made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the common electrode may not be provided on the array substrate, and the common electrode is provided on the color filter substrate 20 to form a TN or VA display mode.
  • the second transparent conductive layer 16 may not be provided, and the first conductive portion 122 may be directly used as the drain, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122 .
  • FIG3 is a schematic diagram of the cross-sectional structure of the display panel in the first embodiment of the present invention.
  • the present invention also provides a display panel, comprising the array substrate as described above, an opposing substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the opposing substrate 20.
  • An upper polarizer 41 is provided on the opposing substrate 20, and a lower polarizer 42 is provided on the array substrate.
  • the light transmission axis of the upper polarizer 41 and the light transmission axis of the lower polarizer 42 are perpendicular to each other.
  • the liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy).
  • the positive liquid crystal molecules are treated in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the opposing substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate.
  • the array substrate and the opposing substrate 20 are also provided with an alignment layer in a layer facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.
  • the counter substrate 20 is a color filter substrate, and a black matrix 21 and a color resist layer 22 are provided on the counter substrate 20.
  • the black matrix 21 corresponds to the scan line 111, the data line 151, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates a plurality of color resist layers 22.
  • the color resist layer 22 includes color resist materials of red (R), green (G) and blue (B), and correspondingly forms sub-pixels of red (R), green (G) and blue (B).
  • FIG4 is a schematic diagram of the cross-sectional structure of the array substrate in the second embodiment of the present invention.
  • FIG5 is a schematic diagram of the plan view of the array substrate in the second embodiment of the present invention.
  • the array substrate provided in the second embodiment of the present invention is substantially the same as the array substrate in the first embodiment (FIG. 1), except that, in the present embodiment:
  • the array substrate further includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second transparent conductive layer 16 includes a second electrode 161, the second electrode 161 is a common electrode, the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the first conductive portion 122 is directly used as the drain, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122. Therefore, the second transparent conductive layer 16 does not need to form a third conductive portion 162, and the second insulating layer 102 does not need to open holes in the area corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • the first conductive part 122 is directly used as the drain, and the impedance of the drain is relatively large, but the second transparent conductive layer 16 does not need to form the third conductive part 162, and there is no need to open holes in the second insulating layer 102 corresponding to the first electrode 121 and the second conductive part 153, which can simplify the manufacturing process.
  • FIG. 6 is a cross-sectional schematic diagram of one of the manufacturing methods of the array substrate in the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional schematic diagram of the second manufacturing method of the array substrate in the second embodiment of the present invention.
  • the manufacturing method provided in the second embodiment of the present invention is basically the same as the manufacturing method in the first embodiment (FIG. 2a to FIG. 2p), except that, in the present embodiment:
  • the first transparent conductive layer 12 is made of metal oxide semiconductor material.
  • the manufacturing method further includes: before forming the second metal layer 15, firstly conducting the first transparent conductive layer 12; after etching the second metal layer 15 for the second time, using a hydrogen doping process to conduct a hydrogen channel treatment on the active layer 131 exposed in the channel region 142. Since the doped semiconductor layer 14 is provided before forming the second metal layer 15 in this embodiment, it is necessary to conduct the first transparent conductive layer 12 before forming the doped semiconductor layer 14.
  • the first transparent conductive layer 12 is then subjected to a conductor treatment, and then a negative photoresist layer 100 is formed on the surface of the first transparent conductive layer 12.
  • the first transparent conductive layer 12 is then subjected to a conductor treatment, and then a semiconductor layer 13 and a positive photoresist layer 200 are sequentially formed on the first insulating layer 101.
  • the first transparent conductive layer 12 is then subjected to a conductor treatment.
  • the first transparent conductive layer 12 is first subjected to a conductor treatment, so that all the first transparent conductive layers 12 can be subjected to a conductor treatment, that is, the first conductive portion 122 can also be subjected to a conductor treatment to reduce the impedance of the first conductive portion 122.
  • the first transparent conductive layer 12 may also be made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO), thereby eliminating the need for a conductor treatment process.
  • a second insulating layer 102 is formed on the first insulating layer 101, and the second insulating layer 102 does not need to have holes in the regions corresponding to the first electrode 121 and the second conductive portion 153.
  • the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • a second transparent conductive layer 16 is formed on the second insulating layer 102, and the second transparent conductive layer 16 is etched.
  • the second transparent conductive layer 16 forms a patterned second electrode 161, and the second electrode 161 is a common electrode.
  • the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the first conductive portion 122 is directly used as the drain, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122. Therefore, the second transparent conductive layer 16 does not need to form a third conductive portion 162, and the second insulating layer 102 does not need to open holes in the area corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • the first conductive part 122 is directly used as the drain in this embodiment, and the impedance of the drain is relatively large, but the second transparent conductive layer 16 does not need to form the third conductive part 162, and it is not necessary to open holes in the second insulating layer 102 corresponding to the first electrode 121 and the second conductive part 153, which can simplify the manufacturing process.
  • the first transparent conductive layer 12 is firstly subjected to a conductor treatment, so that all the first transparent conductive layers 12 can be subjected to a conductor treatment, that is, the first conductive part 122 can also be subjected to a conductor treatment to reduce the impedance of the first conductive part 122.
  • the display panel provided in the second embodiment of the present invention is basically the same as the display panel in the first embodiment ( Figure 3), except that, in the present embodiment: the display panel includes the array substrate as described above, an opposing substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the opposing substrate 20.
  • the array substrate further includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second transparent conductive layer 16 includes a second electrode 161, the second electrode 161 is a common electrode, the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the first conductive portion 122 is directly used as the drain, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122. Therefore, the second transparent conductive layer 16 does not need to form a third conductive portion 162, and the second insulating layer 102 does not need to open holes in the area corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • FIG8 is a schematic diagram of the cross-sectional structure of the array substrate in the third embodiment of the present invention.
  • the array substrate provided in the third embodiment of the present invention is substantially the same as the array substrates in the first embodiment (FIG. 1) and the second embodiment (FIG. 4), except that, in the present embodiment:
  • the first conductive portion 122 and the second conductive portion 153 are conductively connected to each other.
  • the first conductive portion 122 and the second conductive portion 153 serve as a drain electrode.
  • the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122 and the second conductive portion 153 .
  • the array substrate further includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second transparent conductive layer 16 includes a second electrode 161, the second electrode 161 is a common electrode, the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the second transparent conductive layer 16 does not need to form a third conductive portion 162, and the second insulating layer 102 does not need to open holes in the areas corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • the first conductive portion 122 and the second conductive portion 153 are directly conductively connected, so that the second transparent conductive layer 16 does not need to form the third conductive portion 162, and there is no need to open holes in the second insulating layer 102 corresponding to the first electrode 121 and the second conductive portion 153, thereby simplifying the manufacturing process and having little effect on the impedance of the drain.
  • 9a-9b are cross-sectional schematic diagrams of a method for manufacturing an array substrate in Embodiment 3 of the present invention.
  • the manufacturing method provided in Embodiment 3 of the present invention is substantially the same as the manufacturing method in Embodiment 1 (FIGS. 2a to 2p) and Embodiment 2 (FIGS. 5 to 7), except that, in this embodiment:
  • a doped semiconductor layer 14 is formed on the semiconductor layer 13, that is, the semiconductor layer 13, the doped semiconductor layer 14 and the positive photoresist layer 200 are sequentially formed on the first insulating layer 101.
  • the positive photoresist layer 200 is subjected to photolithography (exposure, development) from the side of the substrate 10 away from the positive photoresist layer 200 (the back side of the substrate 10), and the positive photoresist layer 200 forms a patterned positive photoresist pattern layer 210, and the positive photoresist pattern layer 210 corresponds to the scan line 111 and the gate 112, that is, the positive photoresist layer 200 corresponding to the scan line 111 and the gate 112 is retained.
  • photolithography exposure, development
  • the semiconductor layer 13 is etched and the doped semiconductor layer 14 is first etched using the positive photoresist pattern layer 210 as a shield, and the semiconductor layer 13 forms an active layer 131 corresponding to the scan line 111 and the gate 112.
  • the doped semiconductor layer 14 is first etched using the positive photoresist pattern layer 210 as a shield, so that when the second metal layer 15 is formed, the second metal layer 15 can be in direct contact with the first transparent conductive layer 12.
  • the doped semiconductor layer 14 is etched for the second time with the second photoresist pattern layer 320 as a shield, and the doped semiconductor layer 14 forms a doped semiconductor pattern layer 141.
  • the doped semiconductor pattern layer 141 is disconnected in the channel region 142, and the first conductive portion 122 and the second conductive portion 153 are conductively connected.
  • a second insulating layer 102 is formed on the first insulating layer 101, and the second insulating layer 102 does not need to have holes in the regions corresponding to the first electrode 121 and the second conductive portion 153.
  • the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • a second transparent conductive layer 16 is formed on the second insulating layer 102, and the second transparent conductive layer 16 is etched.
  • the second transparent conductive layer 16 forms a patterned second electrode 161, and the second electrode 161 is a common electrode.
  • the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 has a comb-like structure in the area corresponding to the first electrode 121, so as to form a horizontal electric field with the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the first conductive portion 122 and the second conductive portion 153 are used as drains, and the first conductive portion 122 and the second conductive portion 153 are directly conductively connected, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122 and the second conductive portion 153. Therefore, the second transparent conductive layer 16 does not need to form the third conductive portion 162, and the second insulating layer 102 does not need to have holes in the areas corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • the doped semiconductor layer 14 when etching the semiconductor layer 13, the doped semiconductor layer 14 is first etched using the positive photoresist pattern layer 210 as a shield, so that the first conductive portion 122 and the second conductive portion 153 can be directly conductively connected, so that the second transparent conductive layer 16 does not need to form the third conductive portion 162, and there is no need to open holes in the second insulating layer 102 corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process and has little effect on the impedance of the drain.
  • the display panel provided in the third embodiment of the present invention is basically the same as the display panels in the first embodiment ( Figure 3) and the second embodiment, except that, in the present embodiment: the display panel includes the array substrate as described above, an opposing substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the opposing substrate 20.
  • the array substrate further includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second transparent conductive layer 16 includes a second electrode 161, which is a common electrode.
  • the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located below the common electrode.
  • the second electrode 161 is a comb-shaped structure in the area corresponding to the first electrode 121, so as to facilitate the formation of a horizontal electric field between the second electrode 121 and the first electrode 121 to form a fringe field switching mode (Fringe Field Switching, FFS).
  • FFS fringe field switching mode
  • the first conductive portion 122 and the second conductive portion 153 are directly conductively connected, the first conductive portion 122 and the second conductive portion 153 serve as a drain together, and the first electrode 121 is conductively connected to the active layer 131 through the first conductive portion 122 and the second conductive portion 153, the second transparent conductive layer 16 does not need to form the third conductive portion 162, and the second insulating layer 102 does not need to have holes in the areas corresponding to the first electrode 121 and the second conductive portion 153, which can simplify the manufacturing process.
  • FIG10 is a schematic diagram of the cross-sectional structure of the array substrate in the fourth embodiment of the present invention.
  • FIG11 is a schematic diagram of the plan view of the array substrate in the fourth embodiment of the present invention.
  • the array substrate provided in the fourth embodiment of the present invention is substantially the same as the array substrates in the first embodiment (FIG. 1), the second embodiment (FIG. 4), and the third embodiment (FIG. 8), except that, in the present embodiment:
  • the first electrode 121 is a common electrode, and the first electrode 121 and the first conductive part 122 are insulated from each other.
  • the array substrate also includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second insulating layer 102 is provided with a contact hole H in the region corresponding to the second conductive part 153.
  • the second transparent conductive layer 16 includes a second electrode 161 and a third conductive part 162, the second electrode 161 is a pixel electrode, the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located above the common electrode.
  • the third conductive part 162 is conductively connected to the second electrode 161, and the third conductive part 162 is conductively connected to the second conductive part 153 through the contact hole H, that is, in this embodiment, the second conductive part 153 serves as a drain.
  • the first electrode 121 is a common electrode
  • the second electrode 161 is a pixel electrode, so that the pixel electrode is located above the common electrode to form another fringe field switching mode (Fringe Field Switching, FFS).
  • FFS Frringe Field Switching
  • Figures 12a to 12c are schematic diagrams of a method for manufacturing an array substrate in a fourth embodiment of the present invention.
  • the manufacturing method provided in the fourth embodiment of the present invention is basically the same as the manufacturing method in the first embodiment ( Figures 2a to 2p), the second embodiment ( Figures 5 to 7), and the third embodiment ( Figures 9a to 9b), except that, in this embodiment:
  • the preparation method also includes:
  • a doped semiconductor layer 14, a second metal layer 15, and a photoresist layer 300 are sequentially formed above the first transparent conductive layer 12 and the semiconductor layer 13.
  • the second mask process uses a half-tone mask 400 (Half Tone Mask) as a shield, and performs photolithography on the photoresist layer 300 from the side of the half-tone mask 400 away from the substrate 10 (the front side of the substrate 10), and the photoresist layer 300 forms a patterned first photoresist pattern layer 310, and the first photoresist pattern layer 310 includes a completely photoetched non-photoresist pattern area 311, a partially photoetched half-photoresist pattern layer 312, and a non-photoetched full-photoresist pattern layer 313.
  • the pattern of the halftone mask 400 in this embodiment is different from the pattern of the halftone mask 400 in the first embodiment.
  • a light-transmitting area 410 is provided between the semi-transmitting area 420 in the area corresponding to the first electrode 121 and the non-transmitting area 430 in the area corresponding to the first conductive part 122, so that on the first photoresist pattern layer 310, a non-photoresist pattern area 311 is provided between the semi-photoresist pattern layer 312 in the area corresponding to the first electrode 121 and the full photoresist pattern layer 313 in the area corresponding to the first conductive part 122, so that when the first metal layer 15 is etched for the first time with the first photoresist pattern layer 310 as a shield, the first electrode 121 and the first conductive part 122 can be disconnected.
  • the first photoresist pattern layer 310 is used as a shield, and the second metal layer 15 is etched for the first time, the doped semiconductor layer 14 is etched for the first time, and the first transparent conductive layer 12 is etched for the second time in sequence.
  • the first transparent conductive layer 12 forms a patterned first electrode 121 and a first conductive portion 122, and the first conductive portion 122 is conductively connected to the active layer 131.
  • the first electrode 121 is a common electrode, and the first electrode 121 and the first conductive portion 122 are insulated from each other.
  • the half photoresist pattern layer 312 is removed by a photoresist ashing process, and a portion of the full photoresist pattern layer 313 is retained, and the first photoresist pattern layer 310 forms a second photoresist pattern layer 320.
  • the second photoresist pattern layer 320 as a shield, the second metal layer 15 is etched for the second time and the doped semiconductor layer 14 is etched for the second time in sequence.
  • the second metal layer 15 forms a data line 151, a source electrode 152, and a second conductive portion 153, exposing the first electrode 121 and the active layer 131 of the channel region 142, and the data line 151 is conductively connected to the source electrode 152.
  • a second insulating layer 102 is formed on the first insulating layer 101, and the second insulating layer 102 is etched to form a contact hole H in a region corresponding to the second conductive portion 153.
  • the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.
  • a second transparent conductive layer 16 is formed on the second insulating layer 102, and the second transparent conductive layer 16 is etched to form a patterned second electrode 161 and a third conductive portion 162.
  • the second electrode 161 is a pixel electrode, and the first electrode 121 (common electrode) and the second electrode 161 (pixel electrode) are insulated from each other, and the pixel electrode is located above the common electrode.
  • the third conductive portion 162 is conductively connected to the second electrode 161, and the third conductive portion 162 is conductively connected to the second conductive portion 153 through the contact hole H, that is, in this embodiment, the second conductive portion 153 serves as a drain.
  • the first electrode 121 is a common electrode
  • the second electrode 161 is a pixel electrode, so that the pixel electrode is located above the common electrode to form another fringe field switching mode (Fringe Field Switching, FFS).
  • FFS Frringe Field Switching
  • FIG13 is a schematic diagram of the cross-sectional structure of the display panel in the fourth embodiment of the present invention.
  • the display panel provided in the fourth embodiment of the present invention is substantially the same as the display panels in the first embodiment (FIG. 3), the second embodiment, and the third embodiment, except that, in the present embodiment: the display panel includes the array substrate as described above, the opposing substrate 20 disposed opposite to the array substrate, and the liquid crystal layer 30 disposed between the array substrate and the opposing substrate 20.
  • the first electrode 121 on the array substrate is a common electrode, the first electrode 121 and the first conductive portion 122 are insulated from each other, and the second electrode 161 is a pixel electrode, so that the pixel electrode is located above the common electrode to form another fringe field switching mode (Fringe Field Switching, FFS).
  • the array substrate also includes a second insulating layer 102 disposed above the first insulating layer 101 and a second transparent conductive layer 16 disposed above the second insulating layer 102.
  • the second insulating layer 102 is provided with a contact hole H in the region corresponding to the second conductive portion 153.
  • the second transparent conductive layer 16 includes a second electrode 161 and a third conductive portion 162.
  • the second electrode 161 is a pixel electrode.
  • the first electrode 121 and the second electrode 161 are insulated from each other, that is, the pixel electrode and the common electrode are insulated from each other, and the pixel electrode is located above the common electrode.
  • the third conductive portion 162 is conductively connected to the second electrode 161, and the third conductive portion 162 is conductively connected to the second conductive portion 153 through the contact hole H, that is, in this embodiment, the second conductive portion 153 serves as a drain.
  • the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second” used in this document are only used to distinguish names and are not used to limit quantity and order.
  • the first transparent conductive layer is etched for the first time and the semiconductor layer is etched respectively, and then using a half-tone mask, the first transparent conductive layer is etched for the second time and the second metal layer is etched twice, thereby reducing the number of masks, simplifying the manufacturing process, and reducing the manufacturing cost; and after etching the second metal layer twice, the first transparent conductive layer is still retained under the data line, the source electrode, and the second conductive part, thereby reducing the impedance of the data line, the source electrode, and the second conductive part.

Abstract

本发明公开了一种阵列基板的制作方法及阵列基板，该制作方法包括：在基底上形成扫描线和栅极，覆盖扫描线和栅极的第一绝缘层；在第一绝缘层上形成第一透明导电层和负性光阻层，对负性光阻层进行背面光刻处理，再对第一透明导电层进行第一次蚀刻；在第一绝缘层上依次形成半导体层和正性光阻层，对正性光阻层进行背面光刻处理，再对半导体层进行蚀刻；在第一透明导电层和半导体层上依次形成第二金属层和光阻层，采用半色调掩膜版对光阻层进行正面光刻处理，先对第二金属层进行第一次蚀刻以及对第一透明导电层进行第二次蚀刻，除去半光阻图案层后，再对第二金属层进行第二次蚀刻。从而可以减少掩膜版的数量，简化制作工艺，降低制作成本。

Description

阵列基板的制作方法及阵列基板 技术领域
本发明涉及显示器技术领域，特别是涉及一种阵列基板的制作方法及阵列基板。
 背景技术
随着显示技术的发展，轻薄化的显示面板倍受消费者的喜爱，尤其是轻薄化的显示面板(liquid crystal display，LCD)。
现有的一种显示装置包括薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、彩膜基板(Color Filter Substrate，CF Substrate)以及填充在薄膜晶体管阵列基板和彩膜基板之间的液晶分子，上述显示装置工作时，在薄膜晶体管阵列基板的像素电极与彩膜基板的公共电极分别施加驱动电压或者在薄膜晶体管阵列基板的公共电极和像素电极分别施加驱动电压，控制两个基板之间的液晶分子的旋转方向，以将显示装置的背光模组提供的背光折射出来，从而显示画面。
 技术问题
现有技术中薄膜晶体管阵列基板的制作工艺比较复杂，例如：在制作扫描线和栅极时需要第一道掩膜工艺；在制作有源层时需要第二道掩膜工艺；在制作像素电极时需要第三道掩膜工艺；在制作数据线、源极和漏极时需要第四道掩膜工艺；在对绝缘层进行开孔时需要第五道掩膜工艺；在制作公共电极时需要第六道掩膜工艺。因此，现有技术中在制作薄膜晶体管阵列基板时，至少需要使用六道掩膜工艺，需要六种掩膜版，制作工艺复杂，制作时间较长，成本较高。
 技术解决方案
为了克服现有技术中存在的缺点和不足，本发明的目的在于提供一种阵列基板的制作方法及阵列基板，以解决现有技术中阵列基板制作工艺复杂的问题。
本发明的目的通过下述技术方案实现：
本发明提供一种阵列基板的制作方法，包括：
提供基底；
在所述基底的上方形成第一金属层，对所述第一金属层进行蚀刻，所述第一金属层形成图案化的扫描线和栅极，所述栅极与所述扫描线导电连接；
在所述基底的上方形成覆盖所述扫描线和所述栅极的第一绝缘层；
在所述第一绝缘层的上方依次形成第一透明导电层和负性光阻层，以所述第一金属层为掩模版，从所述基底远离所述负性光阻层一侧对所述负性光阻层进行光刻处理，除去与所述扫描线和所述栅极对应区域的所述负性光阻层，所述负性光阻层形成图案化的负性光阻图案层，以所述负性光阻图案层为遮挡，对所述第一透明导电层进行第一次蚀刻，除去与所述扫描线和所述栅极对应区域的所述第一透明导电层；
在所述第一绝缘层的上方依次形成半导体层和正性光阻层，以所述第一金属层为掩模版，从所述基底远离所述正性光阻层一侧对所述正性光阻层进行光刻处理，所述正性光阻层形成图案化的正性光阻图案层，所述正性光阻图案层与所述扫描线和所述栅极相对应，以所述正性光阻图案层为遮挡，对所述半导体层进行蚀刻，所述半导体层形成与所述扫描线和所述栅极对应的有源层；
在所述第一透明导电层和所述半导体层的上方依次形成第二金属层和光阻层，采用半色调掩膜版为遮挡，从所述半色调掩膜版远离所述基底一侧对所述光阻层进行光刻处理，所述光阻层形成图案化的第一光阻图案层，所述第一光阻图案层包括完全被光刻掉的无光阻图案区、部分被光刻掉的半光阻图案层以及未被光刻掉的全光阻图案层；
以所述第一光阻图案层为遮挡，对所述第二金属层进行第一次蚀刻以及对所述第一透明导电层进行第二次蚀刻，所述第一透明导电层形成图案化的第一电极和第一导电部，所述第一导电部与所述有源层导电连接；
采用光阻灰化工艺除去所述半光阻图案层，所述第一光阻图案层形成所述第二光阻图案层，以所述第二光阻图案层为遮挡，对所述第二金属层进行第二次蚀刻，所述第二金属层形成数据线、源极以及第二导电部，且露出所述第一电极和所述沟道区的所述有源层，所述数据线与所述源极导电连接，所述第一导电部和所述第二导电部至少其中之一为漏极，所述第一电极和所述有源层的沟道区均与所述半光阻图案区相对应，所述数据线、所述源极以及所述第二导电部均与所述全光阻图案层相对应。
进一步地，所述制作方法还包括：
在对所述半导体层进行蚀刻之后，先在所述第一透明导电层和所述半导体层的上方形成掺杂半导体层，再在所述掺杂半导体层的上方依次形成所述第二金属层和所述光阻层；
对所述第二金属层进行第一次蚀刻之后，以所述第一光阻图案层为遮挡，对所述掺杂半导体层进行第一次蚀刻；
对所述第二金属层进行第二次蚀刻之后，以所述第二光阻图案层为遮挡，对所述掺杂半导体层进行第二次蚀刻，所述掺杂半导体层形成图案化的掺杂半导体图案层，所述掺杂半导体图案层在所述沟道区断开。
进一步地，所述制作方法还包括：
在形成所述半导体层之后，先在所述半导体层的上方形成掺杂半导体层，再在所述掺杂半导体层的上方形成所述正性光阻层；
对所述半导体层进行蚀刻之前，先以所述正性光阻图案层为遮挡，对所述掺杂半导体层进行第一次蚀刻；
对所述第二金属层进行第二次蚀刻之后，再以所述第二光阻图案层为遮挡，对所述掺杂半导体层进行第二次蚀刻，所述掺杂半导体层形成掺杂半导体图案层，所述掺杂半导体图案层在所述沟道区断开，所述第一导电部和所述第二导电部导电连接。
进一步地，所述第一电极为像素电极，所述第一电极和所述第一导电部导电连接。
进一步地，所述制作方法还包括：
在所述第一绝缘层的上方形成第二绝缘层，对所述第二绝缘层进行蚀刻，所述第二绝缘层在对应所述第一电极和所述第二导电部的区域形成接触孔；
在所述第二绝缘层上方形成第二透明导电层，对所述第二透明导电层进行蚀刻，所述第二透明导电层形成图案化的第二电极和第三导电部，所述第二电极为公共电极，所述第三导电部和所述第一电极均与所述第二电极相互绝缘，所述第三导电部通过所述接触孔将所述第一电极和所述第二导电部导电连接。
进一步地，所述第一电极为公共电极，所述第一电极和所述第一导电部相互绝缘，所述制作方法还包括：
在所述第一绝缘层的上方形成第二绝缘层，对所述第二绝缘层进行蚀刻并在对应所述第二导电部的区域形成有接触孔；
在所述第二绝缘层的上方形成第二透明导电层，对所述第二透明导电层进行蚀刻，所述第二透明导电层形成图案化的第二电极和第三导电部，所述第二电极为像素电极，所述第三导电部与所述第二电极导电连接，所述第二电极与所述第一电极相互绝缘，所述第三导电部通过所述接触孔与所述第二导电部导电连接。
进一步地，所述第一透明导电层采用金属氧化物半导体材料，所述制作方法还包括：
在形成所述第二金属层之前，先对所述第一透明导电层进行导体化处理；
在对所述第二金属层进行第二次蚀刻之后，采用氢掺杂工艺对所述沟道区露出的所述有源层进行氢通道处理。
进一步地，所述第一透明导电层采用金属氧化物半导体材料，所述制作方法还包括：
在对所述第二金属层进行第二次蚀刻之后，再对所述第一透明导电层进行导体化处理。
进一步地，所述制作方法还包括：
采用氢掺杂工艺对所述第一透明导电层进行导体化处理，以及对所述沟道区露出的所述有源层进行氢通道处理。
本申请还提供一种阵列基板，采用如上所述的制作方法制作而成，所述阵列基板包括：
基底；
设于所述基底上方的第一金属层，所述第一金属层包括扫描线和栅极，所述栅极与所述扫描线导电连接；
设于所述第一金属层上方的第一绝缘层，所述第一绝缘层覆盖所述扫描线和所述栅极；
设于所述第一绝缘层上方的第一透明导电层和半导体层，所述第一透明导电层包括第一电极和第一导电部，所述半导体层包括有源层，所述第一导电部与所述有源层导电连接；
设于所述第一透明导电层和所述半导体层上方的第二金属层，所述第二金属层包括数据线、源极以及第二导电部，所述数据线与所述源极导电连接，所述第一导电部和所述第二导电部至少其中之一为漏极。
进一步地，所述阵列基板还包括设于所述半导体层和所述第二金属层之间的掺杂半导体层，所述掺杂半导体层包括图案化的掺杂半导体图案层，所述掺杂半导体图案层在所述有源层的沟道区断开。
进一步地，所述第一电极为像素电极，所述第一电极和所述第一导电部导电连接。
进一步地，所述阵列基板还包括：
设于所述第一绝缘层上方的第二绝缘层，所述第二绝缘层在对应所述第一电极和所述第二导电部的区域设有接触孔；
设于所述第二绝缘层上方的第二透明导电层，所述第二透明导电层包括第二电极和第三导电部，所述第二电极为公共电极，所述第三导电部和所述第一电极均与所述第二电极相互绝缘，所述第三导电部通过所述接触孔将所述第一电极和所述第二导电部导电连接。
进一步地，所述第二导电部与所述第一导电部导电连接。
进一步地，所述第一电极为公共电极，所述第一电极和所述第一导电部相互绝缘，所述阵列基板还包括：
设于所述第一绝缘层上方的第二绝缘层，所述第二绝缘层在对应所述第二导电部的区域设有接触孔；
设于所述第二绝缘层上方的第二透明导电层，所述第二透明导电层包括第二电极和第三导电部，所述第二电极为像素电极，所述第三导电部与所述第二电极导电连接，所述第一电极与所述第二电极相互绝缘，所述第三导电部通过所述接触孔与所述第二导电部导电连接。
 有益效果
通过以第一金属层为掩模版，利用背面曝光方式，搭配负型光阻和正型光阻的交替使用，从而分别对第一透明导电层进行第一次蚀刻以及对半导体层进行蚀刻，再利用半色调掩膜版，从而对第一透明导电层进行第二次蚀刻以及对第二金属层进行两次蚀刻，从而可以减少掩膜版的数量，简化制作工艺，降低制作成本；而且对第二金属层进行两次蚀刻后，数据线、源极以及第二导电部的下方依然会保留第一透明导电层，从而可以降低数据线、源极以及第二导电部的阻抗。
 附图说明
图1是本发明实施例一中阵列基板的截面示意图。
图2a至2p是本发明实施例一中阵列基板的制作方法的示意图。
图3是本发明实施例一中显示面板的截面结构示意图。
图4是本发明实施例二中阵列基板的截面结构示意图。
图5是本发明实施例二中阵列基板的平面示意图。
图6是本发明实施例二中阵列基板的制作方法的截面示意图之一。
图7是本发明实施例二中阵列基板的制作方法的截面示意图之二。
图8是本发明实施例三中阵列基板的截面结构示意图。
[根据细则26改正 31.05.2023]
图9a至9b是本发明实施例三中阵列基板的制作方法的截面示意图。
图10是本发明实施例四中阵列基板的截面结构示意图。
图11是本发明实施例四中阵列基板的平面示意图。
图12a至12c是本发明实施例四中阵列基板的制作方法的示意图。
图13是本发明实施例四中显示面板的截面结构示意图。
 本发明的实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的阵列基板的制作方法及阵列基板的具体实施方式、结构、特征及其功效，详细说明如下：
[实施例一]
图1是本发明实施例一中阵列基板的截面示意图。如图1所示，本发明实施例一提供的一种阵列基板，该阵列基板包括：基底10，基底10可以由玻璃、石英、硅、丙烯酸或聚碳酸酯等材料制成，基底10也可为柔性基板，用于柔性基板的适当材料包括例如聚醚砜(PES)、聚萘二甲酸乙二醇酯(PEN)、聚乙烯(PE)、聚酰亚胺(PI)、聚氯乙烯(PVC)、聚对苯二甲酸乙二醇酯(PET)或其组合。
设于基底10上方的第一金属层11，第一金属层11直接设于基底10的上表面，第一金属层11包括扫描线111和栅极112，栅极112与扫描线111导电连接。本实施例中，扫描线111的其中一部分作为栅极112，即栅极112与扫描线111位于同一直线上，从而可以增加像素的开口率。其中，第一金属层11可以采用金属例如铜(Cu)、银(Ag)、铬(Cr)、钼(Mo)、铝(Al)、钛(Ti)、锰(Mn)、镍(Ni)等，或者采用上述金属的组合例如Al/Mo、Cu/Mo等。当然，在其他实施例中，栅极112也可以与扫描线111不在同一直线上，即栅极112凸出于扫描线111进行设置，在此不作限制。
设于第一金属层11上方的第一绝缘层101，第一绝缘层101直接设于基底10和第一金属层11的上表面并覆盖扫描线111和栅极112。其中，第一绝缘层101为栅极绝缘层，第一绝缘层101的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
设于第一绝缘层101上方的第一透明导电层12和半导体层13，第一透明导电层12包括第一电极121和第一导电部122，半导体层13包括有源层131，第一导电部122与有源层131导电连接。其中，半导体层13采用非晶硅(a-Si)材料；第一透明导电层12可以采用金属氧化物半导体材料，但需要通过对金属氧化物半导体进行导体化处理，例如采用等离子体进行处理，离子轰击、氢(H2)掺杂、氦(He)掺杂以及氩(Ar)掺杂等方式，使第一透明导电层12的部分区域实现导体化，经过导体化处理的第一透明导电层12，其阻抗低于导体化处理前的阻抗，与氧化铟锡(ITO)或氧化铟锌(IZO)的阻抗相当。金属氧化物半导体优选采用透明金属氧化物半导体材料制成，例如铟锌氧化物(InZnO)、铟镓氧化物(InGaO)、铟锡氧化物(InSnO)、锌锡氧化物(ZnSnO)、镓锡氧化物(GaSnO)、镓锌氧化物(GaZnO)、铟镓锌氧化物(IGZO)或铟镓锌锡氧化物(IGZTO)等制成。当然，在其他实施例中，第一透明导电层12也可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明电极制成，从而无需导体化处理的工艺。
设于第一透明导电层12和半导体层13上方的第二金属层15(图2h)，第二金属层15包括数据线151、源极152以及第二导电部153，数据线151与源极152导电连接，第一导电部122和第二导电部153至少其中之一为漏极。其中，第二金属层15可以采用金属例如铜(Cu)、银(Ag)、铬(Cr)、钼(Mo)、铝(Al)、钛(Ti)、锰(Mn)、镍(Ni)等，或者采用上述金属的组合例如Al/Mo、Cu/Mo等。
本实施例中，阵列基板还包括设于半导体层13和第二金属层15之间的掺杂半导体层14(图2h)，掺杂半导体层14包括图案化的掺杂半导体图案层141，掺杂半导体图案层141在有源层131的沟道区142断开。数据线151、源极152以及第二导电部153均与掺杂半导体图案层141相对应，即数据线151、源极152以及第二导电部153共同在基底10上的投影与掺杂半导体图案层141相重合。掺杂半导体层14采用掺杂非晶硅(N+a-Si)材料，从而使得源极152和漏极可更好地与有源层131进行电性连接。
本实施例中，第一电极121为像素电极，第一电极121和第一导电部122导电连接。
进一步地，阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二绝缘层102在对应第一电极121和第二导电部153的区域设有接触孔H。第二透明导电层16包括第二电极161和第三导电部162，第二电极161为公共电极，第三导电部162和第一电极121均与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。第三导电部162通过接触孔H将第一电极121和第二导电部153导电连接，即本实施例中，第一导电部122和第二导电部153均为漏极。通过将第一导电部122和第二导电部153均作为漏极，并通过第三导电部162将第一电极121和第二导电部153导电连接，从而可以降低漏极的阻抗。其中，第二绝缘层102的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合；第二透明导电层16采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明电极制成。在其他实施例中，阵列基板上也可不用设置公共电极，公共电极设于彩膜基板20上，以形成TN或VA显示模式。当然，也可以不用设置第二透明导电层16，直接以第一导电部122为漏极，第一电极121通过第一导电部122与有源层131导电连接。
其中，基底10朝向第一金属层11的一侧为上方向(或正面)，基底10远离第一金属层11的一侧为下方向(或背面)。
图2a至2p是本发明实施例一中阵列基板的制作方法的示意图。如图2a至图2p所示，本实施例还提供一种阵列基板的制作方法，该制作方法用于制作上述阵列基板，该制作方法包括：如图2a-1和图2a-2所示，提供基底10，基底10可以由玻璃、石英、硅、丙烯酸或聚碳酸酯等材料制成，基底10也可为柔性基板，用于柔性基板的适当材料包括例如聚醚砜(PES)、聚萘二甲酸乙二醇酯(PEN)、聚乙烯(PE)、聚酰亚胺(PI)、聚氯乙烯(PVC)、聚对苯二甲酸乙二醇酯(PET)或其组合。
在基底10的上方形成第一金属层11，第一金属层11设于直接在基底10的上表面。采用第一道掩膜工艺对第一金属层11进行蚀刻，第一金属层11形成图案化的扫描线111和栅极112，栅极112与扫描线111导电连接。其中，第一金属层11可以采用金属例如铜(Cu)、银(Ag)、铬(Cr)、钼(Mo)、铝(Al)、钛(Ti)、锰(Mn)、镍(Ni)等，或者采用上述金属的组合例如Al/Mo、Cu/Mo等。
在基底10的上方形成覆盖扫描线111和栅极112的第一绝缘层101，第一绝缘层101直接设于基底10和第一金属层11的上表面并覆盖扫描线111和栅极112。其中，第一绝缘层101为栅极绝缘层，第一绝缘层101的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。如图2b至图2d-2所示，在第一绝缘层101的上方依次形成第一透明导电层12和负性光阻层100。以第一金属层11为掩模版，从基底10远离负性光阻层100一侧(基底10的背面)对负性光阻层100进行光刻处理(曝光、显影)，以除去与扫描线111和栅极112对应区域的负性光阻层100，负性光阻层100形成图案化的负性光阻图案层110。以负性光阻图案层110为遮挡，对第一透明导电层12进行第一次蚀刻，除去与扫描线111和栅极112对应区域的第一透明导电层12。其中，第一透明导电层12采用金属氧化物半导体材料，但需要通过对金属氧化物半导体进行导体化处理，例如采用等离子体进行处理，离子轰击、氢(H2)掺杂、氦(He)掺杂以及氩(Ar)掺杂等方式，使第一透明导电层12的部分区域或全部区域实现导体化，经过导体化处理的第一透明导电层12，其阻抗低于导体化处理前的阻抗，与氧化铟锡(ITO)或氧化铟锌(IZO)的阻抗相当。金属氧化物半导体优选采用透明金属氧化物半导体材料制成，例如铟锌氧化物(InZnO)、铟镓氧化物(InGaO)、铟锡氧化物(InSnO)、锌锡氧化物(ZnSnO)、镓锡氧化物(GaSnO)、镓锌氧化物(GaZnO)、铟镓锌氧化物(IGZO)或铟镓锌锡氧化物(IGZTO)等制成。当然，在其他实施例中，第一透明导电层12也可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明电极制成，从而无需导体化处理的工艺。
如图2e至图2g-2所示，在第一绝缘层101的上方依次形成半导体层13和正性光阻层200。以第一金属层11为掩模版，从基底10远离正性光阻层200一侧(基底10的背面)对正性光阻层200进行光刻处理(曝光、显影)，正性光阻层200形成图案化的正性光阻图案层210，正性光阻图案层210与扫描线111和栅极112相对应，即与保留扫描线111和栅极112对应区域的正性光阻层200，扫描线111和栅极112共同在基底10上的投影与正性光阻图案层210相重合。以正性光阻图案层210为遮挡，对半导体层13进行蚀刻，半导体层13形成与扫描线111和栅极112对应的有源层131，即扫描线111和栅极112共同在基底10上的投影与有源层131相重合。其中，只有栅极112对应区域的有源层131具有开关特性，半导体层13采用非晶硅(a-Si)材料。
其中，可以先对第一透明导电层12进行第一次蚀刻之后，再在第一绝缘层101的上方依次形成半导体层13和正性光阻层200；也可以先对半导体层13进行蚀刻并形成有源层131之后，再在第一绝缘层101的上方依次形成第一透明导电层12和负性光阻层100，两次蚀刻工艺的顺序可以调整。
本实施例中，阵列基板还包括设于半导体层13和第二金属层15之间的掺杂半导体层14。如图2h-2i所示，在第一透明导电层12和半导体层13的上方依次形成掺杂半导体层14、第二金属层15以及光阻层300。第二道掩膜工艺采用半色调掩膜版400(Half Tone Mask)为遮挡，从半色调掩膜版400远离基底10一侧(基底10的正面)对光阻层300进行光刻处理，光阻层300形成图案化的第一光阻图案层310，第一光阻图案层310包括完全被光刻掉的无光阻图案区311、部分被光刻掉的半光阻图案层312以及未被光刻掉的全光阻图案层313。其中，掺杂半导体层14采用掺杂非晶硅(N+a-Si)材料，第二金属层15可以采用金属例如铜(Cu)、银(Ag)、铬(Cr)、钼(Mo)、铝(Al)、钛(Ti)、锰(Mn)、镍(Ni)等，或者采用上述金属的组合例如Al/Mo、Cu/Mo等。
光阻层300采用正性光阻，半色调掩膜版400包括透光区410、半透光区420以及非透光区430，光阻层300在对应透光区410的区域完全被光刻掉，并形成无光阻图案区311；光阻层300在对应半透光区420的区域部分被光刻掉，并形成半光阻图案层312；光阻层300在对应非透光区430的区域未被光刻掉，并形成全光阻图案层313。当然，光阻层300也可以采用负性光阻，只是半色调掩膜版400上透光区410和不透光430区的图案相反，光阻层300在对应透光区410的区域未被光刻掉，并形成全光阻图案层313；光阻层300在对应半透光区420的区域部分被光刻掉，并形成半光阻图案层312；光阻层300在对应非透光区430的区域完全被光刻掉，并形成无光阻图案区311。
如图2j-1和图2j-2所示，以第一光阻图案层310为遮挡，依次对第二金属层15进行第一次蚀刻、对掺杂半导体层14进行第一次蚀刻以及对第一透明导电层12进行第二次蚀刻。第一透明导电层12形成图案化的第一电极121和第一导电部122，第一导电部122与有源层131导电连接。本实施例中，第一电极121为像素电极，第一电极121和第一导电部122导电连接，即第一导电部122作为漏极。
如图2k至图2l-2所示，采用光阻灰化工艺除去半光阻图案层312，并保留部分全光阻图案层313，第一光阻图案层310形成第二光阻图案层320。以第二光阻图案层320为遮挡，依次对第二金属层15进行第二次蚀刻以及对掺杂半导体层14进行第二次蚀刻。第二金属层15形成数据线151、源极152以及第二导电部153，且露出第一电极121和沟道区142的有源层131，数据线151与源极152导电连接。掺杂半导体层14形成图案化的掺杂半导体图案层141，掺杂半导体图案层141在沟道区142断开，数据线151、源极152以及第二导电部153均与掺杂半导体图案层141相对应，即数据线151、源极152以及第二导电部153共同在基底10上的投影与掺杂半导体图案层141相重合。通过形成掺杂半导体图案层141，从而使得源极152和漏极可更好地与有源层131进行电性连接，而且数据线151下方保留的掺杂半导体层14和第一透明导电层12可以降低数据线151的阻抗。其中，第一电极121和有源层131的沟道区142均与半光阻图案区312相对应，数据线151、源极152以及第二导电部153均与全光阻图案层313相对应。
如图2m-1和图2m-2所示，本实施例中，第一透明导电层12采用金属氧化物半导体材料，在对第二金属层15进行第二次蚀刻之后，接着对第一透明导电层12进行导体化处理，从而使得第一电极121导体化。例如采用等离子体进行处理，离子轰击、氢(H2)掺杂、氦(He)掺杂以及氩(Ar)掺杂等方式，使第一透明导电层12的部分区域或全部区域实现导体化。优选地，采用氢掺杂工艺对第一透明导电层12进行导体化处理，同时可以对沟道区142露出的有源层131进行氢通道处理。由于在对掺杂半导体层14进行第二次蚀刻并形成沟道时，需要采用氢掺杂工艺对沟道区142露出的有源层131进行氢通道处理，从而保证有源层131具有良好的开关特性，因此，在对第二金属层15进行第二次蚀刻之后，通过采用氢掺杂工艺不仅可以对沟道区142露出的有源层131进行氢通道处理，还可以对第一透明导电层12进行导体化处理，以减少制作工艺的步骤。
如图2n至2o所示，在第一绝缘层101的上方形成第二绝缘层102，采用第三道掩膜工艺对第二绝缘层102进行蚀刻，第二绝缘层102在对应第一电极121和第二导电部153的区域形成接触孔H。其中，第二绝缘层102的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。如图2p-1和图2p-2所示，在第二绝缘层102的上方形成第二透明导电层16，采用第四道掩膜工艺对第二透明导电层16进行蚀刻。第二透明导电层16形成图案化的第二电极161和第三导电部162，第二电极161为公共电极，第三导电部162和第一电极121均与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。第三导电部162通过接触孔H将第一电极121和第二导电部153导电连接，即本实施例中，第一导电部122和第二导电部153均作为漏极，通过将第一导电部122和第二导电部153均作为漏极，并通过第三导电部162将第一电极121和第二导电部153导电连接，从而可以降低漏极的阻抗。其中，第二透明导电层16采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明电极制成。在其他实施例中，阵列基板上也可不用设置公共电极，公共电极设于彩膜基板20上，以形成TN或VA显示模式。当然，也可以不用设置第二透明导电层16，直接以第一导电部122为漏极，第一电极121通过第一导电部122与有源层131导电连接。
图3是本发明实施例一中显示面板的截面结构示意图。如图3所示，本发明还提供一种显示面板，包括如上所述的阵列基板以及与阵列基板相对设置的对置基板20以及设于阵列基板和对置基板20之间的液晶层30。对置基板20上设有上偏光片41，阵列基板上设有下偏光片42，上偏光片41的透光轴与下偏光片42的透光轴相互垂直。其中，液晶层30中的液晶分子采用正性液晶分子(介电各向异性为正的液晶分子)，在初始状态时，正性液晶分子处理于平躺姿态，靠近对置基板20的正性液晶分子的配向方向与靠近阵列基板的正性液晶分子的配向方向相平行。可以理解地是，阵列基板和对置基板20在朝向液晶层30的一层还设有配向层，从而对液晶层30中的正性液晶分子进行配向。
本实施例中，对置基板20为彩膜基板，对置基板20上设有黑矩阵21和色阻层22，黑矩阵21与扫描线111、数据线151、薄膜晶体管以及外围非显示区相对应，黑矩阵21将多个色阻层22间隔开。色阻层22包括红(R)、绿(G)、蓝(B)三色的色阻材料，并对应形成红(R)、绿(G)、蓝(B)三色的子像素。
[实施例二]
图4是本发明实施例二中阵列基板的截面结构示意图。图5是本发明实施例二中阵列基板的平面示意图。如图4和图5所示，本发明实施例二提供的阵列基板与实施例一(图1)中的阵列基板基本相同，不同之处在于，在本实施例中：
阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二透明导电层16包括第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。本实施例中，直接以第一导电部122为漏极，第一电极121通过第一导电部122与有源层131导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
相对于实施例一，本实施例中直接以第一导电部122为漏极，漏极的阻抗相对较大，但第二透明导电层16无需形成第三导电部162，也无需在第二绝缘层102上对应第一电极121和第二导电部153的区域进行开孔，可以简化制作工艺。
图6是本发明实施例二中阵列基板的制作方法的截面示意图之一。图7是本发明实施例二中阵列基板的制作方法的截面示意图之二。如图6至图7所示，本发明实施例二提供的制作方法与实施例一(图2a至图2p)中的制作方法基本相同，不同之处在于，在本实施例中：
第一透明导电层12采用金属氧化物半导体材料。该制作方法还包括：在形成第二金属层15之前，先对第一透明导电层12进行导体化处理；在对第二金属层15进行第二次蚀刻之后，采用氢掺杂工艺对沟道区142露出的有源层131进行氢通道处理。由于本实施例中在形成第二金属层15之前还设有掺杂半导体层14，因此，需要在形成掺杂半导体层14之前，先对第一透明导电层12进行导体化处理。
具体地，如图6所示，且参考图2b，在第一绝缘层101的上方形成第一透明导电层12之后，接着就对第一透明导电层12进行导体化处理，再在第一透明导电层12的表面形成负性光阻层100。或者，可参考图2d-1，对第一透明导电层12进行第一次蚀刻，并剥离负性光阻图案层110之后，接着就对第一透明导电层12进行导体化处理，再在第一绝缘层101的上方依次形成半导体层13和正性光阻层200。再或者，如图7所示，且参考图2g-1，对半导体层13进行蚀刻之后，接着就对第一透明导电层12进行导体化处理。总之，在覆盖第二金属层15和掺杂半导体层14之前，先对第一透明导电层12进行导体化处理，使所有的第一透明导电层12均可导体化处理，即第一导电部122也可以进行导体化处理，以降低第一导电部122的阻抗。当然，在其他实施例中，第一透明导电层12也可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明电极制成，从而无需导体化处理的工艺。
进一步地，可参考图2n-2o，在第一绝缘层101的上方形成第二绝缘层102，第二绝缘层102在对应第一电极121和第二导电部153的区域无需开孔。其中，第二绝缘层102的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
可参考图2p-1和图2p-2，在第二绝缘层102的上方形成第二透明导电层16，对第二透明导电层16进行蚀刻。第二透明导电层16形成图案化的第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。本实施例中，直接以第一导电部122为漏极，第一电极121通过第一导电部122与有源层131导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
相对于实施例一，本实施例中直接以第一导电部122为漏极，漏极的阻抗相对较大，但第二透明导电层16无需形成第三导电部162，也无需在第二绝缘层102上对应第一电极121和第二导电部153的区域进行开孔，可以简化制作工艺。而且，在覆盖第二金属层15和掺杂半导体层14之前，先对第一透明导电层12进行导体化处理，使得所有的第一透明导电层12均可导体化处理，即第一导电部122也可以进行导体化处理，以降低第一导电部122的阻抗。
本发明实施例二提供的显示面板与实施例一(图3)中的显示面板基本相同，不同之处在于，在本实施例中：显示面板包括如上所述的阵列基板以及与阵列基板相对设置的对置基板20以及设于阵列基板和对置基板20之间的液晶层30。
其中，阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二透明导电层16包括第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。本实施例中，直接以第一导电部122为漏极，第一电极121通过第一导电部122与有源层131导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一相同，这里不再赘述。
[实施例三]
图8是本发明实施例三中阵列基板的截面结构示意图。如图8所示，本发明实施例三提供的阵列基板与实施例一(图1)、实施例二(图4)中的阵列基板基本相同，不同之处在于，在本实施例中：
第一导电部122和第二导电部153导电连接，第一导电部122和第二导电部153共同作为漏极，第一电极121通过第一导电部122和第二导电部153与有源层131导电连接。
进一步地，阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二透明导电层16包括第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。由于第一导电部122和第二导电部153直接导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
本实施例中通过将第一导电部122和第二导电部153直接导电连接，从而第二透明导电层16无需形成第三导电部162，也无需在第二绝缘层102上对应第一电极121和第二导电部153的区域进行开孔，可以简化制作工艺，而且对漏极的阻抗基本没有影响。
[根据细则26改正 31.05.2023]
图9a-9b是本发明实施例三中阵列基板的制作方法的截面示意图。如图9a-9b所示，本发明实施例三提供的制作方法与实施例一(图2a至图2p)、实施例二(图5至图7)中的制作方法基本相同，不同之处在于，在本实施例中：
如图9a所示，可参考图2e至图2g-2，在形成半导体层13之后，且形成正性光阻层200之前，在半导体层13的上方形成掺杂半导体层14，即在第一绝缘层101的上方依次形成半导体层13、掺杂半导体层14以及正性光阻层200。以第一金属层11为掩模版，从基底10远离正性光阻层200一侧(基底10的背面)对正性光阻层200进行光刻处理(曝光、显影)，正性光阻层200形成图案化的正性光阻图案层210，正性光阻图案层210与扫描线111和栅极112相对应，即与保留扫描线111和栅极112对应区域的正性光阻层200。以正性光阻图案层210为遮挡，对半导体层13进行蚀刻以及对掺杂半导体层14进行第一次蚀刻，半导体层13形成与扫描线111和栅极112对应的有源层131。通过在形成第二金属层15之前，先以正性光阻图案层210为遮挡，对掺杂半导体层14进行第一次蚀刻，从而在形成第二金属层15时，第二金属层15可以与第一透明导电层12直接接触。
如图9b所示，可参考图2l-1，对第二金属层15进行第二次蚀刻之后，再以第二光阻图案层320为遮挡，对掺杂半导体层14进行第二次蚀刻，掺杂半导体层14形成掺杂半导体图案层141，掺杂半导体图案层141在沟道区142断开，第一导电部122和第二导电部153导电连接。
进一步地，可参考图2n-2o，在第一绝缘层101的上方形成第二绝缘层102，第二绝缘层102在对应第一电极121和第二导电部153的区域无需开孔。其中，第二绝缘层102的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
可参考图2p-1和图2p-2，在第二绝缘层102的上方形成第二透明导电层16，对第二透明导电层16进行蚀刻。第二透明导电层16形成图案化的第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。本实施例中，以第一导电部122和第二导电部153为漏极，且第一导电部122和第二导电部153直接导电连接，第一电极121通过第一导电部122和第二导电部153与有源层131导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
本实施例中通过在对半导体层13进行蚀刻时，采用正性光阻图案层210为遮挡先对掺杂半导体层14进行第一次蚀刻，使得第一导电部122和第二导电部153可以直接导电连接，从而第二透明导电层16无需形成第三导电部162，也无需在第二绝缘层102上对应第一电极121和第二导电部153的区域进行开孔，可以简化制作工艺，而且对漏极的阻抗基本没有影响。
本发明实施例三提供的显示面板与实施例一(图3)、实施例二中的显示面板基本相同，不同之处在于，在本实施例中：显示面板包括如上所述的阵列基板以及与阵列基板相对设置的对置基板20以及设于阵列基板和对置基板20之间的液晶层30。
其中，阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二透明导电层16包括第二电极161，第二电极161为公共电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的下方。第二电极161在对应第一电极121的区域为梳状结构，从而便于与第一电极121之间形成水平电场，以形成边缘场开关模式(Fringe Field Switching，FFS)。由于第一导电部122和第二导电部153直接导电连接，第一导电部122和第二导电部153共同作为漏极，第一电极121通过第一导电部122和第二导电部153与有源层131导电连接，因此，第二透明导电层16无需形成第三导电部162，第二绝缘层102在对应第一电极121和第二导电部153的区域也无需开孔，可以简化制作工艺。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一、实施例二相同，这里不再赘述。
[实施例四]
图10是本发明实施例四中阵列基板的截面结构示意图。图11是本发明实施例四中阵列基板的平面示意图。如图10和11所示，本发明实施例四提供的阵列基板与实施例一(图1)、实施例二(图4)、实施例三(图8)中的阵列基板基本相同，不同之处在于，在本实施例中：
第一电极121为公共电极，第一电极121和第一导电部122相互绝缘。该阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二绝缘层102在对应第二导电部153的区域设有接触孔H。第二透明导电层16包括第二电极161和第三导电部162，第二电极161为像素电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的上方。第三导电部162与第二电极161导电连接，第三导电部162通过接触孔H与第二导电部153导电连接，即本实施例中，第二导电部153作为漏极。
本实施例中，第一电极121为公共电极，第二电极161为像素电极，从而使得像素电极位于公共电极的上方，以形成另一种边缘场开关模式(Fringe Field Switching，FFS)。
图12a至12c是本发明实施例四中阵列基板的制作方法的示意图。如图12a至12c所示，本发明实施例四提供的制作方法与实施例一(图2a至图2p)、实施例二(图5至图7)、实施例三(图9a至图9b)中的制作方法基本相同，不同之处在于，在本实施例中：
该制作方法还包括：
如图12a所示，可参考图2h-2i，在第一透明导电层12和半导体层13的上方依次形成掺杂半导体层14、第二金属层15以及光阻层300。第二道掩膜工艺采用半色调掩膜版400(Half Tone Mask)为遮挡，从半色调掩膜版400远离基底10一侧(基底10的正面)对光阻层300进行光刻处理，光阻层300形成图案化的第一光阻图案层310，第一光阻图案层310包括完全被光刻掉的无光阻图案区311、部分被光刻掉的半光阻图案层312以及未被光刻掉的全光阻图案层313。
其中，本实施例中半色调掩膜版400的图案与实施例一中半色调掩膜版400的图案有所不同。具体地，在本实施例中，第一电极121对应区域的半透光区420与第一导电部122对应区域的非透光区430之间设有透光区410，从而在第一光阻图案层310上，第一电极121对应区域半光阻图案层312与第一导电部122对应区域的全光阻图案层313之间设有无光阻图案区311，在以第一光阻图案层310为遮挡，对第二金属层15进行第一次蚀刻时，使得第一电极121和第一导电部122之间可以断开。
如图12b-1和14a所示，可参考图2j-1和图2j-2，以第一光阻图案层310为遮挡，依次对第二金属层15进行第一次蚀刻、对掺杂半导体层14进行第一次蚀刻以及对第一透明导电层12进行第二次蚀刻。第一透明导电层12形成图案化的第一电极121和第一导电部122，第一导电部122与有源层131导电连接。本实施例中，第一电极121为公共电极，第一电极121和第一导电部122相互绝缘。
如图12c-1和14b所示，可参考图2k-2l和图2l-2，采用光阻灰化工艺除去半光阻图案层312，并保留部分全光阻图案层313，第一光阻图案层310形成第二光阻图案层320。以第二光阻图案层320为遮挡，依次对第二金属层15进行第二次蚀刻以及对掺杂半导体层14进行第二次蚀刻。第二金属层15形成数据线151、源极152以及第二导电部153，露出第一电极121和沟道区142的有源层131，数据线151与源极152导电连接。
可参考图2n-2o，在第一绝缘层101的上方形成第二绝缘层102，对第二绝缘层102进行蚀刻并在对应第二导电部153的区域形成有接触孔H。其中，第二绝缘层102的材料为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合。
可参考图2p-1和图2p-2，在第二绝缘层102上方形成第二透明导电层16，对第二透明导电层16进行蚀刻，第二透明导电层16形成图案化的第二电极161和第三导电部162。第二电极161为像素电极，第一电极121(公共电极)与第二电极161(像素电极)相互绝缘设置，且像素电极位于公共电极的上方。第三导电部162与第二电极161导电连接，第三导电部162通过接触孔H与第二导电部153导电连接，即本实施例中，第二导电部153作为漏极。
本实施例中，第一电极121为公共电极，第二电极161为像素电极，从而使得像素电极位于公共电极的上方，以形成另一种边缘场开关模式(Fringe Field Switching，FFS)。
图13是本发明实施例四中显示面板的截面结构示意图。如图13所示，本发明实施例四提供的显示面板与实施例一(图3)、实施例二、实施例三中的显示面板基本相同，不同之处在于，在本实施例中：显示面板包括如上所述的阵列基板以及与阵列基板相对设置的对置基板20以及设于阵列基板和对置基板20之间的液晶层30。其中，阵列基板上的第一电极121为公共电极，第一电极121和第一导电部122相互绝缘，第二电极161为像素电极，从而使得像素电极位于公共电极的上方，以形成另一种边缘场开关模式(Fringe Field Switching，FFS)。阵列基板还包括设于第一绝缘层101上方的第二绝缘层102以及设于第二绝缘层102上方的第二透明导电层16。第二绝缘层102在对应第二导电部153的区域设有接触孔H。第二透明导电层16包括第二电极161和第三导电部162，第二电极161为像素电极，第一电极121与第二电极161相互绝缘设置，即像素电极和公共电极相互绝缘设置，且像素电极位于公共电极的上方。第三导电部162与第二电极161导电连接，第三导电部162通过接触孔H与第二导电部153导电连接，即本实施例中，第二导电部153作为漏极。
本领域的技术人员应当理解的是，本实施例的其余结构以及工作原理均与实施例一、实施例二、实施例三相同，这里不再赘述。
在本文中，所涉及的上、下、左、右、前、后等方位词是以附图中的结构位于图中的位置以及结构相互之间的位置来定义的，只是为了表达技术方案的清楚及方便。应当理解，所述方位词的使用不应限制本申请请求保护的范围。还应当理解，本文中使用的术语“第一”和“第二”等，仅用于名称上的区分，并不用于限制数量和顺序。
以上所述，仅是本发明的较佳实施例而已，并非对本发明做任何形式上的限定，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰，为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的保护范围之内。
 工业实用性
通过以第一金属层为掩模版，利用背面曝光方式，搭配负型光阻和正型光阻的交替使用，从而分别对第一透明导电层进行第一次蚀刻以及对半导体层进行蚀刻，再利用半色调掩膜版，从而对第一透明导电层进行第二次蚀刻以及对第二金属层进行两次蚀刻，从而可以减少掩膜版的数量，简化制作工艺，降低制作成本；而且对第二金属层进行两次蚀刻后，数据线、源极以及第二导电部的下方依然会保留第一透明导电层，从而可以降低数据线、源极以及第二导电部的阻抗。

Claims (15)

  1. 一种阵列基板的制作方法，其特征在于，包括：
    提供基底(10)；
    在所述基底(10)的上方形成第一金属层(11)，对所述第一金属层(11)进行蚀刻，所述第一金属层(11)形成图案化的扫描线(111)和栅极(112)，所述栅极(112)与所述扫描线(111)导电连接；
    在所述基底(10)的上方形成覆盖所述扫描线(111)和所述栅极(112)的第一绝缘层(101)；
    在所述第一绝缘层(101)的上方依次形成第一透明导电层(12)和负性光阻层(100)，以所述第一金属层(11)为掩模版，从所述基底(10)远离所述负性光阻层(100)一侧对所述负性光阻层(100)进行光刻处理，除去与所述扫描线(111)和所述栅极(112)对应区域的所述负性光阻层(100)，所述负性光阻层(100)形成图案化的负性光阻图案层(110)，以所述负性光阻图案层(110)为遮挡，对所述第一透明导电层(12)进行第一次蚀刻，除去与所述扫描线(111)和所述栅极(112)对应区域的所述第一透明导电层(12)；
    在所述第一绝缘层(101)的上方依次形成半导体层(13)和正性光阻层(200)，以所述第一金属层(11)为掩模版，从所述基底(10)远离所述正性光阻层(200)一侧对所述正性光阻层(200)进行光刻处理，所述正性光阻层(200)形成图案化的正性光阻图案层(210)，所述正性光阻图案层(210)与所述扫描线(111)和所述栅极(112)相对应，以所述正性光阻图案层(210)为遮挡，对所述半导体层(13)进行蚀刻，所述半导体层(13)形成与所述扫描线(111)和所述栅极(112)对应的有源层(131)；
    在所述第一透明导电层(12)和所述半导体层(13)的上方依次形成第二金属层(15)和光阻层(300)，采用半色调掩膜版(400)为遮挡，从所述半色调掩膜版(400)远离所述基底(10)一侧对所述光阻层(300)进行光刻处理，所述光阻层(300)形成图案化的第一光阻图案层(310)，所述第一光阻图案层(310)包括完全被光刻掉的无光阻图案区(311)、部分被光刻掉的半光阻图案层(312)以及未被光刻掉的全光阻图案层(313)；
    以所述第一光阻图案层(310)为遮挡，对所述第二金属层(15)进行第一次蚀刻以及对所述第一透明导电层(12)进行第二次蚀刻，所述第一透明导电层(12)形成图案化的第一电极(121)和第一导电部(122)，所述第一导电部(122)与所述有源层(131)导电连接；
    采用光阻灰化工艺除去所述半光阻图案层(312)，所述第一光阻图案层(310)形成所述第二光阻图案层(320)，以所述第二光阻图案层(320)为遮挡，对所述第二金属层(15)进行第二次蚀刻，所述第二金属层(15)形成数据线(151)、源极(152)以及第二导电部(153)，且露出所述第一电极(121)和所述沟道区(142)的所述有源层(131)，所述数据线(151)与所述源极(152)导电连接，所述第一导电部(122)和所述第二导电部(153)至少其中之一为漏极，所述第一电极(121)和所述有源层(131)的沟道区(142)均与所述半光阻图案区(312)相对应，所述数据线(151)、所述源极(152)以及所述第二导电部(153)均与所述全光阻图案层(313)相对应。
  2. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述制作方法还包括：
    在对所述半导体层(13)进行蚀刻之后，先在所述第一透明导电层(12)和所述半导体层(13)的上方形成掺杂半导体层(14)，再在所述掺杂半导体层(14)的上方依次形成所述第二金属层(15)和所述光阻层(300)；
    对所述第二金属层(15)进行第一次蚀刻之后，以所述第一光阻图案层(310)为遮挡，对所述掺杂半导体层(14)进行第一次蚀刻；
    对所述第二金属层(15)进行第二次蚀刻之后，以所述第二光阻图案层(320)为遮挡，对所述掺杂半导体层(14)进行第二次蚀刻，所述掺杂半导体层(14)形成图案化的掺杂半导体图案层(141)，所述掺杂半导体图案层(141)在所述沟道区(142)断开。
  3. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述制作方法还包括：
    在形成所述半导体层(13)之后，先在所述半导体层(13)的上方形成掺杂半导体层(14)，再在所述掺杂半导体层(14)的上方形成所述正性光阻层(200)；
    对所述半导体层(13)进行蚀刻之前，先以所述正性光阻图案层(210)为遮挡，对所述掺杂半导体层(14)进行第一次蚀刻；
    对所述第二金属层(15)进行第二次蚀刻之后，再以所述第二光阻图案层(320)为遮挡，对所述掺杂半导体层(14)进行第二次蚀刻，所述掺杂半导体层(14)形成掺杂半导体图案层(141)，所述掺杂半导体图案层(141)在所述沟道区(142)断开，所述第一导电部(122)和所述第二导电部(153)导电连接。
  4. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述第一电极(121)为像素电极，所述第一电极(121)和所述第一导电部(122)导电连接。
  5. 根据权利要求4所述的阵列基板的制作方法，其特征在于，所述制作方法还包括：
    在所述第一绝缘层(101)的上方形成第二绝缘层(102)，对所述第二绝缘层(102)进行蚀刻，所述第二绝缘层(102)在对应所述第一电极(121)和所述第二导电部(153)的区域形成接触孔(H)；
    在所述第二绝缘层(102)的上方形成第二透明导电层(16)，对所述第二透明导电层(16)进行蚀刻，所述第二透明导电层(16)形成图案化的第二电极(161)和第三导电部(162)，所述第二电极(161)为公共电极，所述第三导电部(162)和所述第一电极(121)均与所述第二电极(161)相互绝缘，所述第三导电部(162)通过所述接触孔(H)将所述第一电极(121)和所述第二导电部(153)导电连接。
  6. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述第一电极(121)为公共电极，所述第一电极(121)和所述第一导电部(122)相互绝缘，所述制作方法还包括：
    在所述第一绝缘层(101)的上方形成第二绝缘层(102)，对所述第二绝缘层(102)进行蚀刻并在对应所述第二导电部(153)的区域形成接触孔(H)；
    在所述第二绝缘层(102)的上方形成第二透明导电层(16)，对所述第二透明导电层(16)进行蚀刻，所述第二透明导电层(16)形成图案化的第二电极(161)和第三导电部(162)，所述第二电极(161)为像素电极，所述第三导电部(162)与所述第二电极(161)导电连接，所述第二电极(161)与所述第一电极(121)相互绝缘，所述第三导电部(162)通过所述接触孔(H)与所述第二导电部(153)导电连接。
  7. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述第一透明导电层(12)采用金属氧化物半导体材料，所述制作方法还包括：
    在形成所述第二金属层(15)之前，先对所述第一透明导电层(12)进行导体化处理；
    在对所述第二金属层(15)进行第二次蚀刻之后，采用氢掺杂工艺对所述沟道区(142)露出的所述有源层(131)进行氢通道处理。
  8. 根据权利要求1所述的阵列基板的制作方法，其特征在于，所述第一透明导电层(12)采用金属氧化物半导体材料，所述制作方法还包括：
    在对所述第二金属层(15)进行第二次蚀刻之后，再对所述第一透明导电层(12)进行导体化处理。
  9. 根据权利要求8所述的阵列基板的制作方法，其特征在于，所述制作方法还包括：
    采用氢掺杂工艺对所述第一透明导电层(12)进行导体化处理，以及对所述沟道区(142)露出的所述有源层(131)进行氢通道处理。
  10. 一种阵列基板，其特征在于，采用如权利要求1-9任一项所述的制作方法制作而成，所述阵列基板包括：
    基底(10)；
    设于所述基底(10)上方的第一金属层(11)，所述第一金属层(11)包括扫描线(111)和栅极(112)，所述栅极(112)与所述扫描线(111)导电连接；
    设于所述第一金属层(11)上方的第一绝缘层(101)，所述第一绝缘层(101)覆盖所述扫描线(111)和所述栅极(112)；
    设于所述第一绝缘层(101)上方的第一透明导电层(12)和半导体层(13)，所述第一透明导电层(12)包括第一电极(121)和第一导电部(122)，所述半导体层(13)包括有源层(131)，所述第一导电部(122)与所述有源层(131)导电连接；
    设于所述第一透明导电层(12)和所述半导体层(13)上方的第二金属层(15)，所述第二金属层(15)包括数据线(151)、源极(152)以及第二导电部(153)，所述数据线(151)与所述源极(152)导电连接，所述第一导电部(122)和所述第二导电部(153)至少其中之一为漏极。
  11. 根据权利要求10所述的阵列基板，其特征在于，所述阵列基板还包括设于所述半导体层(13)和所述第二金属层(15)之间的掺杂半导体层(14)，所述掺杂半导体层(14)包括图案化的掺杂半导体图案层(141)，所述掺杂半导体图案层(141)在所述有源层(131)的沟道区(142)断开。
  12. 根据权利要求10所述的阵列基板，其特征在于，所述第一电极(121)为像素电极，所述第一电极(121)和所述第一导电部(122)导电连接。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述阵列基板还包括：
    设于所述第一绝缘层(101)上方的第二绝缘层(102)，所述第二绝缘层(102)在对应所述第一电极(121)和所述第二导电部(153)的区域设有接触孔(H)；
    设于所述第二绝缘层(102)上方的第二透明导电层(16)，所述第二透明导电层(16)包括第二电极(161)和第三导电部(162)，所述第二电极(161)为公共电极，所述第三导电部(162)和所述第一电极(121)均与所述第二电极(161)相互绝缘，所述第三导电部(162)通过所述接触孔(H)将所述第一电极(121)和所述第二导电部(153)导电连接。
  14. 根据权利要求12所述的阵列基板，其特征在于，所述第二导电部(153)与所述第一导电部(122)导电连接。
  15. 根据权利要求10所述的阵列基板，其特征在于，所述第一电极(121)为公共电极，所述第一电极(121)和所述第一导电部(122)相互绝缘，所述阵列基板还包括：
    设于所述第一绝缘层(101)上方的第二绝缘层(102)，所述第二绝缘层(102)在对应所述第二导电部(153)的区域设有接触孔(H)；
    设于所述第二绝缘层(102)上方的第二透明导电层(16)，所述第二透明导电层(16)包括第二电极(161)和第三导电部(162)，所述第二电极(161)为像素电极，所述第三导电部(162)与所述第二电极(161)导电连接，所述第一电极(121)与所述第二电极(161)相互绝缘，所述第三导电部(162)通过所述接触孔(H)与所述第二导电部(153)导电连接。
PCT/CN2023/093722 2023-05-11 2023-05-11 阵列基板的制作方法及阵列基板 WO2024229870A1 (zh)

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