WO2023207965A1 - Chip verification method and platform - Google Patents

Abstract

The present disclosure relates to the technical field of chip verification, and particularly provides a chip verification method and platform. The chip verification platform comprises: an excitation data component, configured to generate excitation data on the basis of a case under test and send the excitation data to a component to be verified; and a counting control component, configured to detect and count, in real time, in a verification process, a target signal of each piece of result data output by the component to be verified, and determine, in response to the fact that the number of the target signals meets a preset condition, that verification of the case under test is finished, the target signal representing a timing dependent signal of the result data. According to embodiments of the present disclosure, the chip verification efficiency is improved.

Description

Chip verification method and platform

Cross-references to related applications

This application claims priority from the Chinese patent application with application number 2022104732395, submitted on April 29, 2022, which is incorporated herein by reference.

Technical field

The present disclosure relates to the field of chip verification technology, and specifically relates to a chip verification method and platform.

Background technique

Chip verification is a key step in the design process of digital IC (integrated circuit, integrated circuit), which can usually be achieved using various verification platforms, such as UVM (Universal Verification Methodology, universal verification method) verification platform. In related technologies, when using a verification platform for chip verification, the verification time is longer, resulting in a longer chip development cycle.

Contents of the invention

In order to improve chip verification efficiency, embodiments of the present disclosure provide a chip verification method and platform, electronic equipment, and storage media.

In a first aspect, embodiments of the present disclosure provide a chip verification platform, including: an incentive data component configured to generate incentive data based on a use case to be tested and send the incentive data to the component to be verified; a counting control component configured to Configured to detect and count the target signals of the result data output by the component to be verified in real time during the verification process, and in response to the number of the target signals meeting the preset conditions, determine that the verification of the use case to be tested is completed; the target Signal represents a time-series dependent signal of the resulting data.

In some embodiments, the counting control component is configured to: determine an expected number of the result data based on the use case to be tested in advance; and in response to the number of the target signals reaching the expected number, determine the target signal The quantity meets the preset conditions.

In some embodiments, the chip verification platform further includes: a reference model component configured to receive the stimulus data and output corresponding expected result data; a comparison component configured in the verification environment for performing During the verification process, the result data output by the component to be verified is compared with the expected result data in real time to obtain a comparison result corresponding to the result data; in response to an error in the comparison result of the result data, stop The verification process.

In some embodiments, the result data includes a data signal and a timing signal, and the expected result data includes an expected data signal and an expected timing signal; the comparison component is configured to: compare the data signal of the result data with the Compare the expected data signal of the expected result data to obtain the first result; compare the timing signal of the result data with the expected timing signal of the expected result data to obtain the second result; according to the first result The comparison result corresponding to the result data is determined with the second result.

In some implementations, the stimulus data component includes: a data generation component, configured outside the verification environment, for generating the stimulus data based on the use case to be tested; a stimulus component, configured in the verification environment, for receiving the stimulus data and sending the stimulus data to the component to be verified; wherein the data generation component is configured to send the stimulus data to the reference model component, and the Reference model components are deployed outside the verification environment.

In some embodiments, the comparison component is configured as an output proxy component.

In some embodiments, the chip verification platform further includes: a configuration agent component, configured in the verification environment, for generating and sending configuration information to the component to be verified according to the incentive data; a coverage detection component, Configured in the verification environment, used to detect the configuration information, and determine the functional coverage information of the use case to be tested based on the configuration information.

In a second aspect, embodiments of the present disclosure provide a chip verification method, including: generating incentive data based on use cases to be tested, and sending the incentive data to components to be verified; and detecting the components to be verified in real time during the verification process. The target signals of the output result data are counted; the target signal represents the timing related signal of the result data; in response to the number of the target signals meeting the preset condition, it is determined that the verification of the use case to be tested is completed.

In some embodiments, determining that the verification of the use case to be tested is completed in response to the number of target signals meeting a preset condition includes: determining the expected amount of result data based on the use case to be tested in advance; responding to The number of the target signals reaches the expected number, and it is determined that the number of the target signals meets the preset condition.

In some embodiments, the method of the present disclosure further includes: sending the stimulus data to a reference model component to obtain the expected result data output by the reference model component; during the verification process, transmitting the stimulus data to the reference model component in real time. The result data output by the component to be verified is compared with the expected result data to obtain a comparison result corresponding to the result data; in response to an error in the comparison result of the result data, the verification process is stopped.

In some embodiments, the result data includes data signals and timing signals, and the expected result data includes expected data signals and expected timing signals; during the verification process, all the output signals of the component to be verified are output in real time. Comparing the result data with the expected result data to obtain a comparison result corresponding to the result data includes: comparing a data signal of the result data with an expected data signal of the expected result data to obtain a first result; Compare the timing signal of the result data with the expected timing signal of the expected result data to obtain a second result; determine the comparison result corresponding to the result data based on the first result and the second result.

In some embodiments, generating stimulus data based on the use case to be tested and sending the stimulus data to the component to be verified includes: a data generating component outside the verification environment will generate the stimulus data based on the use case to be tested. The data is sent to the stimulus component in the verification environment, and in the verification environment, the stimulus component sends the stimulus data sent to the component to be verified; sending the stimulus data to the reference model component to obtain the expected result data output by the reference model component includes: the data generation component sending the stimulus data to the verification environment The reference model component outside the verification environment sends the expected result data to the verification environment.

In some embodiments, during the verification process, the result data output by the component to be verified is compared with the expected result data in real time to obtain a comparison result corresponding to the result data, including: In the verification environment, the output agent component receives the result data and the expected result data respectively, and compares the result data with the expected result data in real time to obtain the comparison result.

In some implementations, the method of the present disclosure further includes: in the verification environment, detecting the configuration information of the stimulus data sent to the component to be verified, and determining the use case to be tested based on the configuration information Functional coverage information.

In some embodiments, the target signal includes one or more of a valid signal, a ready signal, a line start signal, and a line end signal.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: a processor; and a memory storing computer instructions, the computer instructions being used to cause the processor to execute the method according to any embodiment of the second aspect. .

In a fourth aspect, an embodiment of the present disclosure provides a storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the method according to any embodiment of the second aspect.

The chip verification platform of the disclosed embodiment includes an incentive data component and a counting control component. The incentive data component is used to generate incentive data based on the use case to be tested and send the incentive data to the component to be verified. The counting control component is used to perform the verification during the verification process. , detect and count the target signals of each result data output by the component to be verified in real time, and in response to the number of target signals meeting the preset conditions, it is determined that the verification of the use case to be tested is completed. In the disclosed embodiment, the processing progress of the stimulus data can be accurately detected, and the end time of the verification process can be accurately determined, which not only avoids verification failure caused by early ending, but also avoids the reduction of verification efficiency caused by long delays, and improves chip verification efficiency.

Description of the drawings

In order to more clearly explain the specific embodiments of the present disclosure or the technical solutions in the prior art, the drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of the UVM verification platform in related technologies.

Figure 2 is a schematic structural diagram of a chip verification platform according to some embodiments of the present disclosure.

Figure 3 is a flow chart of a chip verification method according to some embodiments of the present disclosure.

Figure 4 is a flow chart of a chip verification method according to some embodiments of the present disclosure.

Figure 5 is a flow chart of a chip verification method according to some embodiments of the present disclosure.

Figure 6 is a flow chart of a chip verification method according to some embodiments of the present disclosure.

Figure 7 is a schematic structural diagram of a chip verification platform according to some embodiments of the present disclosure.

Figure 8 is a structural block diagram of an electronic device according to some embodiments of the present disclosure.

Detailed ways

The technical solution of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this disclosure. In addition, the technical features involved in different embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other.

Figure 1 shows the structural schematic diagram of the traditional UVM (Universal Verification Methodology) verification platform. The following is a brief description of the chip verification process in conjunction with Figure 1.

As shown in Figure 1, in the UVM verification environment, the platform architecture mainly includes: incentive generation component (Sequence), input agent component (Input agent), output agent component (Output agent), and component to be verified (DUT, device under test) , reference model component (reference model) and scoreboard (Scoreboard).

The stimulus generation component is used to generate stimulus data for the use case to be tested (Case). For example, taking ISP (Image Signal Processing, Image Signal Processing) chip verification as an example, the stimulus data generated by the stimulus generation component can be randomly generated image data.

The input agent component is used to send stimulus data to the component to be verified in a certain time sequence based on the relevant configuration information required by the component to be verified. For example, the stimulus data takes a single frame of image data as an example. The input agent component can send the pixel data included in the image to the component to be verified frame by frame according to a predetermined timing sequence.

The component to be verified represents an RTL (register-transfer level) design component that is completely consistent with the chip functional module. It can process the received stimulus data according to the preset function and output the processed execution result data to Output proxy component.

The output agent component is used to detect the output data of the component to be verified and send the output execution result data to the scoreboard.

The reference model component represents a reference model corresponding to the expected functionality of the component to be verified. The input agent component sends stimulus data to the reference model component, and the reference model sends the resulting expected outcome data to the scoreboard.

The scoreboard receives expected result data sent by the reference model component and actual execution data forwarded by the output agent component. By running the result data and comparing whether the two are consistent, you can determine whether the function of the component to be verified is realized, that is, the verification result of the component to be verified is obtained.

In the above-mentioned traditional UVM verification process, for the verification process of a use case to be tested, the start and end of the verification are generally controlled through the object mechanism. That is, the verification starts when the stimulus generation component sends the stimulus data, and ends when the stimulus data is sent or delayed for a period. However, this method is difficult to apply to complex chip verifications with a large amount of calculations, such as ISP.

Taking ISP chip verification as an example, the amount of stimulus data is huge. For example, for 720p image data, the output will generate 1280*720 pixel data. From the time the stimulus data is sent to the output data of the component to be verified, The time is difficult to know accurately. If each use case to be tested is for a certain fixed resolution image data, it may be possible to obtain a roughly accurate delay period through multiple experiments. However, the resolution of the image data generated by different use cases to be tested will vary. They are all different and it is difficult to obtain the delay period by means of experiments.

Therefore, if the delay period is set to be short, the verification will end early and the verification will fail; conversely, if the delay period is set to be long, the verification time will be lengthened and verification efficiency will be reduced. It can be seen from this that the UVM verification platform in related technologies is not complete and the chip verification is not robust.

In view of the shortcomings of the above related technologies, the embodiments of the present disclosure provide a chip verification platform and method, electronic equipment, and storage media, aiming to reasonably determine the verification end time of chip verification and improve the accuracy and robustness of the verification platform.

FIG. 2 shows an image of the structural principle of the chip verification platform in some embodiments of the present disclosure. The chip verification platform in some embodiments of the present disclosure will be described below with reference to FIG. 2 .

As shown in FIG. 2 , in some embodiments, the chip verification platform of the present disclosure includes a stimulus data component 100 , an input agent component 200 , a component to be verified 300 , a reference model component 400 , a comparison component 500 and a counting control component 800 .

The stimulus data component 100 is used to generate stimulus data according to the use case to be tested, and send the stimulus data to the input agent component 200. The input agent component 200 sends the stimulus data to the component to be verified 300 and the reference model component in time sequence based on the set configuration information. 400. The component to be verified 300 sends the processed result data to the comparison component 500 , and the reference model component 400 sends the processed expected result data to the comparison component 500 . The comparison component 500 compares the result data and the expected result data to obtain the comparison result of the use case to be tested.

It can be understood that during the chip verification process, the input agent component 200 inputs stimulus data to the component to be verified 300 one by one in time sequence. Similarly, the result data output by the component to be verified 300 is also output one by one in time sequence.

Taking ISP chip verification as an example, in one example, the stimulus data component 100 generates The complete stimulus data represents a frame of image data of 1280 pixels*720 pixels, so the input agent component 200 inputs each pixel data to the component to be verified 300 pixel by pixel. After the component 300 to be verified processes each pixel data, it also outputs the result data corresponding to each pixel data pixel by pixel.

Therefore, in the embodiment of the present disclosure, the counting control component 800 is set up in the verification environment. The counting control component 800 is used to detect and count the target signal in the result data output by the component 300 to be verified in real time. That is, every time the counting control component 800 detects Once the target signal is reached, 1 can be added to the previous count result.

It can be understood that the function of the target signal is to perform statistics on each result data. Therefore, in an actual implementation scenario, the target signal may be a signal related to timing statistics included in the result data, that is, the timing described in this disclosure. Relevant signals.

For example, the Valid/Ready (valid signal/ready signal) handshake mechanism is a common data communication protocol for chip verification. Its basic principle is that when the upper-level module (sender) sets the Valid signal high, it indicates that data has been successfully sent to the lower-level module (receiver). ), the lower-level module sets the Ready signal high to indicate that it is ready to receive data. Therefore, when the result data output by the component 300 to be verified includes a Valid signal or a Ready signal, it means that the pixel data corresponding to the result data has been processed.

In some embodiments of the present disclosure, the counting control component 800 can detect the Valid signal or the Ready signal in each result data output by the to-be-verified component 300, that is, the Valid signal or the Ready signal can be used as the target signal. When the counting control component 800 detects a target signal, it means that one pixel data has been processed and the corresponding result data is output. Therefore, the counting control component 800 can add 1 on the basis of the previous statistical result, and so on, until the target When the statistical number of signals reaches the preset conditions, it can be determined that the verification is over.

Still taking ISP chip verification as an example, the stimulus data generated by a use case to be tested represents a frame of image data of 1280*720 pixels, that is, the component 300 to be verified needs to process a total of 1280*720 pixel data, and the corresponding output is 1280*720 result data. During the verification process, the counting control component 800 can detect the target signal of each result data in real time. When the target signal is detected once, the counting result can be increased by 1 until the counting result reaches 1280*720, and the target signal to be measured can be determined. The verification process of the use case ends.

When the counting control component 800 determines that the verification process is over, the counting control component 800 can send an end signal to the incentive data component 100, thereby controlling the incentive data component 100 to end data generation and sending (drop objection), and the entire verification process stops.

Of course, it can be understood that the target signal is not limited to the Valid signal (valid signal) or Ready signal (preparation signal) in the above example, and can also be any other timing-related signal suitable for marking the number of result data, such as a row start signal, Line end signal, frame start signal, frame end signal, etc., this disclosure does not limit this. However, it can also be understood that the Valid signal and the Ready signal are more versatile and can be applied to various types of Chip verification.

On the basis of the verification platform shown in Figure 2, some embodiments of the present disclosure provide a chip verification method, which will be described below in conjunction with Figure 3.

As shown in Figure 3, in some implementations, the chip verification method of the disclosed example includes:

S310. Generate incentive data based on the use case to be tested, and send the incentive data to the component to be verified.

In the embodiment of the present disclosure, the use case to be tested can be understood as a task (case) for functional verification of the component to be verified 300. For different use cases to be tested, the incentive data component 100 can generate different incentive data.

For example, in one example, a use case to be tested indicates that the component 300 to be verified is used to denoise an image. The excitation data component 100 can randomly generate the image data of the image to be denoised, that is, the excitation data, according to the relevant configuration information of the use case to be tested. , and sends the excitation data to the input agent component 200, and then the input agent component 200 sends each pixel data pixel by pixel to the component to be verified 300 according to the corresponding time sequence.

S320. During the verification process, detect and count the target signal of each result data output by the component to be verified in real time.

Still taking the above example as an example, the component to be verified 300 processes each received pixel data in turn, obtains the result data corresponding to the pixel data, and outputs it. As shown in Figure 2, the counting control component 800 detects the target signal in the result data output by the verification component 300. When the target signal is detected once, the counting result can be increased by 1, so that the data processing progress of the verification component 300 can be processed in real time. statistics.

S330. In response to the number of target signals meeting the preset conditions, it is determined that the verification of the use case to be tested is completed.

In the embodiment of the present disclosure, during the verification process, the counting control component 800 continues to detect the number of target signals output by the component 300 to be verified until the number of target signals meets the preset conditions, that is, it proves that the stimulus data generated for the use case to be tested has been All processing is completed and the verification process can be ended.

Specifically, as shown in Figure 4, in some embodiments, the process of determining that the number of target signals meets preset conditions includes:

S331. Determine the expected quantity of result data in advance based on the use case to be tested.

S332. In response to the number of target signals reaching the expected number, determine that the number of target signals meets the preset condition.

For example, in one example, the stimulus data generated based on the use case to be tested represents a frame of image data of 1280 pixels*720 pixels, so it can be determined that the expected number of result data corresponding to the stimulus data is 1280*720.

Combined with the foregoing process, while the component to be verified 300 continues to process the stimulus data, the counting control component 800 continues to detect and count the number of target signals in the output result data. When the number of target signals reaches 1280*720, it means that the stimulus All pixel data in the data has been processed, so the validation process for the use case under test is complete.

When the count control component 800 determines that the verification process is complete, the count control component 800 may send a request to the stimulus data component. 100 sends an end signal, thereby controlling the incentive data component 100 to end data generation and sending (drop objection), and the entire verification process stops.

As can be seen from the above, in the embodiments of the present disclosure, during the chip verification process, by detecting the number of target signals in the result data output by the component to be verified DUT, the processing progress of the stimulus data can be accurately detected, and the end of the verification process can be accurately determined. time, not only to avoid early termination leading to verification failure, but also to avoid long delays leading to reduced verification efficiency. Moreover, the disclosed method can be applied to any chip verification scenario and is not limited by chip type, thereby improving the robustness of the verification platform.

As shown in Figure 1, in the traditional chip verification method, the scoreboard often starts to compare the expected result data output by the reference model component and the execution result data sent by the output agent component after the use case to be tested is completely processed. . For example, in one example, the stimulus data represents image data of 1280*720 pixels. In the traditional verification process, the component to be verified needs to process all 1280*720 pixel data to obtain the execution result data, and then the scoreboard uses the execution results Compare the data with the expected result data output by the reference model component to confirm whether they are consistent. However, for ISP chips, the process of processing one frame of image data is very long, which can reach several hours or even dozens of hours, resulting in a long waiting time for data comparison.

In addition, during this process, when an error occurs in a certain pixel data, you need to trace back the waveform chart on Verdi (automated debugging system) to find out the erroneous code. However, for the huge amount of data generated by the ISP chip, for example, this process is very time-consuming and labor-intensive, and you need to wait for the data processing to be completed before you can start looking for bugs (errors). The ISP chip also takes a very long time to process one frame of image, resulting in low verification efficiency. .

Based on this, as shown in Figure 5, in some implementations, the chip verification method of the disclosed example also includes:

S510. Send the stimulus data to the reference model component to obtain the expected result data output by the reference model component.

Combined with the verification platform shown in Figure 2, the incentive data generated by the incentive data component 100 is configured by the input agent component 200 and sent to the reference model component 400. The reference model component 400 processes the incentive data and outputs expected result data.

S520. During the verification process, compare each result data output by the component to be verified with the corresponding expected result data in real time to obtain a comparison result corresponding to the result data.

In the embodiment of the present disclosure, the comparison component 500 receives the expected result data output by the reference model component 400 and the result data output by the component to be verified 300 . However, in the embodiment of the present disclosure, the comparison is not performed until the component 300 to be verified outputs all the result data. Instead, each received result data is compared with the corresponding expected result data in real time.

For example, in an example, the excitation data represents a frame of image data of 1280 pixels*720 pixels. By processing the image data with reference to the model component 400, the expected results corresponding to all pixel data can be obtained, that is, the number of expected results. according to. The component to be verified 300 processes the pixel data pixel by pixel, thereby outputting the result data corresponding to each pixel data pixel by pixel. When the comparison component 500 receives a piece of result data, it immediately compares the result data with the expected result data corresponding to the pixel data, and obtains a comparison result between the two without waiting for all pixel data to be processed.

S530. In response to an error in the comparison result of the result data, stop the verification process.

In the embodiment of the present disclosure, the comparison component 500 compares each result data with the corresponding expected result data in real time, thereby determining the comparison result between the two. If the comparison results between the two are consistent, it means that the processing function of the pixel data of the component 300 to be verified is correct, and the verification process continues, waiting for the comparison result of the next result data. If the comparison results between the two are inconsistent, it means that there is an error in the processing function of the pixel data of the component 300 to be verified, and the verification process can be stopped immediately and an error is reported.

It can be seen from the above that in the embodiment of the present disclosure, the result data can be compared in real time without waiting for all the stimulus data processing to be completed. Therefore, when an error in the comparison result is found, the verification process will be stopped immediately to report an error, and there is no need to spend a lot of time finding the error location and error. By tracing back waveforms, error codes can be determined by tracing back fewer waveforms, improving chip verification efficiency.

As shown in Figure 1, in the traditional chip verification method, during the data comparison process on the scoreboard, only the data signals are compared, while the timing signals are ignored. In the result data output by the component 300 to be verified, timing signal errors may not have much impact on the current components of the RTL design, but may have a fatal impact on lower-level components. As the RTL design gradually improves, timing errors may cause errors in the entire chip process. .

Therefore, in the embodiment of the present disclosure, the comparison component 500 not only compares the data signals of the result data, but also compares the timing signals of the result data, which will be described below with reference to the embodiment of FIG. 6 .

As shown in Figure 6, in some embodiments, in the chip verification method of the present disclosure, the comparison component 500 performs data comparison and obtains the comparison result, including:

S610. For each result data, compare the data signal of the result data with the expected data signal of the corresponding expected result data to obtain the first result.

S620: Compare the timing signal of the result data with the expected timing signal of the corresponding expected result data to obtain the second result.

S630. Determine the comparison result corresponding to the result data according to the first result and the second result.

As shown in FIG. 2 , in the embodiment of the present disclosure, each time the comparison component 500 receives a result data output by the component 300 to be verified, it compares the data signal included in the result data with the expected data signal of the expected result data, thereby obtaining two results. the first result. On this basis, the comparison component 500 simultaneously compares the timing signals included in the result data with the expected timing signals of the expected result data to obtain the second result. Then combine the first result and the second result result, determine the comparison result corresponding to the result data.

In some embodiments, the timing detection model can be pre-configured in the comparison component 500, and the timing detection model can be used to compare the timing signals of the result data to determine whether the output timing and output quantity of the timing signal of the result data are correct, that is, obtain Second result.

It can be understood that the first result represents the correctness of the data signal of the result data, and the second result represents the correctness of the timing signal of the result data, so that the comparison result obtained by combining the two includes both the data signal and the timing signal. result. When there is an error in either of the two, it means that the comparison result of the result data is an error, and the verification process is stopped based on the foregoing implementation method and an error is reported. On the contrary, if both results are correct, it means that the comparison result of the result data is correct, and the verification process continues.

From the above, it can be seen that in the embodiment of the present disclosure, when comparing the result data with the expected result data, not only the data signals are compared, but also the timing signals are compared to ensure the accuracy of the timing signals and improve the accuracy of chip verification.

FIG. 7 shows a schematic structural diagram of a verification platform in some embodiments of the present disclosure. The embodiments of the present disclosure will be further described below in conjunction with FIG. 7 .

In some embodiments, compared with the verification platform of the embodiment of Figure 2, in the example of Figure 7, the incentive data component 100 is split into a data generation component 110 and an incentive component 120, and the data generation component 110 is separated from the verification outside the environment.

This is because the verification environment needs to be pre-configured during the chip verification process, and during chip verification, different stimulus data needs to be configured for different use cases to be tested. Especially for complex chips such as ISP chips, it is necessary to modify the stimulus data during the verification process. Very common and frequent. In the traditional UVM platform shown in Figure 1, for example, since the stimulus generation component that generates stimulus data is configured in the verification environment, when modifying the stimulus data, the entire verification environment needs to be recompiled. The compilation process is time-consuming and labor-intensive. This leads to inefficiency in the entire verification process.

In the embodiment illustrated in Figure 7 of the present disclosure, the data generation component 110 is separated from the verification environment, that is, the stimulus data is generated outside the verification environment. In this way, when the stimulus data needs to be modified, only the data generation component needs to be modified. 110 can be recompiled. There is no need to recompile the entire verification environment and RTL, which shortens verification time.

In addition, since the data generation component 110 is separated from the verification environment, it means that the component is no longer limited to compilation using the System Verilog hardware design language, and can be compiled using other programming languages, such as python, perl, C++, etc., which shortens the time It reduces configuration time and is more suitable for some scenarios where it is difficult to generate data using the System Verilog hardware design language, greatly reducing development time.

Referring to FIG. 7 , in the embodiment of the present disclosure, the incentive component 120 in the verification environment no longer has the function of data generation, but only forwards data. That is, the data generation component 110 located outside the verification environment produces The stimulus data is generated and sent to the stimulus component 120 in the verification environment, and the stimulus component 120 sends the stimulus data to the input agent component 200.

In some embodiments, as shown in FIG. 7 , since the data generation component 110 is separated from the verification environment, the reference model component 400 can also be separated from the verification environment. The advantages of this are: first, since both the data generation component 110 and the reference model component 400 are separated from the verification environment, the generated stimulus data does not need to be forwarded by the input agent component 200 and can be directly generated by the data generation component 110 outside the verification environment. Sent to the reference model component 400, so that before the verification process starts, the reference model component 400 can perform the work and provide expected result data for the subsequent comparison process earlier; secondly, since the reference model component 400 separates the verification model, the verification The excitation component 120 and the input agent component 200 in the environment do not need to consider the process of sending data to the reference model component 400 and avoid calling the transmission data interface. At the same time, the verification environment reduces component modules and improves the compilation speed of the verification environment.

The data generation component 110 generates stimulus data outside the verification environment, and directly sends the stimulus data to the reference model component 400 outside the verification environment. The reference model component 400 obtains expected result data through data processing, and sends the expected result data to the verification Environment.

In some implementations, as shown in Figure 7, compared to the traditional UVM verification platform shown in Figure 1, in the implementation of the present disclosure, the data comparison function of the scoreboard and the above-mentioned timing signal comparison function are integrated into the output agent component In 510, that is, the output agent component 510 is used to realize all the functions of the comparison component 500 in Figure 2.

This is taken into account that since the reference model component 400 has separated out the verification model, comparison of the data signals does not have to be performed in the scoreboard. In addition, it can be seen from the above-mentioned embodiments of the present disclosure that the present disclosure not only compares the data signals of the result data, but also compares the timing signals, and the comparison process of the timing signals by the scoreboard is very cumbersome.

Therefore, in the embodiment of the present disclosure, the comparison function of data signals and timing signals is integrated into the output agent component 510, and the output agent component 510 is recompiled. On the basis of realizing the above comparison function, the efficiency of chip verification can be improved and shortened. Validation cycle.

In some implementations, as shown in FIG. 7 , the disclosed example provides a separate configuration agent component 210 in the verification environment for data input of the component 300 to be verified.

The input agent component 200 is used to receive the stimulus data forwarded by the stimulus component 120, and send the stimulus data pixel by pixel to the component to be verified 300 according to a preset timing sequence. The function of the configuration agent component 210 is to provide configuration parameters for data processing of the component to be verified 300. The configuration parameters may include register configuration parameters of the component to be verified 300, processing parameters for pixel data, etc.

Of course, those skilled in the art can understand that the corresponding functions of the configuration agent component 210 can be integrated into the input In the proxy component 200 , the purpose of setting up and configuring the proxy component 210 separately in this disclosure is to better detect the function coverage information of the use case to be tested and the component 300 to be verified.

Specifically, as shown in Figure 7, the verification platform of the present disclosure example is provided with a coverage detection component 700 in the verification environment. The coverage detection component 700 is used to detect in real time the configuration information of the incentive data configured by the configuration agent component 210. The configuration The information can reflect the function coverage of the component to be verified 300 in the incentive data. For example, the coverage detection component 700 can detect the register configuration parameters of the configuration agent component 210, and by detecting the register configuration, it can reflect the function coverage of the component to be verified 300 during the verification process. The coverage detection component 700 can record the execution status of each coverage point (Cover Point) in real time according to the configuration information of the stimulus data, thereby obtaining functional coverage information.

The functional coverage information can reflect the functional coverage of the component to be verified 300 by the use case to be tested. If the coverage is very low, it means that the use case to be tested cannot properly verify the complete function of the component to be verified 300, so the incentive data needs to be readjusted. That is the process of modifying the incentive data mentioned above. In other words, in the embodiment of the present disclosure, the functional coverage information obtained through the coverage detection component 700 can effectively guide the targeted modification of the stimulus data of the use case to be tested and improve the chip verification efficiency.

With reference to FIG. 7 , the construction and verification process of the chip verification platform in the embodiment of the present disclosure will be described below.

As shown in FIG. 7 , firstly, the agent components need to be determined according to the RTL design of the component to be verified 300 and the reference model component 400 , such as the input agent component 200 , the configuration agent component 210 and the output agent component 510 . Secondly, the counting control component 800 and the coverage detection component 700 are constructed at the same level as the proxy component, and then each of the aforementioned functional components can be instantiated according to the environment variable (Env). Then build the incentive component 120 and the verification environment, and finally build the executable files of the data generation component 110 and the reference model component 400 to complete the construction of the verification platform. The component to be verified 300, the reference model component 400, the input agent component 200, the configuration agent component 210, the output agent component 510, the counting control component 800, the coverage detection component 700, the stimulus data component 100, the comparison component 500, and the stimulus mentioned in this disclosure Component 120 and data generation component 110 may be implemented by a computer.

During the verification process, the data generation component 110 generates stimulus data and sends the stimulus data to the reference model component 400. The reference model component 400 processes the stimulus data to obtain expected result data, and sends the expected result data to the output in the verification environment. Agent component 510.

At the same time, the data generation component 110 sends the stimulus data to the stimulus component 120 in the verification environment, and the stimulus component 120 forwards the stimulus data to the input agent component 200 and the configuration agent component 210 respectively. The input agent component 200 and the configuration agent component 210 send the incentive data to the component to be verified 300 in time sequence. At the same time, the coverage detection component 700 detects the configuration information output by the configuration agent component 210, records the execution status of each coverage point, and obtains functional coverage information. .

The component to be verified 300 processes the stimulus data one by one according to the time sequence, and outputs the corresponding result data to the output agent component 510. The output agent component 510 performs real-time processing on the data signals and time series signals of the received result data based on the expected result data obtained in advance. Compare and obtain the comparison results corresponding to the result data. At the same time, the counting control component 800 detects the target signal in the result data in real time and makes statistics. When the target signal data meets the preset conditions, it sends a stop signal to the excitation component 120 and the entire verification process stops.

As can be seen from the above, in the embodiments of the present disclosure, during the chip verification process, by detecting the number of target signals in the result data output by the component to be verified DUT, the processing progress of the stimulus data can be accurately detected, and the end of the verification process can be accurately determined. time, not only to avoid early termination leading to verification failure, but also to avoid long delays leading to reduced verification efficiency. Moreover, the disclosed method can be applied to any chip verification scenario and is not limited by chip type, thereby improving the robustness of the verification platform. There is no need to wait for all stimulus data processing to be completed, and the result data can be compared in real time. When an error in the comparison result is found, the verification process will be stopped immediately and an error will be reported. The error code can be discovered immediately without the need for a large number of traceback waveform operations, which improves chip verification efficiency. . When comparing the result data with the expected result data, not only the data signals are compared, but also the timing signals are compared to ensure the accuracy of the timing signals and improve the accuracy of chip verification.

In some embodiments, embodiments of the present disclosure provide an electronic device, including: a processor; and a memory storing computer instructions, and the computer instructions are used to cause the processor to execute the chip verification method of any of the above embodiments.

In some embodiments, embodiments of the present disclosure provide a storage medium that stores computer instructions, and the computer instructions are used to cause the computer to execute the chip verification method of any of the above embodiments.

Specifically, FIG. 8 shows a schematic structural diagram of an electronic device 600 suitable for implementing the method of the present disclosure. Through the electronic device shown in FIG. 8 , the corresponding functions of the above-mentioned processor and storage medium can be realized.

As shown in FIG. 8 , the electronic device 600 includes a processor 601 that can perform various appropriate actions and processes according to programs stored in the memory 602 or loaded into the memory 602 from the storage part 608 . In the memory 602, various programs and data required for the operation of the electronic device 600 are also stored. The processor 601 and the memory 602 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., speakers, etc.; and a storage section 608 including a hard disk, etc. ; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. Driver 610 is also connected to I/O interface 605 as needed. Removable media 611, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 610 as needed, so that a computer program read therefrom is installed into the storage portion 608 as needed.

In particular, according to embodiments of the present disclosure, the above method process may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program tangibly embodied on a machine-readable medium, the computer program including program code for performing the above-described method. In such embodiments, the computer program may be downloaded and installed from the network via communication portion 609 and/or installed from removable media 611 .

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more components for implementing the specified logical function. Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or operations. , or can be implemented using a combination of specialized hardware and computer instructions.

Obviously, the above-mentioned embodiments are only examples for clear explanation and are not limitations of the embodiments. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is neither necessary nor possible. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims (17)

1. A chip verification platform, which is characterized by including:

   The stimulus data component is configured to generate stimulus data based on the use case to be tested, and send the stimulus data to the component to be verified;

   A counting control component configured to detect and count target signals of the result data output by the component to be verified in real time during the verification process, and in response to the number of the target signals meeting a preset condition, determine verification of the use case to be tested End; the target signal represents the timing-related signal of the result data.
2. The chip verification platform according to claim 1, characterized in that the counting control component is configured to:

   Determine the expected amount of result data in advance based on the use case to be tested;

   In response to the number of target signals reaching the expected number, it is determined that the number of target signals satisfies a preset condition.
3. The chip verification platform according to claim 1 or 2, further comprising:

   A reference model component configured to receive the stimulus data and output corresponding expected result data;

   A comparison component, configured in the verification environment, used to compare the result data output by the component to be verified with the expected result data in real time during the verification process to obtain a comparison result corresponding to the result data. ; In response to an error in the comparison result of the result data, the verification process is stopped.
4. The chip verification platform according to claim 3, wherein the result data includes a data signal and a timing signal, and the expected result data includes an expected data signal and an expected timing signal; the comparison component is configured to:

   Compare the data signal of the result data with the expected data signal of the expected result data to obtain a first result;

   Compare the timing signal of the result data with the expected timing signal of the expected result data to obtain a second result;

   The comparison result corresponding to the result data is determined based on the first result and the second result.
5. The chip verification platform according to claim 3 or 4, characterized in that the stimulus data component includes:

   A data generation component configured outside the verification environment and used to generate the stimulus data based on the use case to be tested;

   An excitation component, configured in the verification environment, is used to receive the excitation data and send the excitation data to the component to be verified;

   Wherein, the data generation component is configured to send the stimulus data to the reference model component, and the reference model component is configured outside the verification environment.
6. The chip verification platform according to claim 5, wherein the comparison component is configured as an output proxy component.
7. The chip verification platform according to any one of claims 1 to 4, further comprising:

   A configuration agent component, configured in the verification environment, is used to generate and send configuration information to the component to be verified according to the incentive data;

   A coverage detection component is configured in the verification environment, used to detect the configuration information, and determine the functional coverage information of the use case to be tested based on the configuration information.
8. A chip verification method, characterized by including:

   Generate stimulus data based on the use case to be tested and send the stimulus data to the component to be verified;

   During the verification process, the target signal of the result data output by the component to be verified is detected in real time and counted; the target signal represents the timing-related signal of the result data;

   In response to the number of the target signals meeting the preset condition, it is determined that the verification of the use case under test is completed.
9. The method according to claim 8, characterized in that, in response to the number of the target signals meeting a preset condition, determining that the verification of the use case to be tested is completed, including:

   Determine the expected amount of result data in advance based on the use case to be tested;

   In response to the number of target signals reaching the expected number, it is determined that the number of target signals satisfies a preset condition.
10. The method according to claim 8 or 9, further comprising:

    Send the stimulus data to the reference model component to obtain the expected result data output by the reference model component;

    During the verification process, compare the result data output by the component to be verified with the expected result data in real time to obtain a comparison result corresponding to the result data;

    In response to the comparison result of the result data being erroneous, the verification process is stopped.
11. The method according to claim 10, wherein the result data includes a data signal and a timing signal, and the expected result data includes an expected data signal and an expected timing signal; during the verification process, all data are processed in real time. Compare the result data output by the component to be verified with the expected result data to obtain a comparison result corresponding to the result data, including:

    Compare the data signal of the result data with the expected data signal of the expected result data to obtain a first result;

    Compare the timing signal of the result data with the expected timing signal of the expected result data to obtain the first 2 results;

    The comparison result corresponding to the result data is determined based on the first result and the second result.
12. The method according to claim 10 or 11, characterized in that generating stimulus data based on the use case to be tested and sending the stimulus data to the component to be verified includes:

    The data generation component outside the verification environment sends the stimulus data generated based on the use case to be tested to the stimulus component in the verification environment. In the verification environment, the stimulus component sends the stimulus data to the Components to be verified;

    The step of sending the stimulus data to the reference model component and obtaining the expected result data output by the reference model component includes:

    The data generation component sends the stimulus data to a reference model component outside the verification environment, and the reference model component outside the verification environment sends the expected result data to the verification environment.
13. The method according to claim 12, characterized in that, during the verification process, the result data output by the component to be verified is compared with the expected result data in real time to obtain the corresponding result data The comparison results include:

    In the verification environment, the output agent component receives the result data and the expected result data respectively, and compares the result data with the expected result data in real time to obtain the comparison result.
14. The method according to any one of claims 8 to 13, further comprising:

    In the verification environment, the configuration information of the stimulus data sent to the component to be verified is detected, and the functional coverage information of the use case to be tested is determined based on the configuration information.
15. The method according to any one of claims 8 to 14, characterized in that,

    The target signal includes one or more of a valid signal, a preparation signal, a line start signal, and a line end signal.
16. An electronic device, characterized by including:

    processor;

    A memory storing computer instructions for causing the processor to execute the method according to any one of claims 8 to 15.
17. A storage medium, characterized in that computer instructions are stored, and the computer instructions are used to cause a computer to execute the method according to any one of claims 8 to 15.