CN117454811A - Verification method and device for design to be tested - Google Patents
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Abstract
The embodiment of the invention provides a verification method and a device for a design to be tested, wherein the method comprises the following steps: inputting data to be tested into the DUT, and obtaining first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-detected sub-design in the DUT, and the to-be-detected sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on register conversion base level RTL description of the DUT; inputting the data to be tested into the RM corresponding to the DUT, and obtaining a second output result of each sub-model contained in the RM; each sub-model corresponds to one sub-design to be tested; and verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point. The accuracy and the debugging efficiency of chip verification can be improved.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method and an apparatus for verifying a design to be tested.
Background
With the development of chip manufacturing technology, chip design and verification becomes more and more complex. In the chip design and verification process, RM (Reference Model) is a very important ring. RM refers to simulating and testing a chip by means of software or hardware, etc., to check the correctness and performance of the chip.
The conventional RM design method usually adopts a black box verification method, however, the verification method can only verify the accuracy of the DUT operation result, and cannot guarantee the accuracy of the DUT (Design under Test ) operation process, and cannot meet the verification requirement for the DUT with complex design.
Disclosure of Invention
The embodiment of the invention aims to provide a verification method and device for a design to be tested, so as to improve the accuracy and the debugging efficiency of chip verification. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention provides a verification method for a design to be tested, including:
inputting data to be tested into a design under test DUT (device under test), and obtaining first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-tested sub-design in the DUT, and the to-be-tested sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on a register conversion base level RTL description of the DUT;
inputting the data to be tested into a reference model RM corresponding to the DUT, and obtaining a second output result of each sub-model contained in the RM; each of the sub-models corresponds to one of the sub-designs under test;
And verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
Optionally, after the inputting the data to be tested into the reference model RM corresponding to the DUT and obtaining the second output result of each sub-model included in the RM, the method further includes:
aiming at the second output result of each sub-model, performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each of the first output results is predetermined based on the RTL description of the DUT;
the verifying the first output result for each target detection point based on the second output result of the sub-model corresponding to the target detection point includes:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to the target detection point aiming at the first output result of each target detection point.
Optionally, the method further comprises:
and verifying the correctness of the target data on a preset signal line and/or a preset cache position in the DUT through a preset assertion statement.
Optionally, the specific action occurrence point includes any one or more of a cache point, a convergence point, a scheduling point, a back pressure point/deletion point and a release point.
In a second aspect, an embodiment of the present invention provides a verification apparatus for a design under test, including:
the first acquisition module is used for inputting data to be detected into the DUT and acquiring first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-detected sub-design in the DUT, and the to-be-detected sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on RTL description of the DUT;
the second acquisition module is used for inputting the data to be detected into the RM corresponding to the DUT and acquiring a second output result of each sub-model contained in the RM; each of the sub-models corresponds to one of the sub-designs under test;
the first verification module is used for verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
Optionally, the method further comprises:
the processing module is used for aiming at the second output result of each sub-model, and performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each of the first output results is predetermined based on the RTL description of the DUT;
the first verification module is specifically configured to:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to the target detection point aiming at the first output result of each target detection point.
Optionally, the method further comprises:
and the second verification module is used for verifying target data on a preset signal line in the DUT and/or verifying data buffering time sequence and data releasing time sequence in the DUT through preset assertion statement.
Optionally, the specific action occurrence point includes any one or more of a cache point, a convergence point, a scheduling point, a back pressure point/deletion point and a release point.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
A memory for storing a computer program;
and the processor is used for realizing the verification method of any one of the designs to be tested when executing the program stored in the memory.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements the verification method of any one of the above designs under test.
The embodiment of the invention also provides a computer program product containing instructions, which when run on a computer, cause the computer to execute the verification method of any of the designs to be tested.
The embodiment of the invention has the beneficial effects that:
according to the verification method and the verification device for the design to be tested, when the DUT is verified, the DUT is split into a plurality of sub-designs to be tested based on specific behavior occurrence points of data flow in the DUT in advance, and each sub-design to be tested carries out corresponding processing on data based on logic of the sub-design to be tested. On this basis, the verification process for the DUT is substantially decoupled for verification of the plurality of sub-designs under test contained therein, that is, for verification of the final output result of the DUT, and for verification of the output result of the target detection point corresponding to each sub-design under test. Thus, when designing the RM, the sub-model corresponding to each sub-design to be tested in the DUT can be designed based on the function that each sub-design to be tested is expected to realize.
In the verification process, data to be tested are input into the DUT and the RM respectively, and the output result of the DUT at each target detection point is verified based on the output result of the sub-model corresponding to the RM and the target detection point. Compared with the traditional verification method, the method can realize verification of accuracy of the operation result of the DUT, and can also verify whether the function of a specific sub-design to be tested in the DUT meets the expectations or not in the operation process, so that the situation that the operation result is correct but the operation process does not meet the expectations in practice is avoided. And when the output result of any target detection point does not meet the expectation, the position where the bug appears can be positioned in the specific sub-design to be detected in a relatively simplified way, so that bug analysis and elimination are convenient, the debugging efficiency is improved, the verification accuracy is higher, and the verification effect is better.
Of course, it is not necessary for any one product or method of practicing the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other embodiments may be obtained according to these drawings to those skilled in the art.
FIG. 1 is a schematic diagram of a chip verification platform according to an embodiment of the present invention;
FIG. 2 is a flow chart of a verification method for a design under test according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a sub-design under test in a DUT provided by an embodiment of the invention;
FIG. 4 is a schematic diagram of a data flow structure provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of a verification device for a design under test according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art will be able to devise all other embodiments that are obtained based on this application and are within the scope of the present invention.
Fig. 1 is a schematic diagram of a chip verification platform provided in an embodiment of the present invention, and for convenience of understanding, a possible application scenario of the embodiment of the present invention is first described in the following with reference to fig. 1.
Chip verification, in particular, verifies whether the implementation of the chip design is consistent with the design intent. In the chip verification step, the chip to be tested is called DUT, which can be understood as a sequential circuit written by verilog (a hardware description language). To test the correctness of a DUT, it is often necessary to design an RM corresponding to the DUT, where the RM is used to perform the same function as the DUT, and the output of the RM is considered to be the expected output of the DUT. Therefore, verification of the DUT can be achieved by comparing consistency between the RM and the output results of the DUT.
Referring to fig. 1, the chip verification platform specifically includes driver (driver), DUT, RM, monitor (monitor), and scoreboard (scoreboard). Wherein driver, RM, monitor and scoreboard are derived specifically by classes in the verification environment env of the chip verification platform, and in the chip verification platform, communication between the above-mentioned different components is typically implemented using TLM (Transaction Level Modeling ) mechanisms.
In the chip verification platform shown in fig. 1, the driver is specifically configured to apply different stimuli to the DUT, the DUT may generate an output result to be verified after receiving the corresponding stimuli, and the chip verification platform monitors the output result of the DUT, converts the output result of the DUT into output data having the same data structure as the output result of the RM, and sends the output data to the scoreboard. The RM is used to perform the same function as the DUT, its input data is consistent with the DUT, and its output data is specifically sent to the scoreboard. The Scoreboard is specifically configured to compare the received output result of the DUT with the output result of the RM, so as to determine whether the output result of the DUT meets the expectations.
However, the conventional black box verification method can only verify the accuracy of the operation result of the DUT, and cannot ensure the accuracy of the operation process of the DUT, and cannot meet the verification requirement for the DUT with complex design.
In order to solve the above-mentioned problems, an embodiment of the present invention provides a verification method of a to-be-tested design, and fig. 2 is a schematic flow chart of the verification method of the to-be-tested design provided in the embodiment of the present invention, referring to fig. 2, the method specifically includes the following steps:
step S201: inputting data to be tested into the DUT, and obtaining first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one sub-design to be tested in the DUT, and the sub-design to be tested is obtained by splitting the DUT according to specific behavior occurrence points of the data flow in the DUT based on RTL description of the DUT.
In an embodiment of the invention, the DUT, i.e., the object that needs to be verified in the chip verification process. In particular, in the process of designing a chip, an RTL code is generally used to describe the chip. In practice of the invention, the object to be verified can thus be understood as a pre-designed RTL code or RTL description.
Based on the foregoing, it can be seen that since the output data of the RM is specifically considered as the expected output data of the DUT when chip verification is performed, the design accuracy and design rationality of the RM play a crucial role in the verification effect of the chip. For the conventional chip verification method, the RM is written specifically based on the functions and features of the DUT, and the written RM has the same functions as the DUT.
For DUTs implemented by RTL description, the designer will describe the circuitry specifically in terms of the flow and handling of data between registers when writing the RTL code. Thus, analysis of the data flow within the DUT can be accomplished based on the RTL code, determining the flow and processing of data between different components within the DUT during the input to output, so that the design within the DUT can be logically decoupled into multiple sub-designs in nature from the perspective of the data flow. That is, throughout the process of entering data into the DUT and outputting processing results from the DUT, the decoupled sub-designs within the DUT will in turn process the data accordingly based on their own logic, and the output data from the current sub-design, i.e., the input data to be streamed into the next sub-design. In this regard, the internal logic of each sub-design may be considered independent of the internal logic of the other sub-designs.
Fig. 3 is a schematic diagram of a design under test sub-design in a DUT according to an embodiment of the invention, see fig. 3, a1 being data under test input into the DUT, and a5 being result data output from the DUT. In the example of fig. 3, the DUT may be specifically decoupled from the perspective of data flow into four sub-designs a through D, each corresponding to a portion of the sequential circuitry inside the DUT and capable of processing the data inside it accordingly based on its own logic. Thus, the DUT processes a1 as a5, specifically includes a process of a processing a1 as a2, B processing a2 as a3, C processing a3 as a4, and D processing a4 as a 5. Since the sub-designs a through D are each used to implement a specific function, verification of the DUT can be actually performed by verifying the four sub-designs a through D.
The conventional chip verification method specifically verifies the output result of the DUT, and on the basis of disassembling the DUT into a plurality of sub-designs to be tested, when verifying the DUT, the output result of each sub-design to be tested in the DUT can be verified. Since the sub-design under test is actually only a logical split result for the DUT, without substantially disassembling the DUT to be tested, the DUT as a whole can still be verified with the data under test input during the test. In this case, in order to obtain the output result of each sub-design to be tested, the corresponding data output position of each sub-design to be tested in the DUT is specifically required to be used as a target detection point according to the logic splitting result of the sub-design to be tested, and after the data to be tested is subsequently input into the DUT, the output result of the DUT at each target detection point is specifically required to be obtained.
As an example, for the sub-designs a to D to be tested in fig. 3, it is specifically required to determine four target detection points in the DUT, so that output results of the sub-designs a to D to be tested can be obtained at output positions corresponding to a2, a3, a4, and a5, respectively.
In the embodiment of the invention, when the DUT is split from the perspective of the data flow, the split of the DUT can be specifically performed according to the specific behavior occurrence point of the data flow in the DUT.
By splitting the DUT, it is mentioned above that the verification for the DUT can be decoupled in particular into the verification for the individual sub-designs to be tested that it contains, i.e. the subsequent positioning of the occurrence of the bug to the specific sub-design to be tested can be simplified. From the point of view of verification efficiency, if data is simply transferred between some components inside the DUT, the possibility of a bug occurring in the some components is not high, and it is not necessary to split the some components into a plurality of sub-designs to be tested. Therefore, in the embodiment of the invention, the specific behaviors of the data flow can be specified according to actual requirements, the data flow in the DUT is considered to be more prone to be bugs when the specific behaviors occur, so that when the DUT is split, the specific flow and the processing process of the data in the DUT can be analyzed according to RTL description to determine the specific behavior occurrence points of the data flow in the DUT, and then the DUT is split and the target detection points are determined based on the specific behavior occurrence points.
Taking fig. 3 as an example, the sub-designs to be tested a to D in the DUT may be specifically obtained by splitting the DUT based on specific behavior occurrence points p1 to p3 of the data flow, where a is used for processing data between an input point of the DUT and p1, B is used for processing data between p1 and p2, and C and D are the same.
The embodiment of the invention does not specifically limit the range of the specific behavior occurrence point of the data stream, and as an example, the specific behavior occurrence point of the data stream can specifically include a convergence point, a cache point, a release point and the like of the data stream.
Step S202: inputting the data to be tested into the RM corresponding to the DUT, and obtaining a second output result of each sub-model contained in the RM; each sub-model corresponds to one sub-design under test.
The foregoing mentions that splitting a DUT into multiple sub-designs under test, in effect splitting verification for the DUT into verification for these sub-designs under test. The RM is specifically configured to verify whether the actual implementation of a specific function is consistent with the expected implementation of the specific function, so that, based on splitting the DUT into a plurality of sub-designs to be tested, a sub-model corresponding to each sub-design to be tested can be designed based on the function expected to be implemented by each sub-design to be tested, and the RM corresponding to the DUT can be obtained.
Taking fig. 3 as an example, specifically, RMs corresponding to a to D may be designed based on the functions that each of the sub-designs to be tested expects to realize, respectively. inthiscase,theRMcorrespondingtotheDUTmayspecificallyincludeasub-modelRM-AcorrespondingtoA,asub-modelRM-BcorrespondingtoB,asub-modelRM-CcorrespondingtoC,andasub-modelRM-DcorrespondingtoD,wherethesub-modelRM-AisusedtoperformthesamefunctionasA,andthesub-modelsRM-BthroughRM-Darethesame.
In the foregoing, a DUT is specifically understood as a sequential circuit implemented by verilog language, and thus the function of the DUT is actually implemented based on hardware-level logic. Whereas RM is simply equivalent in terms of its intended function, logically distinct from DUT in terms of its specific implementation. In practical application, a developer can use a programming language which is more abstract than verilog to realize the function according to the expected realization function of the sub-design to be tested, and develop the RM corresponding to the sub-design to be tested. As an example, the design of the RM may be performed by System Verilog (a programming language) or c++ (a programming language).
After the design of each sub-model included in the RM is completed, in the process of verifying the DUT, the data to be tested input into the DUT is specifically required to be input into the RM, and the output result of each sub-model is obtained. It should be understood that the RM is actually a piece of program code, and thus each sub-model can be understood in particular as a part of the code segments in the complete code of the RM, and the output of the current code segment, i.e. the input of the next code segment.
Step S203: and verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
In the foregoing, each target detection point corresponds to one sub-design to be tested of the DUT, the first output result of the target detection point can be specifically understood as the output result of the corresponding sub-design to be tested, and each sub-design to be tested corresponds to one sub-model of the RM, so that each target detection point specifically corresponds to one sub-model.
Therefore, any sub-design to be tested is verified, specifically, the first output result of the target detection point corresponding to the sub-design to be tested is verified. And when verifying the first output result of any target detection point, in particular, verifying the first output result based on the second output result of the sub-model corresponding to the target detection point. In the foregoing, the sub-model is used for implementing the same function as the to-be-tested sub-design, and the output result of the sub-model is considered as the expected output result of the to-be-tested sub-design, so that in the actual verification process, if the first output result of any one target detection point is consistent with the corresponding second output result, the implementation of the corresponding to-be-tested sub-design can be considered as meeting the expected, and if the first output result of any one target detection point is inconsistent with the corresponding second output result, the implementation of the corresponding to-be-tested sub-design can be considered as not meeting the expected.
takingthepreviousexample,theverificationprocessoftheDUTisexemplarilydescribedwithreferencetoFIG.3,andifthesecondoutputresultsofthesub-modelsRM-AtoRM-Darea2',a3',a4',anda5',respectively,theDUTisverified,specifically,consistencybetweena2anda2',betweena3anda3',betweena4anda4',andbetweena5anda5'iscompared. Illustratively, if a2 and a2' are not identical, verification of the DUT is considered to be failed, and because a2 is specifically obtained after processing a1 for the sub-design under test A, the location in the DUT where the bug occurs can be specifically located within the sub-design under test A.
According to the verification method for the design to be tested, when the DUT is verified, the DUT is split into a plurality of sub-designs to be tested based on specific behavior occurrence points of data flow in the DUT in advance, and each sub-design to be tested carries out corresponding processing on data based on logic of the sub-design to be tested. On this basis, the verification process for the DUT is substantially decoupled for verification of the plurality of sub-designs under test contained therein, that is, for verification of the final output result of the DUT, and for verification of the output result of the target detection point corresponding to each sub-design under test. Thus, when designing the RM, the sub-model corresponding to each sub-design to be tested in the DUT can be designed based on the function that each sub-design to be tested is expected to realize.
In the verification process, data to be tested are input into the DUT and the RM respectively, and the output result of the DUT at each target detection point is verified based on the output result of the sub-model corresponding to the RM and the target detection point. Compared with the traditional verification method, the method can realize verification of accuracy of the operation result of the DUT, and can also verify whether the function of a specific sub-design to be tested in the DUT meets the expectations or not in the operation process, so that the situation that the operation result is correct but the operation process does not meet the expectations in practice is avoided. And when the output result of any target detection point does not meet the expectation, the position where the bug appears can be positioned in the specific sub-design to be detected in a relatively simplified way, so that bug analysis and elimination are convenient, the debugging efficiency is improved, the verification accuracy is higher, and the verification effect is better.
In addition, in chip verification, verification of a timing related complex data path is a very important and weak ring, and is one of the most complex parts in verification of a data path module. Verification of timing-related data paths not only takes into account the accuracy and stability of data transmission, but also takes into account timing issues.
Considering timing issues, it can be understood that: in the chip verification process, a mechanism for strictly comparing according to time sequence exists, and comparison is required according to the sampling result of the rising edge of the DUT clock. The timing alignment mechanism has the advantages of accuracy and real-time performance, but has the difficulty of accuracy and real-time performance, and the alignment mechanism can greatly increase the design difficulty and the coding difficulty of the RM.
The traditional RM design method generally adopts a non-time sequence method, namely, the output results of the RM/DUT are sequentially stored in the queue according to the output sequence, and when the result comparison is carried out, the scoreboard of the chip verification platform sequentially takes out the result data in the queue according to the sequence, and sequentially compares the output results of the RM and the DUT.
However, this verification method is only suitable for design codes whose output sequence is irrelevant to the DUT timing and the internal storage empty-full state, and when the DUT characteristics are that the output result is relevant to the timing and the DUT internal storage empty-full state, the conventional RM cannot simulate the empty-full state of the timing and the real queue, and cannot meet the requirement of verifying the output result of the DUT in terms of timing.
To solve this problem, the strongly clocked RM employs a white-box verification strategy, i.e., system Verilog implements the same logic as the DUT entirely according to the design of the DUT, and ensures that each beat of output data of the RM is tightly synchronized with the DUT. Such verification strategies typically use data from the interfaces and RMs of the DUT to be compared or verified directly on a clock edge by cycle basis, or for some logic that is more difficult to implement, by pulling the DUT signal.
However, the RM with strong timing is suitable for design codes with strong correlation between output sequence and DUT timing and internal storage empty-full state by using a comparison mechanism sampling according to clock edges, and needs to be verified by using a white box verification strategy. When the DUT characteristics are such that the output results are not closely related to the timing and the DUT internal memory empty-full state, the output timing of the DUT is difficult to expect, RM with strong timing is not suitable, and there is a risk in the manner of pulling the DUT signal, so that a new verification method is required.
Moreover, the RM with strong time sequence is particularly required to be realized by adopting a System Verilog language, and because the language is developed on the basis of the Verilog language and the logic of the DUT is required to be strictly simulated by the RM, the similarity between the compiled RM realization logic and the DUT realization logic is higher, so that the written RM is easy to have a tendency error with the DUT to be verified, the bug existing in the DUT cannot be accurately detected by taking the output result of the RM as a reference, and the verification accuracy and reliability are insufficient.
In view of this, in one embodiment of the present invention, a verification method capable of implementing a timing precision comparison mechanism is provided, where in the embodiment, after inputting data to be tested into an RM corresponding to a DUT and obtaining a second output result of each sub-model included in the RM, the method further includes:
Aiming at the second output result of each sub-model, performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each first output result is predetermined based on the RTL description of the DUT;
correspondingly, the verifying the first output result based on the second output result of the sub-model corresponding to the target detection point for the first output result of each target detection point includes:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to each target detection point aiming at the first output result of each target detection point.
As mentioned above, DUT is a specific implementation performed at the hardware level according to the expected function of the chip, so DUT needs to be performed in a beat-to-beat manner according to clock in the process of processing the data to be tested, which consumes a lot of simulation time. In the implementation of an RM through a programming language such as c++, the RM theoretically has no clock, so the RM consumes only execution time, which is almost negligible compared to emulation time. Therefore, when the chip verification platform shown in fig. 1 is applied, the output result of the RM will preferentially reach the scoreboard, so that the timing sequence of the DUT cannot be verified based on the output result of the RM, and one-to-one real-time comparison between the output result of the RM and the output result of the DUT cannot be realized.
In the embodiment of the invention, in order to verify the time sequence of the DUT and realize real-time comparison, the RM design with weak time sequence is adopted, specifically, according to the logic characteristic of data from input to output in the DUT, the output result of the RM and the output result of the DUT are synchronous by adopting a time delay technology.
Specifically, in practical application, from the design scheme of the DUT, specific logic of data inside the DUT can be analyzed in combination with the RTL description to determine the expected output timing of the output result of the DUT. When special conditions such as data backpressure exist, the specific expected output time sequence can be determined by combining an external backpressure signal.
After determining the expected output time sequence of the output result of the target detection point in the DUT, beating processing can be carried out on the output result of the sub-model corresponding to the target detection point, so that the output result of the sub-model is aligned with the output result time sequence of the target detection point.
After the output results of the submodels are subjected to beat processing, the output results of the DUT at each target detection point, the output results of the submodels contained in the RM are aligned in strict time sequence and data are aligned, so that the comparison between the output results of the DUT and the output results of the RM can be directly carried out according to the time sequence.
takingfig.3asanexample,ifnbeatsofoutputresultdataofthesub-designatobetestedafterthesub-modelRM-aoutputstheresultareexpected,afterthesub-modelRM-aobtainsitsownoutputresult,theoutputresultofRM-aisbeaten,sothattheoutputtimingoftheoutputresultisalignedwiththetimingoftheoutputresultofa. On the basis, when the output data of the DUT is verified, because the output data of the RM is synchronous with the output data of the DUT, the output data of the DUT and the output data of the RM can be compared in a beat-to-beat mode based on a clock, and real-time detection is achieved.
In the embodiment of the invention, the synchronization of the output time sequence between the RM and the DUT is carried out in a weak time sequence mode, specifically, the output result of each sub-model of the RM is subjected to beat processing according to the expected output time sequence of the output result of the corresponding target detection point, the time sequence alignment between the output result of the RM and the output result of the DUT is realized, the time sequence uncertainty of the chip under the actual working condition is effectively simulated through the RM of a weak time sequence mechanism, the accurate real-time comparison based on the time sequence is realized, and the verification precision and the reliability are higher.
In addition, the embodiment of the invention does not need to simulate the time sequence in the DUT through the RM, so languages with higher abstraction degree such as C++ can be selected for designing the RM, the designed RM and the DUT have larger difference in realization logic, and the probability of the same error generated by the written RM and the DUT is small, thereby avoiding the problem of insufficient verification accuracy caused by the error of the validity generated by the RM and the DUT.
In one embodiment of the present invention, the specific behavior occurrence points include any one or more of a cache point, a convergence point, a scheduling point, a back pressure point/deletion point, and a release point.
In practice, the specific behavior occurrence points of the data stream in the DUT can be located by analyzing the specific flow direction and processing procedure of the data in the DUT. Fig. 4 is a schematic diagram of a data flow structure provided by an embodiment of the present invention, and the specific behavior occurrence points are briefly described below with reference to fig. 4.
The buffer point is a point for buffering data, referring to fig. 4, the input data inputs 1 to n are stored in the queues 1 to n, so that the buffer point can be determined in the DUT. In practical applications, the back pressure and the delete signal of the subsequent stage may affect the timing of the buffer point, which makes the buffering of the data difficult to expect.
The convergence point, i.e., the point at which the majority of the data streams are converged into a minority of the data streams, see fig. 4, the multiple data streams in queues 1 through n are converged, and thus the convergence point is determined within the DUT. When the input rate of the convergence point is greater than the output rate, blockage is likely to cause back pressure.
The scheduling point is a point using a scheduling algorithm or a random algorithm, and the result is not expected well because the result of the algorithm has microscopic uncertainty. For example, multiple data may need to be selected at a data aggregation point, where data processing is required by a scheduling algorithm or a random algorithm, so that there is a scheduling point at a corresponding location in the DUT, and similarly, there may be a scheduling point at the cache output side of the data. Referring to fig. 4, for the data transmitted in links 1 through n, it is necessary to process the data using a scheduling/random algorithm, so that a scheduling point can be determined at a corresponding location within the DUT.
The back pressure point/delete point is a point that causes the back pressure/delete, or the back pressure of the later module or the gradual back pressure/delete in the module easily complicates the module data flow. For example, a data cache location may result in backpressure/deletion of data due to an excessive cache rate, so that a backpressure/deletion point may be determined at a corresponding location in the DUT.
Release point the point at which data is read out from RAM (Random Access Memory ) is susceptible to unexpected release of cached data due to the complex amount of data in the previous stage. Referring to fig. 4, a release point can be determined on the output side of the data.
Based on the above description, it can be seen that, for the specific behavior occurrence point, it is difficult to accurately construct the verification environment by adopting the strong timing RM due to the complex data path at the corresponding position and timing uncertainty under the actual working condition of the chip. The embodiment of the invention splits the DUT into a plurality of sub designs to be tested based on the specific behavior occurrence point, and delays the output result of the RM through a weak time sequence mechanism so as to ensure that the time sequence of the output result of the RM can effectively simulate the time sequence uncertainty of the chip under the actual working condition, realize the strict comparison between the output results of the DUT and the RM based on the time sequence, improve the accuracy and the reliability of chip verification, and be suitable for the situations that the channel structure of the chip is complex, the DUT characteristics are that the output result is not closely related with the time sequence and the empty-full state in the DUT, or the situation that the response of the excitation is difficult to be obtained through a black box verification method.
Referring to the example of fig. 4, based on the cache point, the convergence point, the scheduling point, the release point, and the back pressure point/deletion point shown therein, the DUT can be split into four sub-designs to be tested, and when the RM design is performed, sub-models RM-1 to RM4 corresponding to sub1 to sub4, respectively, can be designed based on the function that each sub-design to be tested is expected to implement. In this case, verification is performed on sub1, specifically, the output result of the convergence point shown in the drawing of the DUT is compared with the output result of RM-1, and if the output result is inconsistent, the position where the bug appears can be directly located in the sub design sub1 to be tested.
In an embodiment of the present invention, a manner of assertion detection may be used as a supplement to the weak timing verification scheme, so as to further improve accuracy of chip verification, where in the embodiment, the verification method of the to-be-tested design further includes:
and verifying the correctness of the target data on a preset signal line and/or a preset cache position in the DUT through a preset assertion statement.
Specifically, for some complex functions to be implemented by the DUT, the RM may not directly emulate the functions of the DUT, so that a signal line of the DUT needs to be used, and the correctness of the signal line needs to be verified by using the signal line of the DUT.
Where assertions are specifically statements that describe the intended behavior of functions and timing, for example, assertions statements may be used to describe timing relationships between signals, or specific properties of signals. When the actual time sequence relation, the signal attribute and the specific description in the assertion statement are consistent/inconsistent, and the detection result of assertion detection is true/false, when the detection mode of assertion is applied, when the actual condition and description of the signal in the signal line are not consistent, the corresponding function can be determined to not meet the expectations.
In addition, there may be situations where there is an exception in the use of the cache in the actual DUT. In addition, for some DUTs, there may be pre-buffering/pre-releasing of data, which makes it difficult for the RM to align with the DUT in time sequence, and it is difficult to directly apply the detection mechanism of weak time sequence to verify whether the buffer has an abnormal condition, where the assertion method can be specifically used to determine whether the relevant data of the buffer location is correct. As one example, it may be determined by an assertion statement whether a cache in a particular cache address overflows, whether there is an abnormal read-write, whether the application and reclamation of the cache are consistent, and the like. For example, if the application and the recovery of the cache are described by the assertion statement to be consistent, but the DUT has repeated application of the cache in the actual operation process, the application and the descriptor of the assertion statement are different, and at this time, the corresponding abnormal condition in the DUT can be judged according to the execution result of the assertion statement.
Based on the same inventive concept, the embodiment of the present invention further provides a verification device for a design to be tested, referring to fig. 5, the device includes:
a first obtaining module 501, configured to input data to be tested into a DUT, and obtain first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-detected sub-design in the DUT, and the to-be-detected sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on RTL description of the DUT;
a second obtaining module 502, configured to input data to be tested into an RM corresponding to the DUT, and obtain a second output result of each sub-model included in the RM; each sub-model corresponds to one sub-design to be tested;
the first verification module 503 is configured to verify, for a first output result of each target detection point, the first output result based on a second output result of the sub-model corresponding to the target detection point.
According to the verification device for the design to be tested, which is provided by the embodiment of the invention, when the DUT is verified, the DUT is split into a plurality of sub-designs to be tested based on the specific behavior occurrence point of the data flow in the DUT in advance, and each sub-design to be tested carries out corresponding processing on the data based on the logic of the sub-design to be tested. On this basis, the verification process for the DUT is substantially decoupled for verification of the plurality of sub-designs under test contained therein, that is, for verification of the final output result of the DUT, and for verification of the output result of the target detection point corresponding to each sub-design under test. Thus, when designing the RM, the sub-model corresponding to each sub-design to be tested in the DUT can be designed based on the function that each sub-design to be tested is expected to realize.
In the verification process, data to be tested are input into the DUT and the RM respectively, and the output result of the DUT at each target detection point is verified based on the output result of the sub-model corresponding to the RM and the target detection point. Compared with the traditional verification method, the method can realize verification of accuracy of the operation result of the DUT, and can also verify whether the function of a specific sub-design to be tested in the DUT meets the expectations or not in the operation process, so that the situation that the operation result is correct but the operation process does not meet the expectations in practice is avoided. And when the output result of any target detection point does not meet the expectation, the position where the bug appears can be positioned in the specific sub-design to be detected in a relatively simplified way, so that bug analysis and elimination are convenient, the debugging efficiency is improved, the verification accuracy is higher, and the verification effect is better.
In one embodiment of the invention, the apparatus further comprises:
the processing module is used for aiming at the second output result of each sub-model, and performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each first output result is predetermined based on the RTL description of the DUT;
The first verification module 503 is specifically configured to:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to the target detection point aiming at the first output result of each target detection point.
In one embodiment of the invention, the apparatus further comprises:
and the second verification module is used for verifying the correctness of the target data on a preset signal line and/or a preset cache position in the DUT through a preset assertion statement.
In one embodiment of the invention, the specific behavior occurrence points include any one or more of a cache point, a convergence point, a scheduling point, a back pressure point/deletion point, and a release point.
The embodiment of the invention also provides an electronic device, as shown in fig. 6, which comprises a processor 601, a communication interface 602, a memory 603 and a communication bus 604, wherein the processor 601, the communication interface 602 and the memory 603 complete communication with each other through the communication bus 604,
a memory 603 for storing a computer program;
the processor 601 is configured to execute the program stored in the memory 603, and implement the following steps:
inputting data to be tested into the DUT, and obtaining first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-detected sub-design in the DUT, and the to-be-detected sub-design is obtained by splitting the DUT according to specific behavior occurrence points of the data flow in the DUT based on RTL description of the DUT;
Inputting data to be tested into a reference model RM corresponding to the DUT, and obtaining a second output result of each sub-model contained in the RM; each sub-model corresponds to one sub-design to be tested;
and verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
The communication bus mentioned above for the electronic devices may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the electronic device and other devices.
The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
In yet another embodiment of the present invention, a computer readable storage medium is provided, in which a computer program is stored, which when executed by a processor, implements the steps of the verification method of any of the designs under test described above.
In yet another embodiment of the present invention, a computer program product containing instructions that, when run on a computer, cause the computer to perform the verification method of any of the designs under test of the above embodiments is also provided.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the verification apparatus of the design under test, the electronic device, or the readable storage medium embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant points are referred to in the description of the method embodiment.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A method of verifying a design under test, comprising:
inputting data to be tested into a design under test DUT (device under test), and obtaining first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-tested sub-design in the DUT, and the to-be-tested sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on a register conversion base level RTL description of the DUT;
inputting the data to be tested into a reference model RM corresponding to the DUT, and obtaining a second output result of each sub-model contained in the RM; each of the sub-models corresponds to one of the sub-designs under test;
and verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
2. The method according to claim 1, wherein said inputting the data to be tested into the reference model RM corresponding to the DUT, after obtaining the second output result of each sub-model included in the RM, further comprises:
Aiming at the second output result of each sub-model, performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each of the first output results is predetermined based on the RTL description of the DUT;
the verifying the first output result for each target detection point based on the second output result of the sub-model corresponding to the target detection point includes:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to the target detection point aiming at the first output result of each target detection point.
3. The method according to claim 1, wherein the method further comprises:
and verifying the correctness of the target data on a preset signal line and/or a preset cache position in the DUT through a preset assertion statement.
4. The method of claim 1, wherein the specific behavior occurrence point comprises any one or more of a cache point, a convergence point, a dispatch point, a backpressure point/deletion point, and a release point.
5. A verification apparatus for a design under test, comprising:
the first acquisition module is used for inputting data to be detected into the DUT and acquiring first output results of the DUT at a plurality of target detection points; each target detection point corresponds to one to-be-detected sub-design in the DUT, and the to-be-detected sub-design is obtained by splitting the DUT according to a specific behavior occurrence point of a data stream in the DUT based on RTL description of the DUT;
the second acquisition module is used for inputting the data to be detected into the RM corresponding to the DUT and acquiring a second output result of each sub-model contained in the RM; each of the sub-models corresponds to one of the sub-designs under test;
the first verification module is used for verifying the first output result of each target detection point based on the second output result of the sub-model corresponding to the target detection point.
6. The apparatus as recited in claim 5, further comprising:
the processing module is used for aiming at the second output result of each sub-model, and performing beat processing on the second output result based on the expected output time sequence of the first output result corresponding to the sub-model so as to align the output time sequence of the second output result with the expected output time sequence; the expected output timing of each of the first output results is predetermined based on the RTL description of the DUT;
The first verification module is specifically configured to:
and verifying the data correctness and the time correctness of the first output result based on the second output result after the beat processing of the sub-model corresponding to the target detection point aiming at the first output result of each target detection point.
7. The apparatus as recited in claim 5, further comprising:
and the second verification module is used for verifying target data on a preset signal line in the DUT and/or verifying data buffering time sequence and data releasing time sequence in the DUT through preset assertion statement.
8. The apparatus of claim 5, wherein the particular behavior occurrence point comprises any one or more of a cache point, a convergence point, a dispatch point, a backpressure point/delete point, and a release point.
9. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for carrying out the method steps of any one of claims 1-4 when executing a program stored on a memory.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-4.
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