WO2022138608A1 - 三相3レベルインバータの駆動制御装置および駆動制御方法 - Google Patents
三相3レベルインバータの駆動制御装置および駆動制御方法 Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
Definitions
- the present invention relates to a power conversion device that converts a DC voltage into a three-phase AC voltage, and particularly relates to a drive control device and a drive control method for a three-phase three-level inverter.
- a power conversion device that converts DC power into AC power is composed of a main circuit using a semiconductor switching element and a control device that controls the semiconductor switching element, and the semiconductor switching element is controlled at an arbitrary switching frequency.
- An arbitrary frequency and voltage are generated by pulse width modulation control (PWM control).
- AC motors In the field of railroad vehicles as well, AC motors (motors) are driven using power conversion devices (inverters) that use semiconductor switching elements, but because high withstand voltage elements are used, the switching frequency that can be achieved is There is an upper limit. Therefore, in general, depending on the drive frequency of the AC electric motor (motor), it is driven in the asynchronous PWM mode in which the drive frequency (inverter frequency) and the switching frequency are asynchronous in the low speed range, and in the high speed range, the drive frequency is reached. A method of switching to the synchronous PWM mode that synchronizes the (inverter frequency) and the switching frequency is adopted.
- the switching frequency is reduced by switching from the asynchronous PWM mode to the synchronous PWM mode as in the 2-level system, and the switching of the semiconductor switching element is performed.
- a means for reducing the loss can be considered. However, if the switching frequency is simply lowered, the switching ripple (current harmonic) increases, which leads to an increase in the loss (harmonic loss) of the driving AC motor.
- Patent Document 2 The technique described in Patent Document 2 is intended to reduce specific voltage harmonics and is not intended to reduce the entire current harmonics.
- Patent Document 3 belongs to so-called spatial vector modulation control (SVM control), and is expected to reduce unnecessary switching as compared with triangular wave PWM control having a constant carrier frequency.
- SVM control spatial vector modulation control
- the voltage harmonics can be reduced, but the current harmonics cannot always be reduced.
- Patent Document 4 The technique described in Patent Document 4 is intended to reduce current harmonics, but there is no disclosure of pulse patterns, and the details and effects of means for reducing current harmonics are unknown.
- Patent Document 5 aims to reduce the entire current harmonic (OVER ALL) with a small switching frequency. Therefore, one cycle of the modulated wave signal according to the output frequency of the three-phase three-level inverter is equally divided into 12 or 24 sections, and within each divided section, only one of the three phases switches, and the other. The two phases hold the output potential at zero, positive and constant, or negative and constant without switching. Only at the boundaries of the equally divided sections, each of the three phases performs the necessary switching to change the output potential of each equally divided section to either zero or positive and constant or negative and constant. It is something to do.
- the three-phase inverter that drives an AC motor does not always operate constantly at the same modulation factor, and in reality, various disturbances, such as mechanical disturbances that are applied to the load side of the AC motor, and Voltage disturbances applied to the DC voltage source of the inverter are applied.
- various disturbances such as mechanical disturbances that are applied to the load side of the AC motor, and Voltage disturbances applied to the DC voltage source of the inverter are applied.
- the current flowing through the AC motor constantly fluctuates, so it is necessary to finely manipulate the modulation factor to control the current so as to match the desired current value.
- a plurality of synchronous PWM modes are provided, and these synchronous PWM modes are switched and used according to the frequency and the modulation factor.
- Patent Document 5 since the number of section divisions in one cycle of the modulated wave signal is different between Example 1 (FIG. 1) and Example 2 (FIG. 3), it is possible to smoothly switch between these PWM modes. There is a problem that it is difficult.
- one of the typical drive control devices for the three-phase three-level power conversion device is one-fourth of the modulated wave signal per phase of the three-phase three-level inverter.
- the output potential of the three-phase three-level inverter is set to zero.
- switching is performed once, and the output potential is maintained at a constant positive potential for the remaining period after the switching.
- switching is performed once and the output potential is set to zero for the remaining period after the switching, or the output potential is maintained at a constant positive potential without the switching.
- switching is performed once and the output potential is kept at a constant positive potential for the remaining period after the switching, or the output potential is kept at a constant positive potential without the switching.
- switching is performed once and the output potential is set to zero for the remaining period after the switching, or the output potential is maintained at a constant positive potential without the switching.
- a waveform that is output by switching with a phase of 0 to 90 degrees and a waveform that is at least one of vertical symmetry and anteroposterior symmetry are output, and from the remaining two phases, the waveforms output by one phase are 120 degrees and 240 degrees, respectively.
- a symmetric waveform with a phase shift of degrees is output.
- the entire current harmonic (OVER ALL) can be reduced with a small number of switchings, the switching loss of the power converter (inverter) can be reduced, and at the same time, the motor can be driven. It is possible to reduce the loss (harmonic loss) of the existing AC motor. Further, the response of the current control can be improved with respect to the technique described in Patent Document 5. Further, since the first to fourth PWM modes of the present invention all have the same number of section divisions, the PWM mode can be smoothly switched. Issues, configurations and effects other than those mentioned above will be clarified by the description in the embodiments for carrying out the following.
- FIG. 3 is an enlarged view (a range of a phase of 50 to 130 degrees) of one enlarged portion shown in FIG.
- FIG. 4 is a diagram showing a case where the magnitude relationship between T23 and T9 is reversed with respect to FIG.
- FIG. 3 is an enlarged view (a range of a phase of 110 to 190 degrees) of two enlarged parts shown in FIG.
- FIG. 3 is an enlarged view (a range of a phase of 110 to 190 degrees) of two enlarged parts shown in FIG.
- FIG. 6 is a diagram showing a case where the magnitude relationship between T23 and T45 is reversed with respect to FIG. It is a figure which defines the U-phase voltage waveform of the synchronous 8 pulse (2) corresponding to the 2nd PWM mode in the Example of this invention. It is a figure which shows the switching overlap state between a phase in each section of a synchronous 8 pulse (2). It is a figure which shows the U phase and V phase voltage waveform, and the UV line voltage waveform of the synchronous 8 pulse (2). It is an enlarged view (range of phase 110-190 degrees) of the enlarged part shown in FIG. 11 is a diagram showing a case where the magnitude relationship between T3 and T4 is reversed with respect to FIG. 11.
- FIG. 21 is a diagram showing a case where the magnitude relationship between T23 and T89 is reversed with respect to FIG. 21. It is a figure which shows the current harmonic OVER ALL value of each of the 1st to 4th PWM modes with respect to a modulation factor. It is a figure which shows an example of the operation range of each of the 1st to 4th PWM modes. It is a figure which shows the configuration example of the drive system of the AC electric motor (motor) by the three-phase three-level inverter which concerns on embodiment of this invention.
- FIG. 25 is a diagram showing a configuration example of a drive system for an AC motor (motor) using a three-phase three-level inverter according to an embodiment of the present invention.
- the DC voltage supplied by the DC voltage source (not shown) is divided by two sets of smoothing capacitors 1 and 2, and the smoothing capacitors 1 and 2 have a U-phase inverter circuit 3, a V-phase inverter circuit 4, and a V-phase inverter circuit 4.
- the W-phase inverter circuit 5 is connected in parallel.
- the U-phase inverter circuit 3 is composed of four U-phase inverter switching elements 6 to 9 and U-phase clamp diodes 10 and 11, and the V-phase inverter circuit 4 is composed of four V-phase inverter switching elements 12 to 15 and V-phase. It is composed of clamp diodes 16 and 17, and the W-phase inverter circuit 5 is composed of four W-phase inverter switching elements 18 to 21 and clamp diodes 22 and 23.
- the inverter control device 24 outputs gate pulse signals GPUs 1 to 4, GPVs 1 to 4, and GPWs 1 to 4 that drive the inverter switching elements of the U-phase to W-phase inverter circuits 3 to 5.
- the AC motor 25 is connected to the AC output terminal side of the U-phase to W-phase inverter circuits 3 to 5.
- the DC voltage supplied by the DC voltage source is divided by two sets of smoothing capacitors 1 and 2.
- the respective capacitor voltages are Edp and Edn and the neutral point potential is zero
- the output potentials Eu, Ev and Ew of the U-phase to W-phase inverter circuits 3 to 5 are positive potential Edp and negative potential (-Edn).
- the neutral point potential of zero can be taken in three kinds of values.
- the phase voltage of the inverter shall take three values, ⁇ 1 and 0.
- FIG. 1 is a diagram showing a U-phase voltage waveform of synchronous 8 pulses (1) corresponding to the first PWM mode in the embodiment of the present invention, and a U-phase voltage waveform of one cycle in the upper half thereof. Is. For simplicity, the output potential of the U-phase voltage is shown normalized to three levels of ⁇ 1 and 0. In the following, the first PWM mode will be described as synchronous 8 pulse (1).
- the 1/4 period (0 to 90 degrees) of the modulated wave signal according to the output frequency is equally divided into 9 sections, and the 1st to 9th sections are sequentially divided from the phase 0 degree side.
- the output potential is set to zero.
- the phase ⁇ (10 ⁇ ⁇ 30) in the second and third sections the output potential is raised from zero to a positive potential.
- T23 30- ⁇ .
- the phase ⁇ (30 ⁇ ⁇ 50) in the 4th and 5th sections the output potential is lowered from the positive potential to zero.
- the remaining 3/4 period (90 to 360 degrees) is vertically or anteroposteriorly symmetric with the 1/4 period waveform.
- the U-phase voltage waveform is SU ( ⁇ )
- SU ( ⁇ ) in the range of 0 ⁇ ⁇ ⁇ 90 is defined as described above.
- SU ( ⁇ ) SU (180- ⁇ )
- In 180 ⁇ ⁇ ⁇ 270, SU ( ⁇ ) ⁇ SU ( ⁇ -180)
- In 270 ⁇ ⁇ ⁇ 360, SU ( ⁇ ) ⁇ SU (360- ⁇ ) Is defined as.
- U-phase voltage waveform SU ( ⁇ ) is a periodic function with a period of 360 degrees.
- SU ( ⁇ ) SU ( ⁇ ⁇ 180) Is.
- the lower half of FIG. 1 shows the relationship between the four switching phases ⁇ , ⁇ , ⁇ and ⁇ (vertical axis) of the U-phase voltage waveform and the modulation factor (horizontal axis).
- the modulation factor horizontal axis
- the first switching phase ⁇ is within the second and third sections
- the second switching phase ⁇ is within the fifth section
- the third switching phase ⁇ is within the sixth section
- the fourth switching phase ⁇ is. , It is in the 9th section.
- FIG. 2 is a diagram showing a switching overlapping state between phases in each section within one cycle of the synchronous 8 pulse (1).
- the output potentials of the U-phase and V-phase voltages are shown normalized to 3 levels ⁇ 1 and 0, and the UV line voltage is shown normalized to 5 levels ⁇ 2, ⁇ 1 and 0, respectively.
- the case where both the U-phase and V-phase voltage waveforms change in the divided section and the pulse rises and then falls or falls and then rises in the section is shown by an intersection pattern. ..
- the output potential of the UV line voltage changes from +1 to +2 to +1 depending on the order of change of the U phase and V phase voltage waveforms.
- FIG. 3 is a diagram showing U-phase and V-phase voltage waveforms and UV line voltage waveforms of synchronous 8 pulses (1).
- the cross pattern (90 to 100 degrees) is shown due to the symmetry of the waveform. ) Is the center, and the range of the phase of 50 to 130 degrees shown in FIG. 3 is defined as “enlarged 1”, and the enlarged view thereof is shown in FIG.
- the range of the phase 110 to 190 degrees shown in FIG. 3 is defined as “enlargement 2” centering on the intersection pattern (130 to 170 degrees), and the enlarged view thereof is shown in FIG.
- the line voltage of a three-level inverter takes five levels of ⁇ 2, ⁇ 1, and 0, and can be classified into four states in which two adjacent levels come and go. ⁇ +2, +1> Traffic between +2, +1 ⁇ +1, 0> Traffic between +1 and 0 ⁇ -1, 0> Traffic between -1 and 0 ⁇ -2, -1> -2, -1
- These four states are monotonically decreased as ⁇ +2, +1> ⁇ ⁇ +1, 0> ⁇ ⁇ 0, -1> ⁇ ⁇ -1, -2>, or conversely, ⁇ -2.
- -1> ⁇ ⁇ -1, 0> ⁇ ⁇ 0, +1> ⁇ ⁇ +1, +2> monotonically increasing is called "normal order" here.
- this state changes in "normal order"
- the change in the output potential becomes gradual and the output voltage harmonic becomes smaller.
- FIG. 7 is a diagram showing a case where the magnitude relationship between T23 and T45 is reversed (T23> T45) in the range of a phase of 110 to 190 degrees with respect to FIG.
- the state of the UV line voltage changes in the order of ⁇ +1, 0> ⁇ ⁇ 0, -1> ⁇ ⁇ 0, +1> ⁇ ⁇ 0, -1>, and is in the “normal order” defined above. You can see that it is not. If there is such a section that does not become “normal order", it becomes a factor that the voltage harmonics increase. From the above, it can be seen that the condition for “normal order” and the reduction of voltage harmonics is T23 ⁇ T45.
- FIG. 5 shows a case where the magnitude relationship between T23 and T9 is reversed in the range of a phase of 50 to 130 degrees with respect to FIG. Specifically, FIG. 5 shows the case of T23 + T9 ⁇ 10 (degrees), whereas T23 + T9> 10 (degrees) in FIG. Also in FIG. 5, the state of the UV line voltage changes from ⁇ +2, +1> to ⁇ +1, 0>, and it can be seen that this is also in the “normal order” defined above. That is, in the range of the phase of 50 to 130 degrees, the magnitude relationship between T23 and T9 is not restricted.
- the synchronous 8 pulse (1) has a modulation factor of 50% to a little over 90%, which is a domain.
- the first switching phase ⁇ is within the second and third sections, the second switching phase ⁇ is within the fifth section, the third switching phase ⁇ is within the sixth section, and the fourth switching phase ⁇ is. , It is in the 9th section.
- the period T23 in which the positive potential is taken in the second and third sections is smaller than the period T45 in which the positive potential is taken in the fourth and fifth sections (T23 ⁇ T45).
- the switching phases are arranged so that the switching does not overlap between the phases as much as possible within the divided section, and even if the switching overlaps, the “normal order” relationship is maintained.
- the voltage harmonics By reducing the voltage harmonics, the current harmonics are reduced with as few switching times as possible. Further, since the synchronous 8 pulse (1) does not fix the switching phase, the response of the current control is also enhanced.
- FIG. 8 is a diagram showing a U-phase voltage waveform of synchronous 8 pulses (2) corresponding to the second PWM mode in the embodiment of the present invention, and showing a U-phase voltage waveform of one cycle in the upper half thereof. Is. For simplicity, the output potential of the U-phase voltage is shown normalized to 3 levels of ⁇ 1 and 0. In the following, the second PWM mode will be described as synchronous 8 pulse (2).
- the 1/4 period (0 to 90 degrees) of the modulated wave signal according to the output frequency is equally divided into 9 sections, and the 1st to 9th sections are sequentially divided from the phase 0 degree side.
- the output potential is set to zero.
- the phase ⁇ (20 ⁇ ⁇ 30) in the third section the output potential is raised from zero to a positive potential.
- T3 30- ⁇ .
- -At the phase ⁇ (30 ⁇ ⁇ 40) in the fourth section the output potential is lowered from the positive potential to zero.
- the remaining 3/4 period (90 to 360 degrees) is vertically or anteroposteriorly symmetric with the 1/4 period waveform.
- the U-phase voltage waveform is SU ( ⁇ )
- SU ( ⁇ ) in the range of 0 ⁇ ⁇ ⁇ 90 is defined as described above.
- SU ( ⁇ ) SU (180- ⁇ )
- In 180 ⁇ ⁇ ⁇ 270, SU ( ⁇ ) ⁇ SU ( ⁇ -180)
- In 270 ⁇ ⁇ ⁇ 360, SU ( ⁇ ) ⁇ SU (360- ⁇ ) Is defined as.
- U-phase voltage waveform SU ( ⁇ ) is a periodic function with a period of 360 degrees.
- SU ( ⁇ ) SU ( ⁇ ⁇ 180) Is.
- the lower half of FIG. 8 shows the relationship between the switching phases ⁇ , ⁇ , ⁇ and ⁇ of the U-phase voltage waveform and the modulation factor.
- modulation factor 0% to less than 50%, which is the domain of synchronous 8 pulses (2).
- the first switching phase ⁇ is within the third section
- the second switching phase ⁇ is within the fourth section
- the third switching phase ⁇ is within the seventh section
- the fourth switching phase ⁇ is the eighth. It is in the section.
- FIG. 9 is a diagram showing a switching overlapping state between phases in each section of the synchronous 8 pulse (2).
- the output potentials of the U-phase and V-phase voltages are shown normalized to 3 levels ⁇ 1 and 0, and the UV line voltage is shown normalized to 5 levels ⁇ 2, ⁇ 1 and 0, respectively.
- the case where both the U-phase and V-phase voltage waveforms change in the divided section and the pulse rises and then falls or falls and then rises in the section is shown by an intersection pattern in FIG.
- the output potential of the UV line voltage changes from 0 to +1 to 0 or 0 depending on the order of change of the U phase and V phase voltage waveforms.
- FIG. 10 is a diagram showing U-phase and V-phase voltage waveforms and UV line voltage waveforms of synchronous 8 pulses (2).
- the section where the switching of the U-phase and V-phase voltage waveforms overlap in the divided section is shown by the cross pattern, but the cross pattern (140 to 160 degrees) is shown due to the symmetry of the waveform.
- FIG. 11 shows an enlarged view of the phase of 110 to 190 degrees centered on the above.
- FIG. 12 is a diagram showing a case where the magnitude relationship between T3 and T4 is reversed with respect to FIG.
- the state of the UV line voltage changes in the order of ⁇ +1, 0> ⁇ ⁇ -1, 0> ⁇ ⁇ +1, 0> ⁇ ⁇ -1, 0>, and is not in the “normal order” defined above. I understand. If there is such a section that does not become “normal order”, it becomes a factor that the voltage harmonics increase. From the above, it can be seen that the condition for “normal order” and the reduction of voltage harmonics is T3 ⁇ T4.
- the synchronous 8 pulse (2) has a modulation factor of 0% to a little less than 50%, which is the domain.
- the first switching phase ⁇ is within the third section
- the second switching phase ⁇ is within the fourth section
- the third switching phase ⁇ is within the seventh section
- the fourth switching phase ⁇ is the eighth. It is in the section.
- the period T3 in which the positive potential is taken in the third section is smaller than the period T4 in which the positive potential is taken in the fourth section (T3 ⁇ T4).
- the switching phases are arranged so that the switching does not overlap between the phases as much as possible within the divided section, and even if the switching overlaps, the “normal order” relationship is maintained.
- the voltage harmonics By reducing the voltage harmonics, the current harmonics are reduced with as few switching times as possible. Further, since the synchronous 8 pulse (2) does not fix the switching phase, the response of the current control is also enhanced.
- FIG. 13 is a diagram showing a U-phase voltage waveform of 6 synchronous pulses corresponding to the third PWM mode in the embodiment of the present invention, and a U-phase voltage waveform of one cycle in the upper half thereof.
- the output potential of the U-phase voltage is shown normalized to three levels of ⁇ 1 and 0.
- the third PWM mode will be described as synchronous 6 pulses.
- the 1/4 period (0 to 90 degrees) of the modulated wave signal corresponding to the output frequency is equally divided into 9 sections, which are called the 1st to 9th sections in order from the phase 0 degree side.
- the output potential is set to zero.
- the phase ⁇ (10 ⁇ ⁇ 30) in the second and third sections the output potential is raised from zero to a positive potential.
- T23 30- ⁇ .
- the output potential is lowered from the positive potential to zero.
- T45 ⁇ -30.
- T6 60- ⁇ .
- T6 60- ⁇ .
- the output potential is fixed to the positive potential.
- the remaining 3/4 period (90 to 360 degrees) is vertically or anteroposteriorly symmetric with the 1/4 period waveform.
- SU ( ⁇ ) is defined in the range of 0 ⁇ ⁇ ⁇ 90 as described above.
- SU ( ⁇ ) SU (180- ⁇ )
- 180 ⁇ ⁇ ⁇ 270, SU ( ⁇ ) ⁇ SU ( ⁇ -180)
- 270 ⁇ ⁇ ⁇ 360, SU ( ⁇ ) ⁇ SU (360- ⁇ ) Is defined as.
- U-phase voltage waveform SU ( ⁇ ) is a periodic function with a period of 360 degrees.
- SU ( ⁇ ) SU ( ⁇ ⁇ 180) Is.
- the lower half of FIG. 13 shows the relationship between the switching phases ⁇ , ⁇ and ⁇ of the U-phase voltage waveform and the modulation factor.
- the first switching phase ⁇ is in the second and third sections
- the second switching phase ⁇ is in the fourth and fifth sections
- the third switching phase ⁇ is in the sixth section.
- FIG. 14 is a diagram showing a switching overlapping state between phases in each section of synchronous 6 pulses.
- the output potentials of the U-phase and V-phase voltages are shown normalized to 3 levels of ⁇ 1 and 0, and the UV line voltage is shown normalized to 5 levels of ⁇ 2, ⁇ 1 and 0.
- the case where the output potential is raised from zero to positive potential or from negative potential to zero in the divided section is shown by a diagonal line pattern rising to the right.
- the case where the output potential is lowered from the positive potential to zero or from zero to the negative potential in the divided section is shown by a diagonal line pattern downward to the right.
- the case where both the U-phase and V-phase voltage waveforms change in the divided section and the pulse rises and then falls or falls and then rises in the section is shown by an intersection pattern.
- the output potential of the UV line voltage changes from 0 to +1 to 0 or 0 depending on the order of change of the U phase and V phase voltage waveforms.
- FIG. 15 shows U-phase and V-phase voltage waveforms of synchronous 6 pulses and UV line voltage waveforms.
- the section where the switching of the U-phase and V-phase voltage waveforms overlap in the divided section is shown by the cross pattern, but the cross pattern (130 to 170 degrees) is shown due to the symmetry of the waveform. ) Is shown in FIG. 16 with an enlarged view of the phase of 110 to 190 degrees.
- FIG. 17 is a diagram showing a case where the magnitude relationship between T23 and T45 is reversed with respect to FIG.
- the state of the UV line voltage changes in the order of ⁇ +1, 0> ⁇ ⁇ -1, 0> ⁇ ⁇ +1, 0> ⁇ ⁇ -1, 0>, and is not in the “normal order” defined above. I understand. If there is such a section that does not become “normal order”, it becomes a factor that the voltage harmonics increase. From the above, it can be seen that the condition for “normal order” and the reduction of voltage harmonics is T23 ⁇ T45.
- the synchronous 6 pulse is in the range of the modulation factor of 50% to more than 90%, which is the domain.
- the first switching phase ⁇ is in the second and third sections
- the second switching phase ⁇ is in the fourth and fifth sections
- the third switching phase ⁇ is in the sixth section.
- the period T23 in which the positive potential is taken in the second and third sections is smaller than the period T45 in which the positive potential is taken in the fourth and fifth sections (T23 ⁇ T45).
- the synchronous 6 pulses arrange the switching phases so that the switching does not overlap between the phases as much as possible in the divided section, and even if they overlap, the voltage harmonics maintain the "normal order" relationship.
- the current harmonics are reduced with as few switching times as possible. Further, since the synchronous 6 pulse does not fix the switching phase, the response of the current control is also enhanced.
- FIG. 18 is a diagram showing a U-phase voltage waveform of four synchronous pulses corresponding to the fourth PWM mode in the embodiment of the present invention, and a U-phase voltage waveform of one cycle in the upper half thereof.
- the output potential of the U-phase voltage is shown normalized to 3 levels of ⁇ 1 and 0.
- the fourth PWM mode will be described as synchronous 4 pulses.
- the 1/4 period (0 to 90 degrees) of the modulated wave signal corresponding to the output frequency is equally divided into 9 sections, which are called the 1st to 9th sections in order from the phase 0 degree side.
- the output potential is set to zero.
- T23 30- ⁇ .
- the output potential is fixed to the positive potential.
- the remaining 3/4 period (90 to 360 degrees) is vertically or anteroposteriorly symmetric with the 1/4 period waveform.
- SU ( ⁇ ) is defined in the range of 0 ⁇ ⁇ ⁇ 90 from the above.
- SU ( ⁇ ) SU (180- ⁇ )
- 180 ⁇ ⁇ ⁇ 270, SU ( ⁇ ) ⁇ SU ( ⁇ -180)
- 270 ⁇ ⁇ ⁇ 360, SU ( ⁇ ) ⁇ SU (360- ⁇ ) Is defined as.
- U-phase voltage waveform SU ( ⁇ ) is a periodic function with a period of 360 degrees.
- SU ( ⁇ ) SU ( ⁇ ⁇ 180) Is.
- the lower half of FIG. 18 shows the relationship between the switching phases ⁇ and ⁇ of the U-phase voltage waveform and the modulation factor.
- the first switching phase ⁇ is in the second and third sections, and the second switching phase ⁇ is in the eighth and ninth sections.
- FIG. 19 is a diagram showing a switching overlapping state between phases in each section of synchronous 4 pulses.
- the output potentials of the U-phase and V-phase voltages are shown normalized to 3 levels of ⁇ 1 and 0, and the UV line voltage is shown normalized to 5 levels of ⁇ 2, ⁇ 1 and 0.
- the case where both the U-phase and V-phase voltage waveforms change in the divided section and the pulse rises and then falls or falls and then rises in the section is shown by an intersection pattern.
- the output potential of the UV line voltage changes from +1 ⁇ +2 ⁇ +1 or +1 depending on the order of change of the U phase and V phase voltage waveforms.
- FIG. 20 shows U-phase and V-phase voltage waveforms of four synchronous pulses and UV line voltage waveforms.
- FIG. 19 in the UV line voltage waveform, the section where the switching of the U-phase and V-phase voltage waveforms overlap in the divided section is shown by the cross pattern, and the cross pattern (90 to 110 degrees) is shown from the symmetry of the waveform.
- FIG. 21 shows an enlarged view of the phase of 60 to 140 degrees with the center.
- the state of the UV line voltage has a monotonous transition from ⁇ +2, +1> to ⁇ +1, 0>, and is in the "normal order" defined above.
- FIG. 22 is a diagram showing a case where the magnitude relationship between T23 and T89 is reversed with respect to FIG. 21.
- FIG. 21 is the case of T23> 20-T89, that is, T23 + T89> 20 (degrees)
- FIG. 22 is the case of T23 + T89 ⁇ 20 (degrees).
- the state of the UV line voltage changes monotonously as ⁇ +2, +1> ⁇ ⁇ +1, 0>, and is in the “normal order” defined above. That is, the state transition of the UV line voltage is not restricted by the magnitude relationship between T23 and T89.
- the synchronous 4 pulse is in the range of the modulation factor of 60% to 90%, which is the domain.
- the first switching phase ⁇ is in the second and third sections, and the second switching phase ⁇ is in the eighth and ninth sections.
- the synchronous 4 pulses arrange the switching phases so that the switching does not overlap between the phases as much as possible in the divided section, and even if they overlap, the voltage harmonics maintain the "normal order" relationship.
- the current harmonics are reduced with as few switching times as possible. Further, since the synchronous 4 pulse does not fix the switching phase, the response of the current control is also enhanced.
- FIG. 23 is a diagram showing the current harmonic OVER ALL values of the first to fourth PWM modes with respect to the modulation factor. Further, for comparison, among the techniques described in Patent Document 5, the value of synchronous 8 pulses is shown as a conventional technique.
- the current harmonics are increased by the smaller number of pulses as compared with the synchronous 8 pulse (1). ..
- FIG. 24 is a diagram showing an example of the operating range of each of the first to fourth PWM modes.
- the line shown as a "steady operating point" in FIG. 24 indicates a steady operating point from the stopped state to the maximum speed, or from the maximum speed to the decelerated state to the stopped state.
- the horizontal axis (output frequency axis) is normalized with the value at which the line of the steady operating point reaches the maximum value as 100%.
- the inverter moves slowly on the line of the steady operating point, but when the operation of the inverter is stopped when the speed is high, such as in the so-called coasting state, or conversely, the inverter is restarted during coasting.
- a non-steady state such as in the case of an inverter
- the region between the output frequency axis (modulation rate zero) is traversed in a short time from below the line of the steady operating point.
- the state does not reach above the steady operating point line.
- each PWM mode is shown by a rectangle with rounded corners.
- each PWM mode is arranged as shown in the figure according to the modulation factor on the vertical axis and the output frequency on the horizontal axis.
- there is a gap between the regions of each PWM mode so that the regions of each PWM mode can be easily distinguished, but in reality, the regions are lined up without gaps including the corners of the regions, and the PWM mode There is no undefined area.
- synchronous 8 pulses which are the four PWM modes according to the present invention, including the asynchronous dipolar and the asynchronous unipolar, depending on at least one of the modulation factor and the output frequency command.
- synchronous 8 pulse (2), synchronous 6 pulse and synchronous 4 pulse will be switched and used.
- the asynchronous dipolar, the asynchronous unipolar, the synchronous 8 pulse (1), the synchronous 6 pulse, and the synchronous 4 pulse are arranged in order from the origin (A).
- the synchronous 8 pulse (2) is arranged in the region where the modulation factor is lower than that of the synchronous 8 pulse (1).
- each PWM mode is arranged in this way is that it is necessary to arrange the most efficient PWM mode because the current value is large and the operation time is long because the normal rated operation is performed on the line of the steady operating point. be.
- a synchronous 8 pulse (2) is placed below the synchronous 8 pulse (1) (a region where the modulation factor is low) instead of an asynchronous unipolar. ing.
- the synchronous 8 pulse (1) corresponding to the first PWM mode the synchronous 8 pulse (2) corresponding to the second PWM mode, the synchronous 6 pulse corresponding to the third PWM mode of the present invention, and the third. Since each of the four synchronous pulses corresponding to the PWM mode of 4 has a common number of section divisions, the PWM mode can be smoothly switched in a short time.
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Abstract
Description
第1の区間で、三相3レベルインバータの出力電位をゼロとし、
第2と第3の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は出力電位を一定の正電位に保持し、
第4と第5の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は出力電位をゼロとするか、または当該スイッチングなしに出力電位を一定の正電位に保持することを継続し、
第6と第7の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は出力電位を一定の正電位に保持するか、または当該スイッチングなしに出力電位を一定の正電位に保持することを継続し、
第8と第9の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は出力電位をゼロとするか、または当該スイッチングなしに出力電位を一定の正電位に保持することを継続することで、
第1~第9までの区間でスイッチングを二回から四回のいずれかの回数のスイッチングを行い、変調波信号の残りの3/4周期である位相90~360度では、各1/4周期毎に位相0~90度で行うスイッチングにより出力される波形と上下対称および前後対称の少なくともいずれかとなる波形が出力され、残る二相からは、一相が出力する波形とはそれぞれ120度および240度の位相のずれた対称波形が出力されるものである。
上記した以外の課題、構成および効果は、以下の実施をするための形態における説明により明らかにされる。
図25において、直流電圧源(図示せず)が供給する直流電圧を二組の平滑コンデンサ1および2で分圧し、平滑コンデンサ1および2には、U相インバータ回路3、V相インバータ回路4およびW相インバータ回路5が並列接続される。
交流電動機(モータ)25は、U相~W相インバータ回路3~5の交流出力端子側に接続される。
ここで、中性点電圧制御が適切に行われているものと仮定して、平滑コンデンサ1および2の電圧は等しい(Edp=Edn)とする。以下での説明を簡単にするために、インバータの相電圧は、±1および0の3種類の値を取るものとする。
<第1のPWMモード>
図1は、本発明の実施例の内で、第1のPWMモードに相当する同期8パルス(1)のU相電圧波形を定義し、その上半分に1周期のU相電圧波形を示す図である。簡単化のために、U相電圧の出力電位は、±1および0の3レベルに正規化して示している。なお、以下では、第1のPWMモードについては、同期8パルス(1)として記載する。
・第1区間では、出力電位をゼロとする。
・第2・第3区間内の位相α(10<α<30)で、出力電位をゼロから正電位に立ち上げる。第2・第3区間内で出力が正電位を取る期間を“T23”とすると、T23=30-αとなる。
・第4・第5区間内の位相β(30<β<50)で、出力電位を正電位からゼロに立ち下げる。第4・第5区間内で出力が正電位を取る期間を“T45”とすると、T45=β-30となる。
・第6区間内の位相γ(50<γ<60)で、出力電位をゼロから正電位に立ち上げる。第6区間内で出力が正電位を取る期間を“T6”とすると、T6=60-γとなる。
・第7・第8区間では、出力電位を正電位に固定する。
・第9区間内の位相δ(80<δ<90)で、出力電位を正電位からゼロに立ち下げる。第9区間内で出力が正電位を取る期間を“T9”とすると、T9=δ-80となる。
90≦θ≦180において、SU(θ)= SU(180-θ)
180≦θ≦270において、SU(θ)=-SU(θ-180)
270≦θ≦360において、SU(θ)=-SU(360-θ)
と定義される。
SU(θ)=SU(θ±180)
である。
SV(θ)=SU(θ-120)
SW(θ)=SU(θ-240)
と定義される。
第1のPWMモードの定義域である変調率50%から90%強の範囲において、
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第5区間内
・第3のスイッチング位相γは、第6区間内
・第4のスイッチング位相δは、第9区間内
に入っている。
<+2、+1> +2、+1の間を往来
<+1、 0> +1、 0の間を往来
<-1、 0> -1、 0の間を往来
<-2、-1> -2、-1の間を往来
これら4つの状態を、<+2、+1>→<+1、0>→<0、-1>→<-1、-2>のように単調減少する、あるいは逆に、<-2、-1>→<-1、0>→<0、+1>→<+1、+2>のように単調増加することを、ここでは“正順”と呼ぶ。この状態が“正順”で推移する場合には、出力電位の変化が緩やかになり、出力電圧高調波は小さくなる。
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第5区間内
・第3のスイッチング位相γは、第6区間内
・第4のスイッチング位相δは、第9区間内
に入っている。
図8は、本発明の実施例の内で、第2のPWMモードに相当する同期8パルス(2)のU相電圧波形を定義し、その上半分に1周期のU相電圧波形を示す図である。簡単化のために、U相電圧の出力電位は±1および0の3レベルに正規化して示している。なお、以下では、第2のPWMモードについては、同期8パルス(2)として記載する。
・第1・第2区間では、出力電位をゼロとする。
・第3区間内の位相α(20<α<30)で、出力電位をゼロから正電位に立ち上げる。
第3区間内で出力が正電位を取る期間を“T3”とすると、T3=30-αとなる。
・第4区間内の位相β(30<β<40)で、出力電位を正電位からゼロに立ち下げる。第4区間内で出力が正電位を取る期間を“T4”とすると、T4=β-30となる。
・第5・第6区間では、出力電位をゼロに固定する。
・第7区間内の位相γ(60<γ<70)で、出力電位をゼロから正電位に立ち上げる。第7区間内で出力が正電位を取る期間を“T7”とすると、T7=70-γとなる。
・第8区間内の位相δ(70<δ<80)で、出力電位を正電位からゼロに立ち下げる。第8区間内で出力が正電位を取る期間を“T8”とすると、T8=δ-70となる。
・第9区間では、出力電位をゼロとする。
90≦θ≦180において、SU(θ)= SU(180-θ)
180≦θ≦270において、SU(θ)=-SU(θ-180)
270≦θ≦360において、SU(θ)=-SU(360-θ)
と定義される。
SU(θ)=SU(θ±180)
である。
SV(θ)=SU(θ-120)
SW(θ)=SU(θ-240)
と定義される。
同期8パルス(2)の定義域である変調率0%から50%弱の範囲において、
・第1のスイッチング位相αは、第3区間内
・第2のスイッチング位相βは、第4区間内
・第3のスイッチング位相γは、第7区間内
・第4のスイッチング位相δは、第8区間内
に入っている。
・第1のスイッチング位相αは、第3区間内
・第2のスイッチング位相βは、第4区間内
・第3のスイッチング位相γは、第7区間内
・第4のスイッチング位相δは、第8区間内
に入っている。
図13は、本発明の実施例の内で、第3のPWMモードに相当する同期6パルスのU相電圧波形を定義し、その上半分に1周期のU相電圧波形を示す図である。簡単化のために、U相電圧の出力電位は、±1および0の3レベルに正規化して示している。なお、以下では、第3のPWMモードについては、同期6パルスとして記載する。
・第1区間では、出力電位をゼロとする。
・第2・第3区間内の位相α(10<α<30)で、出力電位をゼロから正電位に立ち上げる。第2・第3区間内で出力が正電位を取る期間を“T23”とすると、T23=30-αとなる。
・第4・第5区間内の位相β(30<β<50)で、出力電位を正電位からゼロに立ち下げる。第4・第5区間内で出力が正電位を取る期間を“T45”とする。T45=β-30となる。
・第6区間内の位相γ(50<γ<60)で、出力電位をゼロから正電位に立ち上げる。第6区間内で出力が正電位を取る期間を“T6”とすると、T6=60-γとなる。
・第7~第9区間では、出力電位を正電位に固定する。
90≦θ≦180において、SU(θ)= SU(180-θ)
180≦θ≦270において、SU(θ)=-SU(θ-180)
270≦θ≦360において、SU(θ)=-SU(360-θ)
と定義される。
SU(θ)=SU(θ±180)
である。
SV(θ)=SU(θ-120)
SW(θ)=SU(θ-240)
と定義される。
同期6パルスの定義域である変調率50%から90%強の範囲において、
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第4・第5区間内
・第3のスイッチング位相γは、第6区間内
に入っている。
U相電圧波形およびV相電圧波形において、分割された区間内に出力電位をゼロから正電位、あるいは負電位からゼロに立ち上げる場合を、右上がりの斜線パターンで示す。また、分割された区間内で出力電位を正電位からゼロ、あるいはゼロから負電位に立ち下げる場合を、右下がりの斜線パターンで示す。
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第4・第5区間内
・第3のスイッチング位相γは、第6区間内
に入っている。
図18は、本発明の実施例の内で、第4のPWMモードに相当する同期4パルスのU相電圧波形を定義し、その上半分に1周期のU相電圧波形を示す図である。簡単化のために、U相電圧の出力電位は±1および0の3レベルに正規化して示している。なお、以下では、第4のPWMモードについては、同期4パルスとして記載する。
・第1区間では、出力電位をゼロとする。
・第2・第3区間内の位相α(10<α<30)で、出力電位をゼロから正電位に立ち上げる。第2・第3区間内で出力が正電位を取る期間を“T23”とすると、T23=30-αとなる。
・第4~第7区間では、出力電位を正電位に固定する。
・第8・第9区間内の位相β(70<β<90)で、出力電位を正電位からゼロに立ち下げる。第8・第9区間内で出力が正電位を取る期間を“T89”とすると、T89=β-70となる。
90≦θ≦180において、SU(θ)= SU(180-θ)
180≦θ≦270において、SU(θ)=-SU(θ-180)
270≦θ≦360において、SU(θ)=-SU(360-θ)
と定義される。
SU(θ)=SU(θ±180)
である。
SV(θ)=SU(θ-120)
SW(θ)=SU(θ-240)
と定義される。
第4のPWMモードの定義域である変調率60%強から90%強の範囲において、
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第8・第9区間内
に入っている。
・第1のスイッチング位相αは、第2・第3区間内
・第2のスイッチング位相βは、第8・第9区間内
に入っている。
図24で「定常動作点」として示す線は、停止状態から最高速度まで加速、あるいは最高速度から減速して停止状態に至るまでの定常的な動作点を示す。横軸(出力周波数軸)は、定常動作点の線が最大値に至る値を100%として正規化している。
一方で、状態が定常動作点の線より上側に至ることは無い。
2 N側平滑コンデンサ
3 U相インバータ回路
4 V相インバータ回路
5 W相インバータ回路
6~ 9 U相インバータスイッチング素子
10、11 U相クランプダイオード
12~15 V相インバータスイッチング素子
16、17 V相クランプダイオード
18~21 W相インバータスイッチング素子
22、23 W相クランプダイオード
24 インバータ制御装置
25 モータ
Edp P側平滑コンデンサ電圧
Edn N側平滑コンデンサ電圧
Eu U相インバータ電圧
Ev V相インバータ電圧
Ew W相インバータ電圧
GPU1~4 U相インバータゲートパルス
GPV1~4 V相インバータゲートパルス
GPW1~4 W相インバータゲートパルス
α 第1~4のPWMモードにおける第1のスイッチング位相
β 第1~4のPWMモードにおける第2のスイッチング位相
γ 第1~3のPWMモードにおける第3のスイッチング位相
δ 第1~2のPWMモードにおける第4のスイッチング位相
T2 第2の分割区間において正電位を取る期間
T3 第3の分割区間において正電位を取る期間
T4 第4の分割区間において正電位を取る期間
T5 第5の分割区間において正電位を取る期間
T6 第6の分割区間において正電位を取る期間
T7 第7の分割区間において正電位を取る期間
T8 第8の分割区間において正電位を取る期間
T9 第9の分割区間において正電位を取る期間
T23 T2とT3の和、T23=T2+T3
T45 T4とT5の和、T45=T4+T5
T89 T8とT9の和、T89=T8+T9
Claims (16)
- 三相3レベルインバータの一相につき変調波信号の1/4周期である位相0~90度を順に等分割した第1~第9の9区間について、
第1の区間で、前記三相3レベルインバータの出力電位をゼロとし、
第2と第3の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位を一定の正電位に保持し、
第4と第5の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位をゼロとするか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続し、
第6と第7の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位を前記一定の正電位に保持するか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続し、
第8と第9の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位をゼロとするか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続することで、
前記第1~前記第9までの区間で二回から四回のいずれかの回数のスイッチングを行い、
前記変調波信号の残りの3/4周期である前記位相90~360度では、各1/4周期毎に前記位相0~90度で行うスイッチングにより出力される波形と上下対称および前後対称の少なくともいずれかとなる波形が出力され、
残る二相からは、前記一相が出力する波形とはそれぞれ120度および240度の位相のずれた対称波形が出力される
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項1に記載の三相3レベルインバータの駆動制御装置であって、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれでスイッチングを一回行い、
前記第6の区間内でスイッチングを一回行い、
前記第9の区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で四回のスイッチングを行い、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれで行うスイッチングのタイミングを調整して、前記第2と前記第3の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間が、前記第4と前記第5の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間よりも短い
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項1に記載の三相3レベルインバータの駆動制御装置であって、
前記第3および前記第4の区間内それぞれでスイッチングを一回行い、
前記第7および前記第8の区間内それぞれでスイッチングを一回行うことで、
前記第1~前記第9までの区間で四回のスイッチングを行い、
前記第3の区間内および前記第4の区間内それぞれで行うスイッチングのタイミングを調整して、前記第3の区間内で前記出力電位を前記一定の正電位に保持する時間が、前記第4の区間内で前記出力電位を前記一定の正電位に保持する時間よりも短い
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項1に記載の三相3レベルインバータの駆動制御装置であって、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれでスイッチングを一回行い、
前記第6の区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で三回のスイッチングを行い、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれで行うスイッチングのタイミングを調整して、前記第2と前記第3の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間が、前記第4と前記第5の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間よりも短い
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項1に記載の三相3レベルインバータの駆動制御装置であって、
前記第2と前記第3の区間を併せた区間内でスイッチングを一回行い、
前記第8と前記第9の区間を併せた区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で二回のスイッチングを行う
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項2~5のいずれか1項に記載の三相3レベルインバータの駆動制御装置による駆動制御が、変調率および出力周波数指令の少なくともいずれかに応じて切り替わって実行される
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 請求項2~5のいずれか1項に記載の三相3レベルインバータの駆動制御装置による駆動制御が、前記三相3レベルインバータにより駆動される交流負荷の定常動作点が取り得る出力周波数の範囲に対して、変調率に応じて切り替わって実行される
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 低い変調率から当該変調率を大きくすることに合わせて、請求項3に記載の三相3レベルインバータの駆動制御装置による駆動制御、請求項2に記載の三相3レベルインバータの駆動制御装置による駆動制御、請求項4に記載の三相3レベルインバータの駆動制御装置による駆動制御および請求項5に記載の三相3レベルインバータの駆動制御装置による駆動制御が順に切り替わって実行される
ことを特徴とする三相3レベルインバータの駆動制御装置。 - 三相3レベルインバータの一相につき変調波信号の1/4周期である位相0~90度を順に第1~第9の9区間に等分割し、
第1の区間で、前記三相3レベルインバータの出力電位をゼロとし、
第2と第3の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位を一定の正電位に保持し、
第4と第5の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位をゼロとするか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続し、
第6と第7の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位を前記一定の正電位に保持するか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続し、
第8と第9の区間を併せた区間内で、スイッチングを一回行い当該スイッチング後の残る期間は前記出力電位をゼロとするか、または当該スイッチングなしに前記出力電位を前記一定の正電位に保持することを継続することで、
前記第1~前記第9までの区間で二回から四回のいずれかの回数のスイッチングを行い、
前記変調波信号の残りの3/4周期である前記位相90~360度では、各1/4周期毎に前記位相0~90度で行うスイッチングにより出力される波形と上下対称および前後対称の少なくともいずれかとなる波形を出力させ、
残る二相は、前記一相の出力波形とはそれぞれ120度および240度の位相のずれた対称波形を出力させる
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項9に記載の三相3レベルインバータの駆動制御方法であって、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれでスイッチングを一回行い、
前記第6の区間内でスイッチングを一回行い、
前記第9の区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で四回のスイッチングを行い、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれで行うスイッチングのタイミングを調整して、前記第2と前記第3の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間を、前記第4と前記第5の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間よりも短くする
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項9に記載の三相3レベルインバータの駆動制御方法であって、
前記第3および前記第4の区間内それぞれでスイッチングを一回行い、
前記第7および前記第8の区間内それぞれでスイッチングを一回行うことで、
前記第1~前記第9までの区間で四回のスイッチングを行い、
前記第3の区間内および前記第4の区間内それぞれで行うスイッチングのタイミングを調整して、前記第3の区間内で前記出力電位を前記一定の正電位に保持する時間を、前記第4の区間内で前記出力電位を前記一定の正電位に保持する時間よりも短くする
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項9に記載の三相3レベルインバータの駆動制御方法であって、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれでスイッチングを一回行い、
前記第6の区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で三回のスイッチングを行い、
前記第2と前記第3の区間を併せた区間内および前記第4と前記第5の区間を併せた区間内それぞれで行うスイッチングのタイミングを調整して、前記第2と前記第3の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間を、前記第4と前記第5の区間を併せた区間内で前記出力電位を前記一定の正電位に保持する時間よりも短くする
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項9に記載の三相3レベルインバータの駆動制御方法であって、
前記第2と前記第3の区間を併せた区間内でスイッチングを一回行い、
前記第8と前記第9の区間を併せた区間内でスイッチングを一回行うことで、
前記第1~前記第9までの区間で二回のスイッチングを行う
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項10~13のいずれか1項に記載の三相3レベルインバータの駆動制御方法を、変調率および出力周波数指令の少なくともいずれかに応じて切り替える
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 請求項10~13のいずれか1項に記載の三相3レベルインバータの駆動方法を、前記三相3レベルインバータにより駆動される交流負荷の定常動作点が取り得る出力周波数の範囲に対して、変調率に応じて切り替える
ことを特徴とする三相3レベルインバータの駆動制御方法。 - 低い変調率から当該変調率を大きくすることに合わせて、請求項11に記載の三相3レベルインバータの駆動制御方法、請求項10に記載の三相3レベルインバータの駆動制御方法、請求項12に記載の三相3レベルインバータの駆動制御方法および請求項13に記載の三相3レベルインバータの駆動制御方法を順に切り替える
ことを特徴とする三相3レベルインバータの駆動制御方法。
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JPH08331856A (ja) * | 1995-05-30 | 1996-12-13 | Toshiba Corp | 電力変換装置 |
JPH0937592A (ja) * | 1995-07-21 | 1997-02-07 | Toyo Electric Mfg Co Ltd | 3レベルインバータのpwm制御方法および制御装置 |
JPH09182454A (ja) * | 1995-12-26 | 1997-07-11 | Toyo Electric Mfg Co Ltd | スイッチング損失を低減化した3レベルインバータのpwm制御方法および装置 |
EP2312739A1 (en) * | 2009-09-29 | 2011-04-20 | Weg S.A. | Optimal pulse width modulation for multi-level inverter systems |
JP2016032373A (ja) * | 2014-07-29 | 2016-03-07 | 株式会社日立製作所 | 3レベル三相インバータの駆動制御装置 |
WO2016104370A1 (ja) * | 2014-12-24 | 2016-06-30 | 三菱電機株式会社 | 電力変換装置 |
JP2018023210A (ja) * | 2016-08-03 | 2018-02-08 | 株式会社日立製作所 | 電力変換装置および電力変換方法 |
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JPH08331856A (ja) * | 1995-05-30 | 1996-12-13 | Toshiba Corp | 電力変換装置 |
JPH0937592A (ja) * | 1995-07-21 | 1997-02-07 | Toyo Electric Mfg Co Ltd | 3レベルインバータのpwm制御方法および制御装置 |
JPH09182454A (ja) * | 1995-12-26 | 1997-07-11 | Toyo Electric Mfg Co Ltd | スイッチング損失を低減化した3レベルインバータのpwm制御方法および装置 |
EP2312739A1 (en) * | 2009-09-29 | 2011-04-20 | Weg S.A. | Optimal pulse width modulation for multi-level inverter systems |
JP2016032373A (ja) * | 2014-07-29 | 2016-03-07 | 株式会社日立製作所 | 3レベル三相インバータの駆動制御装置 |
WO2016104370A1 (ja) * | 2014-12-24 | 2016-06-30 | 三菱電機株式会社 | 電力変換装置 |
JP2018023210A (ja) * | 2016-08-03 | 2018-02-08 | 株式会社日立製作所 | 電力変換装置および電力変換方法 |
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