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WO2022082747A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022082747A1
WO2022082747A1 PCT/CN2020/123301 CN2020123301W WO2022082747A1 WO 2022082747 A1 WO2022082747 A1 WO 2022082747A1 CN 2020123301 W CN2020123301 W CN 2020123301W WO 2022082747 A1 WO2022082747 A1 WO 2022082747A1
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WIPO (PCT)
Prior art keywords
via hole
pixel electrode
electrode
source electrode
layer
Prior art date
Application number
PCT/CN2020/123301
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English (en)
French (fr)
Inventor
贾宜訸
丁向前
宋勇志
张小祥
李小龙
杨连捷
庞妍
刘静
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/428,622 priority Critical patent/US20220317524A1/en
Priority to PCT/CN2020/123301 priority patent/WO2022082747A1/zh
Priority to CN202080002443.8A priority patent/CN114747011A/zh
Publication of WO2022082747A1 publication Critical patent/WO2022082747A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to an array substrate, a method for manufacturing the same, and a display device.
  • the liquid crystal display panel includes a cell-to-cell (CELL) thin film transistor (Thin Film Transistor, TFT) array substrate and a color filter (Color Filter, CF) substrate, and liquid crystal (Liquid Crystal, LC) molecules are arranged between the array substrate and the color filter substrate. , by controlling the common electrode and the pixel electrode to form an electric field that drives the liquid crystal to deflect, so as to realize grayscale display.
  • CELL cell-to-cell
  • TFT Thin Film Transistor
  • CF color filter
  • the inventors of the present disclosure found that some array substrates are prone to the problem that the pixel electrode and the source electrode cannot be effectively connected.
  • an array substrate including:
  • a thin film transistor disposed on a substrate
  • connection structure for connecting the source electrode of the thin film transistor and the pixel electrode, wherein the connection structure is provided in a via structure exposing the pixel electrode and the source electrode, or the connection A structure is provided between the pixel electrode and the source electrode.
  • an embodiment of the present disclosure further provides a display device, including: the array substrate in the above-mentioned embodiment.
  • an embodiment of the present disclosure also provides a method for preparing an array substrate, including:
  • a first passivation layer, an organic film layer and a pixel electrode disposed on the thin film transistor forming a via structure exposing the pixel electrode and the source electrode of the thin film transistor, and exposing the pixel
  • a connection structure for connecting the source electrode and the pixel electrode is formed in the via structure of the electrode and the source electrode of the thin film transistor; or, a first passivation layer and an organic film layer disposed on the thin film transistor are formed and a pixel electrode, and a connection structure for connecting the source electrode and the pixel electrode is formed between the pixel electrode and the source electrode; or, a first passivation layer, an organic A film layer and a pixel electrode are formed, and a via structure exposing the source electrode is formed, and the pixel electrode is connected to the source electrode through the via structure exposing the source electrode.
  • 1A is a schematic structural diagram of an array substrate in some technologies
  • 1B is a schematic diagram after forming an organic film layer in some techniques
  • 1C is a schematic diagram after etching the first passivation layer in some techniques
  • 1D is a schematic diagram of an organic film layer in some technologies after ashing treatment
  • FIG. 2A is a schematic structural diagram of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 2B is a schematic diagram after forming a pixel electrode in an exemplary embodiment of the present disclosure
  • 2C is a schematic diagram after forming a second passivation layer in an exemplary embodiment of the present disclosure
  • 2D is a schematic diagram of etching the second passivation layer and the first passivation layer in an exemplary embodiment of the disclosure
  • 3A is a schematic structural diagram of an array substrate in another exemplary embodiment of the present disclosure.
  • 3B is a schematic diagram after forming an organic film layer in another exemplary embodiment of the present disclosure.
  • 3C is a schematic diagram after etching the first passivation layer in another exemplary embodiment of the present disclosure.
  • 3D is a schematic diagram of the organic film layer in another exemplary embodiment of the present disclosure after ashing treatment
  • FIG. 4A is a schematic structural diagram of an array substrate in yet another exemplary embodiment of the present disclosure.
  • FIG. 4B is a schematic diagram after forming a first passivation layer in yet another exemplary embodiment of the present disclosure.
  • 4C is a schematic diagram after etching the first passivation layer in yet another exemplary embodiment of the present disclosure.
  • FIG. 4D is a schematic diagram after forming an organic film layer in yet another exemplary embodiment of the present disclosure.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain region or drain electrode) and the source electrode (or source electrode terminal, source region or source electrode), and current can flow through the drain electrode, channel region and source electrode.
  • the channel region refers to a region through which current mainly flows.
  • source electrode and the “drain electrode” may be interchanged in some cases when transistors with opposite polarities are used or when the direction of current in the circuit operation is changed. Therefore, herein, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • the “element having a certain electrical effect” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors, and capacitors.
  • the "patterning process” mentioned in the embodiments of the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist, and is a mature preparation process in some technologies.
  • the deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can use a known coating process, and the etching can use a known method, which is not limited herein.
  • thin film refers to a layer of thin film made by depositing a certain material on a substrate or by other processes.
  • the "film” does not require a patterning process during the entire manufacturing process, the “film” can also be referred to as a "layer”. If a patterning process is required for the "film” during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the array substrate may include: a substrate 10 , a gate electrode 11 disposed on the substrate 10 , a gate insulating layer (Gate Insulator, GI) 12, the active layer (Active) 13, the source electrode 14 and the drain electrode 15 are arranged on the gate insulating layer 12, a conductive channel is formed between the source electrode 14 and the drain electrode 15, covering the source electrode 14, the drain electrode 15 and the first passivation layer (Passivation Layer, PVX) 16 of the conductive channel, the first passivation layer 16 is provided with a first via hole exposing the source electrode 14, and the organic film layer ( Organic Film, ORG) 17, the organic film layer 17 is provided with a second via hole, and the second via hole communicates with the first via hole to form a via hole structure exposing the source electrode 14 (that is, the via hole structure penetrates the organic film layer 17 and The first passivation layer 16 and expose the source electrode 14), the pixel electrode 18 disposed on a substrate 10 , a gate insulating layer (Gate Insulator, GI) 12, the
  • the inventors of the present disclosure found that, as shown in FIG. 1B and FIG. 1C , after the masking (Mask) process of the organic film layer 17 is completed and the first passivation layer 16 etching (Etch) process is performed, the process shown in FIG. 1C will be generated.
  • the problem of undercut shown that is, the slope angle after etching is greater than 90°
  • the first passivation layer 16 is recessed inward compared with the organic film layer 17, which will cause the pixel electrode 18 to be connected to the source electrode 14. It will be disconnected (Open), reducing the yield.
  • the organic film layer 17 can be reversed by adding a photoresist ashing process to the organic film layer 17 . At this time, as shown in FIG.
  • the first passivation layer 16 is not smaller than the organic film layer 17
  • part of the metal in the source electrode 14 that is, the position of the first via on the first passivation layer 16
  • Oxidative corrosion of the metal at the place occurs, resulting in a corrosion layer 21.
  • FIG. 1A since some array substrates are prone to have a corrosion layer 21 between the pixel electrode 18 and the source electrode 14 at the via structure, the pixel electrode 18 will still be disconnected when it is connected to the source electrode 14 (Open ), reducing the yield.
  • an array substrate As shown in FIG. 2A or FIG. 3A , the array substrate may include:
  • connection structure 22 for connecting the source electrode 14 and the pixel electrode 18 of the thin film transistor, wherein the connection structure 22 is provided in the via structure exposing the pixel electrode 18 and the source electrode 14, or the connection structure 22 is provided in the pixel electrode 18 and the source electrode 14.
  • the thin film transistor may include a gate electrode 11 , an active layer 13 , a source electrode 14 and a drain electrode 15 , the gate electrode 11 is disposed on the substrate 10 , and the gate electrode 11 is covered with a gate insulating layer 12 , an active layer 13 , a source electrode 14 and a drain electrode 15 are arranged on the gate insulating layer 12 , and a conductive channel is formed between the source electrode 14 and the drain electrode 15 .
  • the array substrate may further include: a second passivation layer 19 disposed on the side of the pixel electrode 18 away from the substrate 10 ; the connection structure 22 is disposed on the exposed pixel electrode.
  • 18 and the via structure of the source electrode 14 may include: the first passivation layer 16 is provided with a first via hole exposing the source electrode 14; the organic film layer 17 is provided with a first via hole communicating with the first via hole.
  • the pixel electrode 18 is provided with a third via hole that communicates with the second via hole;
  • the second passivation layer 19 is provided with a fourth via hole that communicates with the third via hole and exposes the pixel electrode 18 ;
  • the four via holes, the third via hole, the second via hole and the first via hole form a via hole structure exposing the pixel electrode 18 and the source electrode 14;
  • the connection structure 22 is connected with the pixel electrode 18 through the via hole structure, and is connected with the source electrode 14 connections.
  • the source electrode and the pixel electrode are exposed at the same time by using the via structure, and the connection structure is arranged at the position of the via structure.
  • the connection structure can be connected with the source electrode exposed in the via structure, and can be connected with the via structure.
  • the pixel electrode exposed by the hole structure is connected.
  • the connection structure can cover the source electrode exposed in the via hole structure, and can cover the pixel electrode exposed in the via hole structure, so that the pixel electrode and the source electrode can be guaranteed. Effective connection, improve yield.
  • the array substrate may further include: a second passivation layer 19 disposed on the side of the pixel electrode 18 away from the substrate 10 , and a second passivation layer 19 disposed away from the second passivation layer 19
  • the material of the connection structure may include indium tin oxide or indium zinc oxide.
  • connection structure 22 is disposed between the pixel electrode 18 and the source electrode 14, which may include: the connection structure 22 is disposed on the side of the source electrode 14 away from the substrate 10; the first The passivation layer 16 is disposed on the side of the connection structure 22 away from the substrate 10, and is provided with a first via hole exposing the connection structure 10; the organic film layer 17 is provided with a second via hole communicating with the first via hole; The second via hole and the first via hole form a via hole structure exposing the connection structure 22 ; the pixel electrode 18 is connected with the connection structure 22 through the via hole structure, and the connection structure 22 is connected with the source electrode 14 .
  • the material of the connection structure is an oxidative corrosion resistant and conductive material.
  • the oxidative corrosion resistant and electrically conductive material includes any one of chrome cobalt, nichrome, and tellurium chrome.
  • the array substrate may further include other film layers, such as a common electrode (Com) lead, a flat layer, or a touch (Touch) lead, etc., which are not limited here.
  • a common electrode (Com) lead such as a flat electrode (Com) lead, a flat layer, or a touch (Touch) lead, etc., which are not limited here.
  • the organic film layer is disposed on the side of the pixel electrode close to the substrate, and is used to separate the Touch/Com line (eg, the same layer and the same material as the source electrode and the drain electrode) and the material of the pixel electrode source.
  • the Touch/Com line eg, the same layer and the same material as the source electrode and the drain electrode
  • the organic film layer may use organic materials such as polyimide, naphthoquinonediazide and the like.
  • the first passivation layer is disposed on the side of the organic film layer close to the substrate, for preventing the organic film layer from contaminating the conductive channel.
  • connection structure for connecting the source electrode and the pixel electrode of the thin film transistor is arranged in the via structure exposing the pixel electrode and the source electrode.
  • FIG. 2A is a schematic structural diagram of an array substrate in an exemplary embodiment of the present disclosure.
  • the array substrate may include:
  • the active layer 13, the source electrode 14 and the drain electrode 15 are arranged on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15;
  • first passivation layer 16 covering the source electrode 14, the drain electrode 15 and the conductive channel, and a first via hole exposing the source electrode 14 is opened on the first passivation layer 16;
  • the pixel electrode 18 disposed on the organic film layer 17, the pixel electrode 18 is provided with a third via hole, the first end of the pixel electrode 18 goes deep into the second via hole, and the second end of the pixel electrode 18 goes deep into the second via hole , the third via hole is located between the first end of the pixel electrode 18 and the second end of the pixel electrode 18, and the third via hole communicates with the first via hole;
  • the second passivation layer 19 is disposed on the pixel electrode 18, a fourth via hole is opened on the second passivation layer 19, the first end of the second passivation layer 19 is deep into the third via hole, and the second passivation layer The second end of 19 is deep into the third via hole, the fourth via hole is located between the first end of the second passivation layer 19 and the second end of the second passivation layer 19, and the fourth via hole is connected to the first via hole. connected, the fourth via hole exposes the pixel electrode 18;
  • the common electrode 20 and the connection structure 22 are disposed on the second passivation layer 19 , and the connection structure 22 is located within the via structure, wherein the via structure consists of the fourth via on the second passivation layer 19 , the pixel electrode 18
  • the third via hole on the upper passivation layer 17, the second via hole on the organic film layer 17 and the first via hole on the first passivation layer 16 are formed (that is, the via hole structure penetrates the second passivation layer 19, the pixel electrode 18, the organic film layer 17 and the first passivation layer 16), and expose the source electrode 14 and the pixel electrode 18;
  • the connection structure 22 is arranged at the position of the via structure, on the one hand is connected with the source electrode 14 exposed in the via structure, and on the other hand
  • One aspect is connected to the pixel electrode 18 exposed by the via structure, that is, the connection structure 22 is simultaneously connected to the source electrode 14 and the pixel electrode 18 through the via structure.
  • the gate electrode 11 , the active layer 13 , the source electrode 14 and the drain electrode 15 may form a thin film transistor.
  • the pixel electrode 18 may be a plate electrode
  • the common electrode 20 may be a slit electrode
  • the common electrode 20 and the pixel electrode 18 together form a multi-dimensional electric field to drive liquid crystal deflection.
  • the common electrode 20 and the connection structure 22 may be provided in the same layer and the same material.
  • both the common electrode 20 and the connection structure 22 can be made of conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the same-layer arrangement means that it can be fabricated by one patterning process.
  • the one-time patterning process refers to the process of forming the required layer structure through one exposure.
  • One patterning process may include processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping.
  • a method for fabricating an array substrate may include:
  • the pixel electrode 18 is provided with a third via hole, the first end of the pixel electrode 18 penetrates into the second via hole, and the second end of the pixel electrode 18 penetrates into the second via hole In the via hole, the third via hole is located between the first end of the pixel electrode 18 and the second end of the pixel electrode 18 , and the third via hole communicates with the second via hole.
  • the first via is connected to the second via, the first end of the second passivation layer 19 penetrates into the third via, the second end of the second passivation layer 19 penetrates into the third via, and the fourth through
  • the hole is located between the first end of the second passivation layer 19 and the second end of the second passivation layer 19, the fourth via hole is communicated with the first via hole, and the via hole structure can be composed of the first via hole, the second via hole and the second via hole.
  • a hole, a third via hole and a fourth via hole are formed, the second passivation layer 19, the pixel electrode 18, the organic film layer 17 and the first passivation layer 16 in the via hole structure are etched away, and the source is exposed at the same time electrode 14 and pixel electrode 18 .
  • connection structure 22 is located in the via structure (formed by the first via, the second via, the third via and the fourth via ), on the one hand, it is connected to the source electrode 14 exposed in the via structure, and on the other hand, it is connected to the pixel electrode 18 exposed by the via structure, that is, the connection structure 22 is simultaneously connected to the source electrode 14 and the pixel electrode through the via structure. 18 connections.
  • step S21 may include:
  • S212 coat a layer of photoresist on the first metal film, use a half-tone or gray-tone mask to step exposure and develop the photoresist, and form an unexposed area (with a first thickness of photoresist) at the gate electrode position photoresist) and fully exposed areas (without photoresist) elsewhere.
  • the substrate may be glass, plastic, or a flexible transparent plate.
  • the first metal thin film can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or a multi-layer composite structure.
  • metal materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or
  • step S22 may include:
  • S222 coat a layer of photoresist on the second metal film, use a half-tone or gray-tone mask to step exposure and develop the photoresist, and form an unexposed area (with the first Thickness of photoresist), a partially exposed area (with a second thickness of photoresist) is formed at the location of the conductive channel, and a fully exposed area (no photoresist) is formed at other locations.
  • the first thickness is greater than the second thickness.
  • the gate insulating film may adopt silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer or multi-layer structure , can be deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the second metal thin film may be a mixture of one or more metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium, and may be a single layer , double-layer or multi-layer structure, which can be deposited by radio frequency magnetron sputtering method.
  • metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium
  • step S23 may include:
  • the first passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • step S24 may include:
  • the organic film thin film may be an organic material such as polyimide, naphthoquinone diazide and the like.
  • step S25 may include:
  • the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • step S26 may include:
  • the via structure can be formed by the first via hole, the second via hole, the third via hole and the fourth via hole, the second passivation layer, the pixel electrode, the organic film layer and the first via hole structure in the via hole structure
  • the passivation layer is etched away, exposing the source and pixel electrodes at the same time
  • the second passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • step S27 may include:
  • connection structure is arranged where the via structure is located The position is connected to the source electrode exposed in the via structure on the one hand, and connected to the pixel electrode exposed by the via structure on the other hand, that is, the connection structure is simultaneously connected to the source electrode and the pixel electrode through the via structure.
  • the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • the gate electrode, the gate insulating layer, the active layer, the source electrode and the drain electrode can be completed by a secondary patterning process.
  • the gate electrode is formed by a patterning process, and then the gate insulating layer, active layer, source and drain electrodes.
  • the gate insulating layer, the active layer, the source electrode and the drain electrode can also be completed by a secondary patterning process.
  • the gate insulating layer and the active layer are formed by a patterning process, and then the source electrode and the drain electrode are formed by another patterning process. pole.
  • the common electrode and the connection structure can also be completed by a secondary patterning process, firstly, the common electrode is formed by one patterning process, and then the connection structure is formed by another patterning process.
  • An array substrate provided by an embodiment of the present disclosure is provided with a via structure penetrating the second passivation layer, the pixel electrode, the organic film layer and the first passivation layer, and the source electrode and the pixel electrode are exposed simultaneously by using the via structure, and A connection structure is arranged at the position of the via hole structure, and the connection structure is used to connect with the source electrode and the pixel electrode through the via hole structure at the same time.
  • the first passivation layer does not need to be etched, so that the problem of undercut will not occur.
  • connection structure is connected with the source electrode exposed in the via structure, and on the other hand, it is connected with the pixel electrode exposed in the via structure, which can ensure the effective connection between the pixel electrode and the source electrode and improve the yield.
  • connection structure for connecting the source electrode of the thin film transistor and the pixel electrode is disposed between the pixel electrode and the source electrode.
  • FIG. 3A is a schematic structural diagram of an array substrate in another exemplary embodiment of the present disclosure.
  • another array substrate provided by an embodiment of the present disclosure may include:
  • the active layer 13, the source electrode 14 and the drain electrode 15 are arranged on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15;
  • connection structure 22 covering the source electrode 14 and the drain electrode 15;
  • the pixel electrode 18 disposed on the organic film layer 17, the pixel electrode 18 is recessed to form a first groove at the position of the via hole structure toward the substrate, and the first groove formed by the pixel electrode 18 is disposed in the via hole structure.
  • the bottom of a groove is connected to the connection structure 22, that is, the connection structure 22 is connected to the source electrode 14 on the one hand, and is connected to the pixel electrode 18 through the via structure on the other hand, that is, through the second connection structure 22 and the via structure, the pixel electrode
  • the electrode 18 is connected to the source electrode 14;
  • the second groove is arranged in the first groove;
  • the common electrode 20 is provided on the second passivation layer 19 .
  • the gate electrode 11 , the active layer 13 , the source electrode 14 and the drain electrode 15 may form a thin film transistor.
  • the first passivation layer is disposed on the side of the organic film layer close to the substrate, for preventing the organic film layer from contaminating the conductive channel.
  • the pixel electrode 18 may be a plate electrode
  • the common electrode 20 may be a slit electrode
  • the common electrode 20 and the pixel electrode 18 together form a multi-dimensional electric field to drive the liquid crystal to deflect.
  • connection structure may be made of oxidative corrosion-resistant and conductive materials such as chromium-cobalt alloy, nickel-chromium alloy, and tellurium-nickel-chromium alloy.
  • another method for fabricating an array substrate may include:
  • connection structure 22 covering the source electrode 14 and the drain electrode 15 .
  • connection structure 22 forming the first passivation layer 16 covering the connection structure 22 and the conductive channel, and forming the organic film layer 17 covering the first passivation layer 16, and the first passivation layer 16 is provided with a first passivation layer exposing the connection structure 22 A via hole
  • the connection structure 23 is connected to the source electrode 14 at the position of the first via hole
  • the organic film layer 17 is provided with a second via hole
  • the second via hole communicates with the first via hole to form a via exposing the connection structure 22
  • the hole structure ie the via hole structure penetrates the organic film layer 17 and the first passivation layer 16, and exposes the connection structure 22);
  • the pixel electrode 18 is recessed in the direction of the via structure toward the substrate to form a first groove, and the first groove formed by the pixel electrode 18 is disposed in the via structure
  • the bottom of the first groove is connected to the connection structure 22, that is, the connection structure 22 is connected to the source electrode 14 on the one hand, and is connected to the pixel electrode 18 through the via structure on the other hand, that is, the connection structure 22 is connected to the source electrode 14 and the pixel electrode 18 at the same time.
  • the pixel electrodes 18 are connected.
  • the second passivation layer 19 is recessed in the direction of the first groove toward the substrate to form a second groove, and the second passivation layer 19 forms a second groove.
  • the groove is provided in the first groove.
  • step S31 may include:
  • the substrate may be glass, plastic, or a flexible transparent plate.
  • the first metal thin film can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or a multi-layer composite structure.
  • metal materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or
  • step S32 may include:
  • the gate insulating film may adopt silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer or multi-layer structure , can be deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the second metal thin film may be a mixture of one or more metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium, and may be a single layer , double-layer or multi-layer structure, which can be deposited by radio frequency magnetron sputtering method.
  • metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium
  • step S33 may include:
  • S331 deposit an anti-oxidation conductive film on the source electrode and the drain electrode, and form a connection structure on the side of the source electrode and the drain electrode away from the substrate.
  • the anti-oxidation conductive thin film can be made of chromium-cobalt alloy, nickel-chromium alloy, tellurium-nickel-chromium alloy and other anti-oxidative corrosion-resistant and conductive materials, and can be a single-layer, double-layer or multi-layer structure. Deposited by radio frequency magnetron sputtering.
  • step S34 may include:
  • the first passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the organic film thin film may be an organic material such as polyimide, naphthoquinone diazide and the like.
  • step S35 may include:
  • S352 coat a layer of photoresist on the first transparent conductive film, use a single-tone mask to expose and develop the photoresist, and form a fully exposed area (without photoresist) at the pixel electrode position, and at other positions Form unexposed areas (retain photoresist);
  • the fully exposed area is etched by an etching process, and the first transparent conductive film in the area is etched to form a pixel electrode, and the pixel electrode 18 is recessed in the direction of the via structure toward the substrate to form a first groove
  • the first groove formed by the pixel electrode 18 is arranged in the via structure, and the groove bottom of the first groove is connected to the connection structure 22, that is, the connection structure 22 is connected to the source electrode 14 on the one hand, and is connected to the source electrode 14 through the via structure on the other hand.
  • the pixel electrode 18 is connected, that is, the connection structure 22 is connected to the source electrode 14 and the pixel electrode 18 at the same time.
  • the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • step S36 may include:
  • the second passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • step S37 may include:
  • the common electrode may be a slit electrode.
  • the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • the gate electrode, the gate insulating layer, the active layer, the source electrode and the drain electrode can be completed by a secondary patterning process.
  • the gate electrode is formed by a patterning process, and then the gate insulating layer, active layer, source and drain electrodes.
  • the gate insulating layer, the active layer, the source electrode and the drain electrode can also be completed by a secondary patterning process.
  • the gate insulating layer and the active layer are formed by a patterning process, and then the source electrode and the drain electrode are formed by another patterning process. pole.
  • Another array substrate provided by the embodiment of the present disclosure is provided with a via structure penetrating through the organic film layer and the first passivation layer, and exposing the connection structure, and an anti-oxidative and conductive structure is provided between the source electrode and the pixel electrode.
  • the connection structure uses the connection structure to connect to the source electrode on the one hand, and to the pixel electrode through the via structure on the other hand, that is, through the connection structure and the via structure, the pixel electrode is connected to the source electrode.
  • connection structure is anti-oxidative and conductive, and the connection structure covers the source electrode, the connection structure can protect the metal in the source electrode from oxidative corrosion, so that no corrosion layer is generated.
  • the connection structure is connected with the source electrode on the one hand, and connected with the pixel electrode through the via structure on the other hand, which can ensure the effective connection between the pixel electrode and the source electrode, and improve the yield.
  • the array substrate provided by the present disclosure will be described in detail below by taking the direct connection between the pixel electrode and the source electrode as an example.
  • FIG. 4A is a schematic structural diagram of an array substrate in another exemplary embodiment of the present disclosure.
  • another array substrate provided by an embodiment of the present disclosure may include:
  • the active layer 13, the source electrode 14 and the drain electrode 15 are arranged on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15;
  • first passivation layer 16 covering the source electrode 14, the drain electrode 15 and the conductive channel, and a first via hole exposing the source electrode 14 is opened on the first passivation layer 16;
  • the organic film layer 17 covering the first passivation layer 16 is provided with a second via hole, and the second via hole communicates with the first via hole to form a via hole structure (ie, via hole structure) exposing the source electrode 14 Passing through the organic film layer 17 and the first passivation layer 16, and exposing the source electrode 14), the two sides of the organic film layer 17 close to the source electrode 14 protrude into the first via hole;
  • a via hole structure ie, via hole structure
  • the bottom of a groove is connected to the source electrode 14, that is, the pixel electrode 18 is connected to the source electrode 14 through the via structure;
  • the second groove is arranged in the first groove;
  • the common electrode 20 is provided on the second passivation layer 19 .
  • the gate electrode 11 , the active layer 13 , the source electrode 14 and the drain electrode 15 may form a thin film transistor.
  • the pixel electrode 18 may be a plate electrode
  • the common electrode 20 may be a slit electrode
  • the common electrode 20 and the pixel electrode 18 together form a multi-dimensional electric field to drive liquid crystal deflection.
  • connection structure may be made of oxidative corrosion-resistant and conductive materials such as chromium-cobalt alloy, nickel-chromium alloy, and tellurium-nickel-chromium alloy.
  • another method for fabricating an array substrate may include:
  • a second via hole is formed on the organic film layer 17, and the second via hole communicates with the first via hole to form a via hole structure exposing the source electrode 14 (ie The via structure penetrates through the organic film layer 17 and the first passivation layer 16, and exposes the source electrode 14), and the two sides of the organic film layer 17 close to the source electrode 14 extend into the first via hole;
  • the pixel electrode 18 is recessed in the direction of the via structure toward the substrate to form a first groove, and the first groove formed by the pixel electrode 18 is disposed in the via structure , the bottom of the first groove is connected to the source electrode 14, that is, the pixel electrode 18 is connected to the source electrode 14 through the via structure;
  • step S41 may include:
  • the substrate may be glass, plastic, or a flexible transparent plate.
  • the first metal thin film can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or a multi-layer composite structure.
  • metal materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or indium tin oxide (ITO) , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), Indium Oxide (In2O3), Aluminum-doped Zinc Oxide (AlZnO) and other conductive oxides, which can be a single-layer structure or
  • step S42 may include:
  • the gate insulating film may adopt silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer or multi-layer structure , can be deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the second metal thin film may be a mixture of one or more metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium, and may be a single layer , double-layer or multi-layer structure, which can be deposited by radio frequency magnetron sputtering method.
  • metal materials such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium
  • step S43 may include:
  • the first passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • step S44 may include:
  • the organic film thin film may be an organic material such as polyimide, naphthoquinonediazide and the like.
  • step S45 may include:
  • the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • step S46 may include:
  • the second passivation film may be a mixture of one or more inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Si(ON)x silicon oxynitride
  • Si(ON)x silicon oxynitride
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • step S47 may include:
  • the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited by a radio frequency magnetron sputtering (Sputter) method.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Sputter radio frequency magnetron sputtering
  • the gate electrode, the gate insulating layer, the active layer, the source electrode and the drain electrode can be completed by a secondary patterning process.
  • the gate electrode is formed by a patterning process, and then the gate insulating layer, active layer, source and drain electrodes.
  • the gate insulating layer, the active layer, the source electrode and the drain electrode can also be completed by a secondary patterning process.
  • the gate insulating layer and the active layer are formed by a patterning process, and then the source electrode and the drain electrode are formed by another patterning process. pole.
  • the first passivation layer etching process is performed first, and then the organic film layer masking process is performed.
  • Undercut problem therefore, there is no need to add a photoresist ashing (Ashing) process to the organic film layer to reverse the organic film layer, and further, there will be no problem of oxidation and corrosion of part of the metal in the source electrode. .
  • Ashing photoresist ashing
  • the preparation process of another array substrate provided by the embodiment of the present disclosure can also save an ashing process, reduce production cost, and improve production efficiency.
  • connection structure for connecting the source electrode and the pixel electrode of the thin film transistor disposed in the via structure exposing the pixel electrode and the source electrode as an example, the embodiment of the present disclosure also provides an array substrate.
  • a preparation method the method may include:
  • S52 forming a first passivation layer, an organic film layer and a pixel electrode disposed on the thin film transistor, forming a via structure exposing the pixel electrode and the source electrode of the thin film transistor, and exposing the source electrode of the pixel electrode and the thin film transistor A connection structure for connecting the source electrode and the pixel electrode is formed in the via structure of the electrode.
  • step S52 may include:
  • connection structure for connecting the source electrode and the pixel electrode in the via structure exposing the pixel electrode and the source electrode of the thin film transistor.
  • step S525 may include:
  • a common electrode is formed on the second passivation layer, and a connection structure for connecting the source electrode and the pixel electrode is formed in the via structure exposing the pixel electrode and the source electrode of the thin film transistor.
  • the embodiment of the present disclosure also provides a method for fabricating an array substrate, which can include:
  • S62 forming a first passivation layer, an organic film layer and a pixel electrode disposed on the thin film transistor, and forming a connection structure between the pixel electrode and the source electrode for connecting the source electrode and the pixel electrode.
  • step S62 may include:
  • S622 forming a first passivation layer covering the connection structure, and forming an organic film layer covering the first passivation layer, a second via hole is formed on the organic film layer, and a second via hole is formed on the first passivation layer connecting and exposing the first via hole of the connection structure, the second via hole and the first via hole form a via hole structure exposing the connection structure, and the connection structure is connected to the source electrode;
  • S623 forming a pixel electrode disposed on the organic film layer, and the pixel electrode is connected to the connection structure through the via structure;
  • step S622 may include:
  • S6222 coat a layer of photoresist on the first passivation film, use a mask to expose and develop the photoresist, form an exposed area at the connection structure position, and form an unexposed area at other positions;
  • S6223 depositing an organic film film on the first passivation film coated with photoresist
  • S6224 Coat a layer of photoresist on the organic film, use a mask to expose and develop the photoresist, form a partially exposed area and a fully exposed area at the position of the second via hole, and form an unexposed area at other positions ;
  • S6226 etching the fully exposed area of the first passivation film by an etching process to form a first passivation layer with a first via hole;
  • the embodiment of the present disclosure also provides a method for fabricating an array substrate, the method may include:
  • step S72 may include:
  • S721 forming a first passivation layer covering the thin film transistor, and opening a first via hole exposing the source electrode on the first passivation layer;
  • S722 forming an organic film layer covering the first passivation layer, a second via hole is opened on the organic film layer, and the second via hole is connected with the first via hole to form a via hole structure exposing the source electrode;
  • Embodiments of the present disclosure further provide a display device including the array substrate of the foregoing embodiments.
  • the display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种阵列基板及其制备方法、显示装置，所述阵列基板包括：基底；设置在基底上的薄膜晶体管；设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极；用于连接所述薄膜晶体管的源电极和所述像素电极的连接结构，其中，所述连接结构设置在暴露出所述像素电极和所述源电极的过孔结构之中，或者，所述连接结构设置在所述像素电极和所述源电极之间。

Description

阵列基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种阵列基板及其制备方法、显示装置。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有体积小、功耗低、无辐射等特点，近年来得到迅速发展。液晶显示面板包括对盒(CELL)的薄膜晶体管(Thin Film Transistor，TFT)阵列基板和彩膜(Color Filter，CF)基板，液晶(Liquid Crystal，LC)分子设置在阵列基板和彩膜基板之间，通过控制公共电极和像素电极来形成驱动液晶偏转的电场，实现灰阶显示。
经本公开发明人研究发现，一些阵列基板，容易出现像素电极与源电极无法有效连接的问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供了一种阵列基板，包括：
基底；
设置在基底上的薄膜晶体管；
设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极；
用于连接所述薄膜晶体管的源电极和所述像素电极的连接结构，其中，所述连接结构设置在暴露出所述像素电极和所述源电极的过孔结构之中，或者，所述连接结构设置在所述像素电极和所述源电极之间。
另一方面，本公开实施例还提供了一种显示装置，包括：上述实施例中的阵列基板。
另一方面，本公开实施例还提供了一种阵列基板的制备方法，包括：
形成基底，在所述基底上形成薄膜晶体管；
形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构，并在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构；或者，形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并在所述像素电极和所述源电极之间形成用于连接所述源电极和所述像素电极的连接结构；或者，形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述源电极的过孔结构，所述像素电极通过所述暴露出所述源电极的过孔结构与所述源电极连接。
当然，实施本公开的任一产品或方法并不一定要同时达到以上所述的所有优点。本公开的其它特征和优点将在随后的说明书实施例中阐述，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为一些技术中的阵列基板的结构示意图；
图1B为一些技术中的形成有机膜层后的示意图；
图1C为一些技术中的刻蚀第一钝化层后的示意图；
图1D为一些技术中的有机膜层进行灰化处理后的示意图；
图2A为本公开的一种示例性实施例中的阵列基板的结构示意图；
图2B为本公开的一种示例性实施例中的形成像素电极后的示意图；
图2C为本公开的一种示例性实施例中的形成第二钝化层后的示意图；
图2D为本公开的一种示例性实施例中的刻蚀第二钝化层和第一钝化层的示意图；
图3A为本公开的另一种示例性实施例中的阵列基板的结构示意图；
图3B为本公开的另一种示例性实施例中的形成有机膜层后的示意图；
图3C为本公开的另一种示例性实施例中的刻蚀第一钝化层后的示意图；
图3D为本公开的另一种示例性实施例中的有机膜层进行灰化处理后的示意图；
图4A为本公开的又一种示例性实施例中的阵列基板的结构示意图；
图4B为本公开的又一种示例性实施例中的形成第一钝化层后的示意图；
图4C为本公开的又一种示例性实施例中的刻蚀第一钝化层后的示意图；
图4D为本公开的又一种示例性实施例中的形成有机膜层后的示意图。
附图标记说明：
10—基底；         11—栅电极；     12—栅绝缘层；
13—有源层；       14—源电极；     15—漏电极；
16—第一钝化层；   17—有机膜层；   18—像素电极；
19—第二钝化层；   20—公共电极；   21—腐蚀层；
22—连接结构。
具体实施方式
本文描述了多个实施例，但是该描述是示例性的，而不是限制性的，在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征 或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
除非另外定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
在本文中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(或称漏电极端子、漏区域或漏电极)与源电极(或称源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本文中，沟道区域是指电流主要流过的区域。
在本文中，在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本文中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
本公开实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是一些技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本公开实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
图1A为一些技术中的阵列基板的结构示意图，如图1A所示，该阵列基板可以包括：基底10，设置在基底10上的栅电极11，覆盖栅电极11的栅绝缘层(Gate Insulator，GI)12，设置在栅绝缘层12上的有源层(Active)13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道，覆盖源电极14、漏电极15和导电沟道的第一钝化层(Passivation Layer，PVX)16，第一钝化层16上开设有暴露出源电极14的第一过孔，覆盖第一钝化层16的有机膜层(Organic Film，ORG)17，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通形成暴露出源电极14的过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出源电极14)，设置在有机膜层17上的像素电极18，设置在像素电极18上的第二钝化层19，设置在第二钝化层19上的公共电极20。其中，公共电极20用于提供公共电压，像素电极18用于提供显示用像素电压，公共电极与像素电极之间产生的多维电场驱动液晶偏转。
经本公开发明人研究发现，如图1B和图1C所示，在结束有机膜层17掩膜(Mask)工艺，进行第一钝化层16刻蚀(Etch)工艺后，会产生如图1C所示的钻刻(Undercut)问题(即刻蚀后坡度角大于90°)，此时，第一钝化层16较有机膜层17向内凹陷，会导致像素电极18在与源电极14连接时会断开(Open)，降低了良品率。接下来，可以通过对有机膜层17增加光刻胶灰化(Ashing)工艺来使有机膜层17倒退，此时，如图1D所示，第一钝化层16较有机膜层17并未向内凹陷，但是，在对有机膜层17进行光刻 胶灰化(Ashing)工艺时，却会导致源电极14中的部分金属(即位于第一钝化层16上的第一过孔位置处的金属)发生氧化腐蚀，产生腐蚀层21。进而，如图1A所示，由于一些阵列基板在过孔结构处像素电极18与源电极14之间容易存在腐蚀层21，仍然会导致像素电极18在与源电极14连接时会断开(Open)，降低了良品率。
本公开实施例提供一种阵列基板，如图2A或图3A所示，该阵列基板可以包括：
基底10；
设置在基底10上的薄膜晶体管；
设置在薄膜晶体管上的第一钝化层16、有机膜层17和像素电极18；
用于连接薄膜晶体管的源电极14和像素电极18的连接结构22，其中，连接结构22设置在暴露出像素电极18和源电极14的过孔结构之中，或者，连接结构22设置在像素电极18和源电极14之间。
在一种示例性实施例中，如图2A或图3A所示，薄膜晶体管可以包括栅电极11、有源层13、源电极14和漏电极15，栅电极11设置在基底10上，栅电极11上覆盖有栅绝缘层12，有源层13、源电极14和漏电极15设置在栅绝缘层12上，源电极14与漏电极15之间形成导电沟道。
在一种示例性实施例中，如图2A所示，该阵列基板还可以包括：设置在像素电极18远离基底10的一侧的第二钝化层19；连接结构22设置在暴露出像素电极18和源电极14的过孔结构之中，可以包括：第一钝化层16上开设有暴露出源电极14的第一过孔；有机膜层17上开设有与第一过孔连通的第二过孔；像素电极18上开设有与第二过孔连通的第三过孔；第二钝化层19上开设有与第三过孔连通并暴露出像素电极18的第四过孔；第四过孔、第三过孔、第二过孔和第一过孔形成暴露出像素电极18和源电极14的过孔结构；连接结构22通过过孔结构与像素电极18连接，并与源电极14连接。
如此，利用过孔结构同时暴露出源电极和像素电极，并在过孔结构所在位置设置连接结构，这样，一方面，连接结构可以与过孔结构中暴露出的源电极连接，并可以与过孔结构暴露出的像素电极连接，另一方面，连接结构 可以覆盖过孔结构中暴露出的源电极，并可以覆盖过孔结构中暴露出的像素电极，从而，能够保证像素电极与源电极的有效连接，提高良品率。
在一种示例性实施例中，如图2A所示，该阵列基板还可以包括：设置在像素电极18远离基底10的一侧的第二钝化层19和设置在第二钝化层19远离基底10的一侧上的公共电极20；其中，连接结构22与公共电极20可以同层同材料设置。如此，公共电极和连接结构可以采用一次构图工艺形成。
在一种示例性实施例中，连接结构的材料可以包括氧化铟锡或者氧化铟锌。
在一种示例性实施例中，如图3A所示，连接结构22设置在像素电极18和源电极14之间，可以包括：连接结构22设置在源电极14远离基底10的一侧；第一钝化层16设置在连接结构22远离基底10的一侧，并开设有暴露出连接结构10的第一过孔；有机膜层17上开设有与第一过孔连通的第二过孔；第二过孔与第一过孔形成暴露出连接结构22的过孔结构；像素电极18通过过孔结构与连接结构22连接，连接结构22与源电极14连接。
在一种示例性实施例中，连接结构的材料为抗氧化腐蚀且导电的材料。
在一种示例性实施例中，抗氧化腐蚀且导电的材料包括铬钴合金、镍铬合金和碲镍铬合金中的任意一种。
在一种示例性实施例中，阵列基板还可以包括其他膜层，如公共电极(Com)引线或平坦层或触控(Touch)引线等，这里不作限定。
在一种示例性实施例中，有机膜层设置在像素电极靠近基底的一侧，用于分隔Touch/Com线(如与源电极、漏电极同层同材料设置)与像素电极源的材料。
在一种示例性实施例中，有机膜层可以采用聚酰亚胺、萘醌二叠氮化合物等有机材料。
在一种示例性实施例中，第一钝化层设置在有机膜层靠近基底的一侧，用于防止有机膜层污染导电沟道。
下面以用于连接薄膜晶体管的源电极和像素电极的连接结构设置在暴露 出像素电极和源电极的过孔结构之中为例，对本公开提供的阵列基板进行详细说明。
图2A为本公开的一种示例性实施例中的阵列基板的结构示意图，如图2A所示，该阵列基板可以包括：
基底10；
设置在基底10上的栅电极11；
覆盖栅电极11的栅绝缘层12；
设置在栅绝缘层12上的有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道；
覆盖源电极14、漏电极15和导电沟道的第一钝化层16，第一钝化层16上开设有暴露出源电极14的第一过孔；
覆盖第一钝化层16的有机膜层17，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通；
设置在有机膜层17上的像素电极18，像素电极18上开设有第三过孔，像素电极18的第一端深入第二过孔内，像素电极18的第二端深入第二过孔内，第三过孔位于像素电极18的第一端与像素电极18的第二端之间，第三过孔与第一过孔连通；
设置在像素电极18上的第二钝化层19，第二钝化层19上开设有第四过孔，第二钝化层19的第一端深入第三过孔内，第二钝化层19的第二端深入第三过孔内，第四过孔位于第二钝化层19的第一端与第二钝化层19的第二端之间，第四过孔与第一过孔连通，第四过孔暴露出像素电极18；
设置在第二钝化层19上的公共电极20和连接结构22，连接结构22位于过孔结构之内，其中，过孔结构由第二钝化层19上的第四过孔、像素电极18上的第三过孔、有机膜层17上的第二过孔以及第一钝化层16上的第一过孔形成(即过孔结构贯穿第二钝化层19、像素电极18、有机膜层17和第一钝化层16)，并暴露出源电极14和像素电极18；连接结构22设置在过孔结构所在位置，一方面与过孔结构中暴露出的源电极14连接，另一方面与过孔 结构暴露出的像素电极18连接，即连接结构22通过过孔结构同时与源电极14和像素电极18连接。
在一种示例性实施例中，如图2A所示，栅电极11、有源层13、源电极14和漏电极15可以形成薄膜晶体管。
在一种示例性实施例中，如图2A所示，像素电极18可以为板状电极，公共电极20可以为狭缝电极，公共电极20与像素电极18一起形成多维电场驱动液晶偏转。
在一种示例性实施例中，公共电极20和连接结构22可以同层同材料设置。例如，公共电极20和连接结构22都可以采用氧化铟锡(ITO)、氧化铟锌(IZO)等导电材料。这里，同层设置是指可以采用一次构图工艺制作。一次构图工艺是指经过一次曝光形成所需要的层结构工艺。一次构图工艺可以包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等工艺。
下面以如图2A所示的阵列基板为例，通过本公开实施例提供的一种阵列基板的制备过程，说明本公开实施例的技术方案。
如图2A至图2D所示，本公开实施例提供的一种阵列基板的制备方法可以包括：
S21、在基底10上形成栅电极11。
S22、形成覆盖栅电极11的栅绝缘层12，并在栅绝缘层12上形成有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道。
S23、形成覆盖源电极14、漏电极15和导电沟道的第一钝化层16。
S24、形成覆盖第一钝化层16的有机膜层17，有机膜层17上开设有第二过孔。
S25、形成设置在有机膜层17上的像素电极18，像素电极18上开设有第三过孔，像素电极18的第一端深入第二过孔内，像素电极18的第二端深入第二过孔内，第三过孔位于像素电极18的第一端与像素电极18的第二端之间，第三过孔与第二过孔连通。
S26、形成设置在像素电极18上的第二钝化层19，并形成位于第二钝化层上的暴露出像素电极18的第四过孔以及位于第一钝化层上的暴露出源电极14的第一过孔。
其中，第一过孔与第二过孔连通，第二钝化层19的第一端深入第三过孔内，第二钝化层19的第二端深入第三过孔内，第四过孔位于第二钝化层19的第一端与第二钝化层19的第二端之间，第四过孔与第一过孔连通，过孔结构可以由第一过孔、第二过孔、第三过孔和第四过孔形成，过孔结构内的第二钝化层19、像素电极18、有机膜层17和第一钝化层16被刻蚀掉，并同时暴露出源电极14和像素电极18。
S27、形成设置在第二钝化层19上的公共电极20和连接结构22，连接结构22位于过孔结构(由第一过孔、第二过孔、第三过孔和第四过孔形成)之内，一方面与过孔结构中暴露出的源电极14连接，另一方面与过孔结构暴露出的像素电极18连接，即连接结构22通过过孔结构同时与源电极14和像素电极18连接。
在一种示例性实施例中，步骤S21可以包括：
S211、在基底上沉积第一金属薄膜。
S212、在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在栅电极位置形成未曝光区域(具有第一厚度的光刻胶)，在其它位置形成完全曝光区域(无光刻胶)。
S213、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一金属薄膜，在基底上形成栅电极。
在一种示例性实施例中，基底可以采用玻璃、塑料或者柔性透明板。
在一种示例性实施例中，第一金属薄膜可以采用金属材料，如铝、铜、钼、钛、铌、银、金、钽、钨、铬等材料，也可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、掺铝氧化锌(AlZnO)等导电氧化物，可以是单层结构，也可以是多层复合结构。
在一种示例性实施例中，步骤S22可以包括：
S221、在形成有栅电极的基底上依次沉积栅绝缘薄膜、半导体薄膜和第 二金属薄膜。
S222、在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在源电极和漏电极位置形成未曝光区域(具有第一厚度的光刻胶)，在导电沟道位置形成部分曝光区域(具有第二厚度的光刻胶)，在其它位置形成完全曝光区域(无光刻胶)。其中，第一厚度大于第二厚度。
S223、通过第一次刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二金属薄膜和半导体薄膜。
S224、通过灰化工艺去除部分曝光区域的光刻胶，暴露出第二金属薄膜。
S225、通过第二次刻蚀工艺对部分曝光区域的第二金属薄膜进行刻蚀，刻蚀掉该区域的第二金属薄膜，剥离剩余的光刻胶，在基底上形成栅绝缘层、有源层、源电极和漏电极，源电极与漏电极之间形成导电沟道，源电极和漏电极的下方保留有半导体薄膜。
在一种示例性实施例中，栅绝缘薄膜可以采用采用氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(Si(ON)x)，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，第二金属薄膜可以为铝、铜、钼、铌、钛、银、金、钽、钨、铬等金属材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用射频磁控溅射方法沉积。
在一种示例性实施例中，步骤S23可以包括：
S231、在形成栅绝缘层、有源层、源电极和漏电极的基底上沉积第一钝化薄膜。
S232、在第一钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第一过孔位置形成完全曝光区域(无光刻胶)，在其它位置形成未曝光区域(保留光刻胶)。
在一种示例性实施例中，第一钝化薄膜可以为氮化硅(SiNx)、氧化硅 (SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，步骤S24可以包括：
S241、在第一钝化层上沉积有机膜薄膜。
S242、在有机膜薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第二过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶。
S243、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的有机膜薄膜，形成开设有第二过孔的有机膜层，第二过孔与第一过孔连通。
在一种示例性实施例中，有机膜薄膜可以采用聚酰亚胺、萘醌二叠氮化合物等有机材料。
在一种示例性实施例中，步骤S25可以包括：
S251、在有机膜层和第一钝化层上沉积第一透明导电薄膜。
S252、在第一透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第三过孔位置形成完全曝光区域(无光刻胶)，在其它位置形成未曝光区域，保留光刻胶。
S253、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一透明导电薄膜，形成开设有第三过孔的像素电极，像素电极的第一端深入第二过孔内，像素电极的第二端深入第二过孔内，第三过孔位于像素电极的第一端与像素电极的第二端之间，第三过孔与第一过孔连通。
在一种示例性实施例中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
在一种示例性实施例中，步骤S26可以包括：
S261、在像素电极和有机膜层上沉积第二钝化薄膜。
S262、在第二钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第四过孔位置形成完全曝光区(无光刻胶)，在其它位 置形成未曝光区域(保留光刻胶)。
S263、通过刻蚀工艺对第二钝化薄膜的完全曝光区域和第一钝化薄膜的完全曝光区域进行刻蚀，刻蚀掉该区域的第二钝化薄膜和第一钝化薄膜，形成开设有第四过孔的第二钝化层以及开设有第一过孔的第一钝化层，第二钝化层的第一端深入第三过孔内，第二钝化层的第二端深入第三过孔内，第四过孔位于第二钝化层的第一端与第二钝化层的第二端之间，第四过孔与第一过孔连通，第一过孔暴露出源电极，过孔结构可以由第一过孔、第二过孔、第三过孔和第四过孔形成，过孔结构内的第二钝化层、像素电极、有机膜层和第一钝化层被刻蚀掉，并同时暴露出源电极和像素电极。
在一种示例性实施例中，第二钝化薄膜可以为氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，步骤S27可以包括：
S271、在第二钝化层上沉积第二透明导电薄膜。
S272、在第二透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在公共电极和连接结构位置形成未曝光区域，保留光刻胶，在其它位置形成曝光区域，无光刻胶。
S273、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二透明导电薄膜，形成公共电极和连接结构；其中，公共电极为狭缝电极；连接结构设置在过孔结构所在位置，一方面与过孔结构中暴露出的源电极连接，另一方面与过孔结构暴露出的像素电极连接，即连接结构通过过孔结构同时与源电极和像素电极连接。
在一种示例性实施例中，第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
虽然前面以七次构图工艺为例，说明了本公开实施例中的阵列基板的制备过程，但实际实施时，本公开实施例中的阵列基板也可以通过其它方法制备。例如，栅电极、栅绝缘层、有源层、源电极和漏电极可以采用二次构图 工艺完成，先通过一次构图工艺形成栅电极，然后通过另一次构图工艺形成栅绝缘层、有源层、源电极和漏电极。又例如，栅绝缘层、有源层、源电极和漏电极也可以采用二次构图工艺完成，先通过一次构图工艺形成栅绝缘层和有源层，然后通过另一次构图工艺形成源电极和漏电极。又例如，公共电极和连接结构也可以采用二次构图工艺完成，先通过一次构图工艺形成公共电极，然后通过另一次构图工艺形成连接结构。
本公开实施例提供的一种阵列基板，设置贯穿第二钝化层、像素电极、有机膜层和第一钝化层的过孔结构，利用过孔结构同时暴露出源电极和像素电极，并在过孔结构所在位置设置连接结构，利用连接结构通过过孔结构同时与源电极和像素电极连接。如此，在结束有机膜层掩膜(Mask)工艺后，无需对第一钝化层进行刻蚀(Etch)工艺，从而就不会产生钻刻(Undercut)问题。接下来，也就无需对有机膜层增加灰化(Ashing)工艺来使有机膜层倒退，那么源电极中的部分金属(即位于第一钝化层上的第一过孔处的金属)就不会发生氧化腐蚀，从而，就不会产生腐蚀层。而连接结构一方面与过孔结构中暴露出的源电极连接，另一方面与过孔结构中暴露出的像素电极连接，能够保证像素电极与源电极的有效连接，提高良品率。
下面以用于连接薄膜晶体管的源电极和像素电极的连接结构设置在像素电极和源电极之间为例，对本公开提供的阵列基板进行详细说明。
图3A为本公开的另一种示例性实施例中的阵列基板的结构示意图，如图3A所示，本公开实施例提供的另一种阵列基板可以包括：
基底10；
设置在基底10上的栅电极11；
覆盖栅电极11的栅绝缘层12；
设置在栅绝缘层12上的有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道；
覆盖源电极14和漏电极15的连接结构22；
覆盖连接结构22和导电沟道的第一钝化层16，第一钝化层16上开设有暴露出连接结构22的第一过孔，在第一过孔所在位置第二连接结构与源电极连接；
覆盖第一钝化层16的有机膜层(Organic Film，ORG)17，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通形成暴露出连接结构22过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出连接结构22)；
设置在有机膜层17上的像素电极18，像素电极18在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极18所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与连接结构22连接，即连接结构22一方面与源电极14连接，另一方面通过过孔结构与像素电极18连接，即通过第二连接结构22和过孔结构，像素电极18与源电极14连接；
覆盖像素电极18和有机膜层17的第二钝化层19，第二钝化层19在第一凹槽所在位置朝向基底的方向凹陷形成第二凹槽，第二钝化层19所形成的第二凹槽设置在第一凹槽中；
设置在第二钝化层19上的公共电极20。
在一种示例性实施例中，栅电极11、有源层13、源电极14和漏电极15可以形成薄膜晶体管。
在一种示例性实施例中，第一钝化层设置在有机膜层靠近基底的一侧，用于防止有机膜层污染导电沟道。
在一种示例性实施例中，像素电极18可以为板状电极，公共电极20可以为狭缝电极，公共电极20与像素电极18一起形成多维电场驱动液晶偏转。
在一种示例性实施例中，连接结构可以采用铬钴合金、镍铬合金、碲镍铬合金等抗氧化腐蚀且导电的材料。
下面以如图3A所示的阵列基板为例，通过本公开实施例提供的另一种阵列基板的制备过程，说明本公开实施例的技术方案。
如图3A至图3D所示，本公开实施例提供的另一种阵列基板的制备方法可以包括：
S31、在基底10上形成栅电极11。
S32、形成覆盖栅电极11的栅绝缘层12，并在栅绝缘层12上形成有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道。
S33、形成覆盖源电极14和漏电极15的连接结构22。
S34、形成覆盖连接结构22和导电沟道的第一钝化层16，并形成覆盖第一钝化层16的有机膜层17，第一钝化层16上开设有暴露出连接结构22的第一过孔，在第一过孔所在位置连接结构23与源电极14连接，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通形成暴露出连接结构22的过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出连接结构22)；
S35、形成设置在有机膜层17上的像素电极18，像素电极18在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极18所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与连接结构22连接，即连接结构22一方面与源电极14连接，另一方面通过过孔结构与像素电极18连接，即连接结构22同时与源电极14和像素电极18连接。
S36、形成覆盖像素电极18的第二钝化层19，第二钝化层19在第一凹槽所在位置朝向基底的方向凹陷形成第二凹槽，第二钝化层19所形成的第二凹槽设置在第一凹槽中。
S37、形成设置在第二钝化层19上的公共电极20。
在一种示例性实施例中，步骤S31可以包括：
S311、在基底上沉积第一金属薄膜。
S312、在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在栅电极位置形成未曝光区域，具有第一厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。
S313、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一金属薄膜，在基底上形成栅电极。
在一种示例性实施例中，基底可以采用玻璃、塑料或者柔性透明板。
在一种示例性实施例中，第一金属薄膜可以采用金属材料，如铝、铜、 钼、钛、铌、银、金、钽、钨、铬等材料，也可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、掺铝氧化锌(AlZnO)等导电氧化物，可以是单层结构，也可以是多层复合结构。
在一种示例性实施例中，步骤S32可以包括：
S321、在形成有栅电极的基底上依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜。
S322、在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在源电极和漏电极位置形成未曝光区域，具有第一厚度的光刻胶，在导电沟道位置形成部分曝光区域，具有第二厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。其中，第一厚度大于第二厚度。
S323、通过第一次刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二金属薄膜和半导体薄膜。
S324、通过灰化工艺去除部分曝光区域的光刻胶，暴露出第二金属薄膜。
S325、通过第二次刻蚀工艺对部分曝光区域的第二金属薄膜进行刻蚀，刻蚀掉该区域的第二金属薄膜，剥离剩余的光刻胶，在基底上形成栅绝缘层、有源层、源电极和漏电极，源电极与漏电极之间形成导电沟道，源电极和漏电极的下方保留有半导体薄膜。
在一种示例性实施例中，栅绝缘薄膜可以采用采用氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(Si(ON)x)，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，第二金属薄膜可以为铝、铜、钼、铌、钛、银、金、钽、钨、铬等金属材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用射频磁控溅射方法沉积。
在一种示例性实施例中，步骤S33可以包括：
S331、在源电极和漏电极上沉积抗氧化的导电薄膜，在源电极和漏电极 远离基底的一侧形成连接结构。
在一种示例性实施例中，抗氧化的导电薄膜可以采用铬钴合金、镍铬合金、碲镍铬合金等抗氧化腐蚀且导电的材料，可以为单层、双层或者多层结构，可以采用射频磁控溅射方法沉积。
在一种示例性实施例中，如图3B至3D所示，步骤S34可以包括：
S341、在形成有栅绝缘层、有源层、源电极、漏电极和连接结构22的基底上沉积第一钝化薄膜；
S342、在第一钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在连接结构位置形成完全曝光区域(无光刻胶)，在其它位置形成未曝光区域(保留光刻胶)；
S343、在第一钝化薄膜上沉积有机膜薄膜；
S344、在有机膜薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在第二过孔位置形成部分曝光区域(具有第二厚度的光刻胶)和完全曝光区域(无光刻胶)，在其它位置形成未曝光区域(具有第一厚度的光刻胶，第一厚度大于第二厚度)；
S345、通过刻蚀工艺对有机膜薄膜的完全曝光区域进行刻蚀，刻蚀掉该区域的有机膜薄膜，如图3C所示，形成开设有待处理的第二过孔的有机膜层17；
S346、通过刻蚀工艺对第一钝化薄膜的完全曝光区域进行刻蚀，刻蚀掉该区域的第一钝化薄膜，形成开设有第一过孔的第一钝化层16，第一过孔暴露出连接结构22，在第一过孔所在位置连接结构22与源电极14连接；
S347、通过灰化工艺去除有机膜薄膜的部分曝光区域的光刻胶，以使有机膜薄膜倒退，如图3D所示，形成开设有第二过孔的有机膜层17，第二过孔与第一过孔连通形成暴露出连接结构22的过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出连接结构22)。
在一种示例性实施例中，第一钝化薄膜可以为氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单 层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，有机膜薄膜可以采用聚酰亚胺、萘醌二叠氮化合物等有机材料。
在一种示例性实施例中，步骤S35可以包括：
S351、在有机膜层和连接结构上沉积第一透明导电薄膜；
S352、在第一透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在像素电极位置形成完全曝光区域(无光刻胶)，在其它位置形成未曝光区域(保留光刻胶)；
S353、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一透明导电薄膜，形成像素电极，像素电极18在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极18所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与连接结构22连接，即连接结构22一方面与源电极14连接，另一方面通过过孔结构与像素电极18连接，即连接结构22同时与源电极14和像素电极18连接。
在一种示例性实施例中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
在一种示例性实施例中，步骤S36可以包括：
S361、在像素电极和有机膜层上沉积第二钝化薄膜。
在一种示例性实施例中，第二钝化薄膜可以为氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，步骤S37可以包括：
S371、在第二钝化层上沉积第二透明导电薄膜；
S372、在第二透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在公共电极位置形成未曝光区域(保留光刻胶)，在 其它位置形成完全曝光区域(无光刻胶)；
S373、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二透明导电薄膜，形成公共电极；其中，公共电极可以为狭缝电极。
在一种示例性实施例中，第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
当然，在实际实施时，本公开实施例中提供的另一种阵列基板也可以通过其它方法制备。例如，栅电极、栅绝缘层、有源层、源电极和漏电极可以采用二次构图工艺完成，先通过一次构图工艺形成栅电极，然后通过另一次构图工艺形成栅绝缘层、有源层、源电极和漏电极。又例如，栅绝缘层、有源层、源电极和漏电极也可以采用二次构图工艺完成，先通过一次构图工艺形成栅绝缘层和有源层，然后通过另一次构图工艺形成源电极和漏电极。
本公开实施例提供的另一种阵列基板，设置贯穿有机膜层和第一钝化层，并暴露出连接结构的过孔结构，并在源电极与像素电极之间设置能够抗氧化且导电的连接结构，利用连接结构一方面与源电极连接，另一方面通过过孔结构与像素电极连接，即通过连接结构和过孔结构，像素电极与源电极连接，如此，虽然在结束有机膜层掩膜(Mask)工艺后，对第一钝化层进行刻蚀(Etch)工艺，会产生钻刻(Undercut)问题，但是接下来，通过对有机膜层增加灰化(Ashing)工艺来使有机膜层倒退，而且由于连接结构能够抗氧化且导电，并且连接结构覆盖源电极，因此，连接结构能够保护源电极中的金属不会发生氧化腐蚀，从而，也就不会产生腐蚀层。而且连接结构一方面与源电极连接，另一方面通过过孔结构与像素电极连接，能够保证像素电极与源电极的有效连接，提高良品率。
下面以像素电极和源电极直接连接为例，对本公开提供的阵列基板进行详细说明。
图4A为本公开的又一种示例性实施例中的阵列基板的结构示意图，如图4A所示，本公开实施例提供的另一种阵列基板可以包括：
基底10；
设置在基底10上的栅电极11；
覆盖栅电极11的栅绝缘层12；
设置在栅绝缘层12上的有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道；
覆盖源电极14、漏电极15和导电沟道的第一钝化层16，第一钝化层16上开设有暴露出源电极14的第一过孔；
覆盖第一钝化层16的有机膜层17，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通形成暴露出源电极14的过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出源电极14)，有机膜层17靠近源电极14的两侧伸入第一过孔内；
设置在有机膜层17上的像素电极18，像素电极18在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极18所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与源电极14连接，即像素电极18通过过孔结构与源电极14连接；
覆盖像素电极18和有机膜层17的第二钝化层19，第二钝化层19在第一凹槽所在位置朝向基底的方向凹陷形成第二凹槽，第二钝化层19所形成的第二凹槽设置在第一凹槽中；
设置在第二钝化层19上的公共电极20。
在一种示例性实施例中，如图4A所示，栅电极11、有源层13、源电极14和漏电极15可以形成薄膜晶体管。
在一种示例性实施例中，如图4A所示，像素电极18可以为板状电极，公共电极20可以为狭缝电极，公共电极20与像素电极18一起形成多维电场驱动液晶偏转。
在一种示例性实施例中，连接结构可以采用铬钴合金、镍铬合金、碲镍铬合金等抗氧化腐蚀且导电的材料。
下面以如图4A所示的阵列基板为例，通过本公开实施例提供的一种阵列基板的制备过程，说明本公开实施例的技术方案。
如图4A至图4D所示，本公开实施例提供的又一种阵列基板的制备方法可以包括：
S41、在基底10上形成栅电极11；
S42、形成覆盖栅电极11的栅绝缘层12，并在栅绝缘层12上形成有源层13、源电极14和漏电极15，源电极14与漏电极15之间形成导电沟道；
S43、形成覆盖源电极14、漏电极15和导电沟道的第一钝化层16，第一钝化层16上开设有暴露出源电极14的第一过孔；
S44、形成覆盖第一钝化层16的有机膜层17，有机膜层17上开设有第二过孔，第二过孔与第一过孔连通形成暴露出源电极14的过孔结构(即过孔结构贯穿有机膜层17和第一钝化层16，并暴露出源电极14)，有机膜层17靠近源电极14的两侧伸入第一过孔内；
S45、形成设置在有机膜层17上的像素电极18，像素电极18在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极18所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与源电极14连接，即像素电极18通过过孔结构与源电极14连接；
S46、形成覆盖像素电极18和有机膜层17的第二钝化层19，第二钝化层19在第一凹槽所在位置朝向基底的方向凹陷形成第二凹槽，第二钝化层19所形成的第二凹槽设置在第一凹槽中；
S47、形成设置在第二钝化层19上的公共电极20。
在一种示例性实施例中，步骤S41可以包括：
S411、在基底上沉积第一金属薄膜。
S412、在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在栅电极位置形成未曝光区域，具有第一厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。
S413、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一金属薄膜，在基底上形成栅电极。
在一种示例性实施例中，基底可以采用玻璃、塑料或者柔性透明板。
在一种示例性实施例中，第一金属薄膜可以采用金属材料，如铝、铜、钼、钛、铌、银、金、钽、钨、铬等材料，也可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、掺铝氧化锌(AlZnO)等导电氧化物，可以是单层结构，也可以是多层复合结构。
在一种示例性实施例中，步骤S42可以包括：
S421、在形成有栅电极的基底上依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜。
S422、在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在源电极和漏电极位置形成未曝光区域，具有第一厚度的光刻胶，在导电沟道位置形成部分曝光区域，具有第二厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。其中，第一厚度大于第二厚度。
S423、通过第一次刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二金属薄膜和半导体薄膜。
S424、通过灰化工艺去除部分曝光区域的光刻胶，暴露出第二金属薄膜。
S425、通过第二次刻蚀工艺对部分曝光区域的第二金属薄膜进行刻蚀，刻蚀掉该区域的第二金属薄膜，剥离剩余的光刻胶，在基底上形成栅绝缘层、有源层、源电极和漏电极，源电极与漏电极之间形成导电沟道，源电极和漏电极的下方保留有半导体薄膜。
在一种示例性实施例中，栅绝缘薄膜可以采用采用氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(Si(ON)x)，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，第二金属薄膜可以为铝、铜、钼、铌、钛、银、金、钽、钨、铬等金属材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用射频磁控溅射方法沉积。
在一种示例性实施例中，如图4B至图4D所示，步骤S43可以包括：
S431、如图4B所示，在源电极14、漏电极和导电沟道上沉积第一钝化薄膜；
S432、在第一钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第一过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶；
S433、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一钝化薄膜，如图4C所示，形成开设有第一过孔的第一钝化层16，第一过孔暴露出源电极。
在一种示例性实施例中，第一钝化薄膜可以为氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，步骤S44可以包括：
S441、在第一钝化层上沉积有机膜薄膜；
S442、在有机膜薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第二过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶；
S443、通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的有机膜薄膜，形成开设有第二过孔的有机膜层，第二过孔与第一过孔连通形成暴露出源电极的过孔结构(即过孔结构贯穿有机膜层和第一钝化层，并暴露出源电极)，有机膜层靠近源电极的两侧伸入第一过孔内。
在一种示例性实施例中，有机膜薄膜可以采用聚酰亚胺、萘醌二叠氮化合物等有机材料。
在一种示例性实施例中，步骤S45可以包括：
S451、在有机膜层上沉积第一透明导电薄膜；
S452、在第一透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在像素电极位置形成曝光区域，无光刻胶，在其它位 置形成未曝光区域，保留光刻胶；
S453、通过刻蚀工艺对曝光区域进行刻蚀，刻蚀掉该区域的第一透明导电薄膜，形成像素电极，像素电极在过孔结构所在位置朝向基底的方向凹陷形成第一凹槽，像素电极所形成的第一凹槽设置在过孔结构中，第一凹槽的槽底与源电极连接，即像素电极通过过孔结构与源电极连接。
在一种示例性实施例中，第一透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
在一种示例性实施例中，步骤S46可以包括：
S461、在像素电极和有机膜层上沉积第二钝化薄膜，形成覆盖像素电极和有机膜层的第二钝化层，第二钝化层在第一凹槽所在位置朝向基底的方向凹陷形成第二凹槽，第二钝化层所形成的第二凹槽设置在第一凹槽中。
在一种示例性实施例中，第二钝化薄膜可以为氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅(Si(ON)x)等无机材料中的一种或多种混合，可以为单层、双层或者多层结构，可以采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
在一种示例性实施例中，步骤S47可以包括：
S471、在第二钝化层上沉积第二透明导电薄膜；
S472、在第二透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在公共电极位置形成未曝光区域，保留光刻胶，在其它位置形成曝光区域，无光刻胶；
S383、通过刻蚀工艺对曝光区域进行刻蚀，刻蚀掉该区域的第二透明导电薄膜，形成公共电极；其中，公共电极为狭缝电极。
在一种示例性实施例中，第二透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，可以采用射频磁控溅射(Sputter)方法沉积。
当然，在实际实施时，本公开实施例中提供的又一种阵列基板也可以通过其它方法制备。例如，栅电极、栅绝缘层、有源层、源电极和漏电极可以采用二次构图工艺完成，先通过一次构图工艺形成栅电极，然后通过另一次 构图工艺形成栅绝缘层、有源层、源电极和漏电极。又例如，栅绝缘层、有源层、源电极和漏电极也可以采用二次构图工艺完成，先通过一次构图工艺形成栅绝缘层和有源层，然后通过另一次构图工艺形成源电极和漏电极。
本公开实施例提供的又一种阵列基板，在制备阵列基板的过程中，通过先进行第一钝化层刻蚀工艺，后进行有机膜层掩膜(Mask)工艺，那么，就不会产生钻刻(Undercut)问题，从而，就无需对有机膜层增加光刻胶灰化(Ashing)工艺来使有机膜层倒退，进而，也就不会出现源电极中的部分金属发生氧化腐蚀的问题。这样，一方面，通过贯穿有机膜层和第一钝化层，并暴露出源电极的过孔结构，就能够实现像素电极与源电极的有效连接，提高良品率。另一方面，与目前的阵列基板的制备方法相比，本公开实施例提供的又一种阵列基板的制备过程还可以节省一道灰化工艺，降低生产成本，提高生产效率。
基于前述实施例，以用于连接薄膜晶体管的源电极和像素电极的连接结构设置在暴露出像素电极和源电极的过孔结构之中为例，本公开实施例还提供了一种阵列基板的制备方法，该方法可以包括：
S51：形成基底，在基底上形成薄膜晶体管；
S52：形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出像素电极和薄膜晶体管的源电极的过孔结构，并在暴露出像素电极和薄膜晶体管的源电极的过孔结构之中形成用于连接源电极和像素电极的连接结构。
在一种示例性实施例中，步骤S52可以包括：
S521：形成覆盖薄膜晶体管的第一钝化层；
S522：形成覆盖第一钝化层的有机膜层，有机膜层上开设有第二过孔；
S523：形成设置在有机膜层上的像素电极，像素电极上开设有第三过孔，第三过孔与第二过孔连通；
S524：形成设置在像素电极上的第二钝化层；
S525：通过一次刻蚀工艺，形成位于第二钝化层上的暴露出像素电极的第四过孔以及位于第一钝化层上的暴露出源电极的第一过孔，第四过孔与第一过孔连通，第一过孔与第二过孔连通，第一过孔、第二过孔、第三过孔和第四过孔形成暴露出像素电极和薄膜晶体管的源电极的过孔结构；
S526：在暴露出像素电极和薄膜晶体管的源电极的过孔结构之中形成用于连接源电极和像素电极的连接结构。
在一种示例性实施例中，步骤S525可以包括：
S5251：通过一次构图工艺，在第二钝化层上形成公共电极，并在暴露出像素电极和薄膜晶体管的源电极的过孔结构之中形成用于连接源电极和像素电极的连接结构。
基于前述实施例，以用于连接薄膜晶体管的源电极和像素电极的连接结构设置在像素电极和源电极之间为例，本公开实施例还提供了一种阵列基板的制备方法，该方法可以包括：
S61：形成基底，在基底上形成薄膜晶体管；
S62：形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并在像素电极和源电极之间形成用于连接源电极和像素电极的连接结构。
在一种示例性实施例中，步骤S62可以包括：
S621：形成覆盖源电极和薄膜晶体管的漏电极的连接结构；
S622：形成覆盖连接结构的第一钝化层，并形成覆盖第一钝化层的有机膜层，有机膜层上开设有第二过孔，第一钝化层上开设有与第二过孔连通并暴露出连接结构的第一过孔，第二过孔与第一过孔形成暴露出连接结构的过孔结构，连接结构与源电极连接；
S623：形成设置在有机膜层上的像素电极，像素电极通过过孔结构与连接结构连接；
S624：形成覆盖像素电极的第二钝化层。
在一种示例性实施例中，步骤S622可以包括：
S6221：在连接结构上沉积第一钝化薄膜；
S6222：在第一钝化薄膜上涂覆一层光刻胶，采用调掩膜版对光刻胶进行曝光并显影，在连接结构位置形成曝光区域，在其它位置形成未曝光区域；
S6223：在涂覆有光刻胶的第一钝化薄膜上沉积有机膜薄膜；
S6224：在有机膜薄膜上涂覆一层光刻胶，采用掩膜版对光刻胶进行曝光并显影，在第二过孔位置形成部分曝光区域和完全曝光区域，在其它位置形成未曝光区域；
S6225：通过刻蚀工艺刻蚀掉有机膜薄膜的完全曝光区域；
S6226：通过刻蚀工艺对第一钝化薄膜的完全曝光区域进行刻蚀，形成开设有第一过孔的第一钝化层；
S6227：通过灰化工艺去除有机膜薄膜的部分曝光区域的光刻胶，形成开设有第二过孔的有机膜层。
基于前述实施例，以像素电极和源电极直接连接为例，本公开实施例还提供了一种阵列基板的制备方法，该方法可以包括：
S71：形成基底，在基底上形成薄膜晶体管；
S72：形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出源电极的过孔结构，像素电极通过暴露出源电极的过孔结构与源电极连接。
在一种示例性实施例中，步骤S72可以包括：
S721：形成覆盖薄膜晶体管的第一钝化层，第一钝化层上开设有暴露出源电极的第一过孔；
S722：形成覆盖第一钝化层的有机膜层，有机膜层上开设有第二过孔，第二过孔与第一过孔连通形成暴露出源电极的过孔结构；
S723：形成设置在有机膜层上的像素电极，像素电极通过暴露出源电极 的过孔结构与源电极连接；
S724：形成覆盖像素电极和有机膜层的第二钝化层。
本公开实施例还提供了一种显示装置，包括前述实施例的阵列基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种阵列基板，包括：
    基底；
    设置在基底上的薄膜晶体管；
    设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极；
    用于连接所述薄膜晶体管的源电极和所述像素电极的连接结构，其中，所述连接结构设置在暴露出所述像素电极和所述源电极的过孔结构之中，或者，所述连接结构设置在所述像素电极和所述源电极之间。
  2. 根据权利要求1所述的阵列基板，还包括：设置在所述像素电极远离所述基底的一侧的第二钝化层；
    所述连接结构设置在暴露出所述像素电极和所述源电极的过孔结构之中，包括：所述第一钝化层上开设有暴露出所述源电极的第一过孔；所述有机膜层上开设有与所述第一过孔连通的第二过孔；所述像素电极上开设有与所述第二过孔连通的第三过孔；所述第二钝化层上开设有与所述第三过孔连通并暴露出所述像素电极的第四过孔；所述第四过孔、所述第三过孔、所述第二过孔和所述第一过孔形成暴露出所述像素电极和所述源电极的过孔结构；所述连接结构通过所述过孔结构与所述像素电极连接，并与所述源电极连接。
  3. 根据权利要求1所述的阵列基板，还包括：设置在所述像素电极远离所述基底的一侧的第二钝化层和设置在所述第二钝化层远离所述基底的一侧上的公共电极；其中，所述连接结构与所述公共电极同层同材料设置。
  4. 根据权利要求3所述的阵列基板，其中，所述连接结构的材料包括氧化铟锡或者氧化铟锌。
  5. 根据权利要求1所述的阵列基板，其中，所述连接结构设置在所述像素电极和所述源电极之间，包括：
    所述连接结构设置在所述源电极远离所述基底的一侧；所述第一钝化层设置在所述连接结构远离所述基底的一侧，并开设有暴露出所述连接结构的第一过孔；所述有机膜层上开设有与所述第一过孔连通的第二过孔；所述第二过孔与所述第一过孔形成暴露出所述连接结构的过孔结构；所述像素电极 通过所述过孔结构与所述连接结构连接，所述连接结构与所述源电极连接。
  6. 根据权利要求1或5所述的阵列基板，其中，所述连接结构的材料为抗氧化腐蚀且导电的材料。
  7. 根据权利要求6所述的阵列基板，其中，所述抗氧化腐蚀且导电的材料包括铬钴合金、镍铬合金和碲镍铬合金中的任意一种。
  8. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管包括栅电极、有源层、所述源电极和漏电极，所述栅电极设置在所述基底上，所述栅电极上覆盖有栅绝缘层，所述有源层、所述源电极和所述漏电极设置在所述栅绝缘层上，所述源电极与漏电极之间形成导电沟道。
  9. 一种显示装置，包括：如权利要求1至8任一项所述的阵列基板。
  10. 一种阵列基板的制备方法，包括：
    形成基底，在所述基底上形成薄膜晶体管；
    形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构，并在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构；或者，形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并在所述像素电极和所述源电极之间形成用于连接所述源电极和所述像素电极的连接结构；或者，形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述源电极的过孔结构，所述像素电极通过所述暴露出所述源电极的过孔结构与所述源电极连接。
  11. 根据权利要求10所述的制备方法，其中，所述形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构，并在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构，包括：
    形成覆盖所述薄膜晶体管的所述第一钝化层；
    形成覆盖所述第一钝化层的所述有机膜层，所述有机膜层上开设有第二 过孔；
    形成设置在所述有机膜层上的所述像素电极，所述像素电极上开设有第三过孔，所述第三过孔与所述第二过孔连通；
    形成设置在所述像素电极上的第二钝化层；
    通过一次刻蚀工艺，形成位于所述第二钝化层上的暴露出所述像素电极的第四过孔以及位于所述第一钝化层上的暴露出所述源电极的第一过孔，所述第四过孔与所述第一过孔连通，所述第一过孔与所述第二过孔连通，所述第一过孔、所述第二过孔、所述第三过孔和所述第四过孔形成所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构；
    在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构。
  12. 根据权利要求11所述的制备方法，其中，所述在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构，包括：
    通过一次构图工艺，在所述第二钝化层上形成公共电极，并在所述暴露出所述像素电极和所述薄膜晶体管的源电极的过孔结构之中形成用于连接所述源电极和所述像素电极的连接结构。
  13. 根据权利要求10所述的制备方法，其中，所述形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并在所述像素电极和所述源电极之间形成用于连接所述源电极和所述像素电极的连接结构，包括：
    形成覆盖所述源电极和所述薄膜晶体管的漏电极的所述连接结构；
    形成覆盖所述连接结构的所述第一钝化层，并形成覆盖所述第一钝化层的所述有机膜层，所述有机膜层上开设有第二过孔，所述第一钝化层上开设有与所述第二过孔连通并暴露出所述连接结构的第一过孔，所述第二过孔与所述第一过孔形成暴露出所述连接结构的过孔结构，所述连接结构与所述源电极连接；
    形成设置在所述有机膜层上的所述像素电极，所述像素电极通过所述过孔结构与所述连接结构连接；
    形成覆盖所述像素电极的第二钝化层。
  14. 根据权利要求13所述的制备方法，其中，所述形成覆盖所述连接结构的所述第一钝化层，并形成覆盖所述第一钝化层的所述有机膜层，所述有机膜层上开设有第二过孔，所述第一钝化层上开设有与所述第二过孔连通并暴露出所述连接结构的第一过孔，包括：
    在所述连接结构上沉积第一钝化薄膜；
    在所述第一钝化薄膜上涂覆一层光刻胶，采用调掩膜版对光刻胶进行曝光并显影，在所述连接结构位置形成曝光区域，在其它位置形成未曝光区域；
    在所述涂覆有光刻胶的所述第一钝化薄膜上沉积有机膜薄膜；
    在有机膜薄膜上涂覆一层光刻胶，采用掩膜版对光刻胶进行曝光并显影，在所述第二过孔位置形成部分曝光区域和完全曝光区域，在其它位置形成未曝光区域；
    通过刻蚀工艺刻蚀掉所述有机膜薄膜的完全曝光区域；
    通过刻蚀工艺对第一钝化薄膜的完全曝光区域进行刻蚀，形成开设有所述第一过孔的第一钝化层；
    通过灰化工艺去除有机膜薄膜的部分曝光区域的光刻胶，形成开设有第二过孔的有机膜层。
  15. 根据权利要求10所述的制备方法，其中，所述形成设置在薄膜晶体管上的第一钝化层、有机膜层和像素电极，并形成暴露出所述源电极的过孔结构，所述像素电极通过所述暴露出所述源电极的过孔结构与所述源电极连接，包括：
    形成覆盖所述薄膜晶体管的所述第一钝化层，所述第一钝化层上开设有暴露出所述源电极的第一过孔；
    形成覆盖所述第一钝化层的所述有机膜层，所述有机膜层上开设有第二过孔，所述第二过孔与所述第一过孔连通形成暴露出所述源电极的过孔结构；
    形成设置在所述有机膜层上的像素电极，所述像素电极通过所述暴露出所述源电极的过孔结构与所述源电极连接；
    形成覆盖所述像素电极和所述有机膜层的第二钝化层。
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