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WO2020147495A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2020147495A1
WO2020147495A1 PCT/CN2019/126280 CN2019126280W WO2020147495A1 WO 2020147495 A1 WO2020147495 A1 WO 2020147495A1 CN 2019126280 W CN2019126280 W CN 2019126280W WO 2020147495 A1 WO2020147495 A1 WO 2020147495A1
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WIPO (PCT)
Prior art keywords
electrode
substrate
drain electrode
photoresist
gate
Prior art date
Application number
PCT/CN2019/126280
Other languages
English (en)
French (fr)
Inventor
王小元
王武
方琰
吴胜学
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/767,237 priority Critical patent/US11573467B2/en
Priority to JP2020564585A priority patent/JP7461302B2/ja
Priority to EP19910539.6A priority patent/EP3913427B1/en
Priority to EP23215698.4A priority patent/EP4312265A3/en
Publication of WO2020147495A1 publication Critical patent/WO2020147495A1/zh
Priority to US18/092,581 priority patent/US11914253B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to an array substrate, a preparation method thereof, and a display panel.
  • LCD Liquid Crystal Display
  • TFT thin film transistor array
  • CF color filter
  • LCD liquid crystal
  • the common electrode and the pixel electrode are controlled to form an electric field that drives the deflection of the liquid crystal to achieve gray scale display.
  • LCD can be divided into: Twisted Nematic (TN) display mode, In Plane Switching (IPS) display mode and Advanced Super Dimension Switch (ADS) display mode, etc.
  • TN Twisted Nematic
  • IPS In Plane Switching
  • ADS Advanced Super Dimension Switch
  • the ADS display mode has become a relatively mature display mode, which has the advantages of wide viewing angle, high aperture ratio, high transmittance, high resolution, fast response speed, low power consumption, and low color difference.
  • the prior art has proposed the IADS (Interchange Advanced Super Dimension Switch) display mode.
  • IADS Interchange Advanced Super Dimension Switch
  • the dual-gate pixel architecture can reduce the number of source driver integrated circuits and reduce costs. Therefore, the IADS display mode has gradually been widely used.
  • the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display panel, which can increase the aperture ratio and improve the yield rate.
  • an array substrate including:
  • Pixel electrodes and thin film transistors arranged on the substrate are Pixel electrodes and thin film transistors arranged on the substrate;
  • a passivation layer covering the thin film transistor and the pixel electrode, the passivation layer is provided with a via hole that simultaneously exposes the pixel electrode and the drain electrode or the source electrode of the thin film transistor;
  • connection electrode disposed on the passivation layer and at the connection via, the connection electrode is connected to the pixel electrode through the via via, and is connected to the drain electrode or the source electrode.
  • the orthographic projection of the connection via on the substrate overlaps the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the drain electrode or the source electrode on the substrate.
  • the array substrate according to the embodiment of the present disclosure further includes a gate line and a data line
  • the thin film transistor includes a gate electrode, an active layer, a source electrode and a drain electrode
  • the pixel electrode, the gate line and the gate electrode are arranged in On the substrate, the pixel electrode, the gate line and the gate electrode are covered with a gate insulating layer, the active layer, source electrode, drain electrode and data line are arranged on the gate insulating layer, so A conductive channel is formed between the source electrode and the drain electrode.
  • the connecting electrode is provided with a first compensation block on the side adjacent to the gate line, and the orthographic projection of the first compensation block on the substrate includes the side of the drain electrode or the source electrode adjacent to the gate line. At least a part of the orthographic projection of the edge on the substrate, and/or a second compensation block is provided on the side of the connecting electrode away from the gate line, and the orthographic projection of the second compensation block on the substrate includes the drain electrode or the source electrode away from the gate. At least part of the orthographic projection of the edge on one side of the line on the substrate.
  • the first compensation block extends from the main body of the connection electrode toward the gate line
  • the second compensation block extends from the main body of the connection electrode in a direction away from the gate line.
  • the size of a compensation block and the second compensation block in a direction parallel to the grid line is smaller than the size of the main body.
  • the orthographic projection of the connecting electrode on the substrate covers the orthographic projection of the drain electrode or the overlapping area between the source electrode and the pixel electrode on the substrate.
  • the shape of the first compensation block and/or the second compensation block includes a rectangle, a trapezoid, a semicircle or a semiellipse.
  • the via via includes a first via portion and a second via portion, the first via portion exposing the drain electrode, and the second via portion exposing the pixel electrode .
  • embodiments of the present disclosure also provide a display panel including the above-mentioned array substrate.
  • embodiments of the present disclosure also provide a method for manufacturing an array substrate, including:
  • the passivation layer is provided with a via hole that simultaneously exposes the pixel electrode and the drain electrode or the source electrode of the thin film transistor;
  • connection electrode is formed on the passivation layer and at the connection via, and the connection electrode is simultaneously connected to the pixel electrode and the drain electrode or the source electrode through the via via.
  • forming a pixel electrode and a thin film transistor on the substrate includes:
  • a gate insulating layer, an active layer, a source electrode, a drain electrode, and a data line are formed through one patterning process, and a conductive channel is formed between the source electrode and the drain electrode.
  • the connecting electrode is provided with a first compensation block on the side adjacent to the gate line
  • the orthographic projection of the first compensation block on the substrate includes the side of the drain electrode or the source electrode adjacent to the gate line.
  • At least a part of the orthographic projection of the edge on the substrate, and/or a second compensation block is provided on the side of the connecting electrode away from the gate line, and the orthographic projection of the second compensation block on the substrate includes the drain electrode or the source electrode away from the gate line At least part of the orthographic projection of the edge on one side on the substrate.
  • the first compensation block extends from the main body of the connection electrode toward the gate line
  • the second compensation block extends from the main body of the connection electrode in a direction away from the gate line.
  • the size of a compensation block and the second compensation block in a direction parallel to the grid line is smaller than the size of the main body.
  • the via via includes a first via portion and a second via portion, the first via portion exposing the drain electrode, and the second via portion exposing the pixel electrode .
  • the forming the pixel electrode, the gate line and the gate electrode through a single patterning process includes: sequentially depositing a first transparent conductive film and a first metal film on the substrate; and coating a layer of light on the first metal film.
  • the resist is stepwise exposed and developed using a halftone or gray tone mask, and an unexposed area is formed where the gate lines and gate electrodes are to be formed.
  • the photoresist with the first thickness is The position of the pixel electrode to be formed forms a partially exposed area with a second thickness of photoresist, and forms a fully exposed area at other positions without photoresist, and the first thickness is greater than the second thickness; through the first etching The process etches away the first metal film and the first transparent conductive film in the fully exposed area; removes the photoresist in the partially exposed area through an ashing process to expose the first metal film; and The second etching process etches away the first metal film in the partially exposed area, strips off the remaining photoresist, and forms the pixel electrode, the gate line and the gate electrode on the substrate.
  • the forming a gate insulating layer, an active layer, a source electrode, a drain electrode, and a data line through a single patterning process, and forming a conductive channel between the source electrode and the drain electrode includes: forming the pixel electrode , The gate line and the gate electrode substrate are sequentially deposited gate insulating film, semiconductor film and second metal film; a layer of photoresist is coated on the second metal film, and a halftone or gray tone mask is used for the photoresist Step exposure and development are performed, unexposed areas are formed at the positions where the source electrode, the drain electrode and the data line are to be formed, the photoresist with the first thickness is formed, and a partially exposed area is formed at the position where the conductive channel is to be formed, with the first Two-thickness photoresist, forming a fully exposed area at other locations, no photoresist, the first thickness is greater than the second thickness; the second metal film and the fully exposed area are etched away by the first etching process
  • the forming a passivation layer covering the thin film transistor, the passivation layer being provided with a via hole that simultaneously exposes the pixel electrode and the drain electrode or the source electrode of the thin film transistor includes: A passivation film is deposited on the substrate of the thin film transistor and the pixel electrode; a layer of photoresist is coated on the passivation film, and the photoresist is exposed and developed by using a single-tone mask, and in the via hole position Form the exposed area without photoresist, and form the unexposed area at other locations, leaving the photoresist; the passivation film and the gate insulating layer in the fully exposed area are etched by an etching process to form a passivation with via holes
  • the drain electrode and the pixel electrode are exposed simultaneously through the via via, the via via includes a first via portion and a second via portion, and the passivation layer in the first via portion is etched
  • the drain electrode is exposed, and the passivation layer and the gate insulating layer in the second via hole portion are
  • FIG. 1 is a schematic diagram of the structure of an ADS display mode array substrate
  • Figure 2 is a cross-sectional view along the A-A direction in Figure 1;
  • FIG. 3 is a schematic diagram of the structure of an IADS display mode array substrate
  • Figure 4 is a cross-sectional view along the A-A direction in Figure 3;
  • FIG. 5 is a schematic diagram of the structure of the first embodiment of the disclosed array substrate
  • Figure 6 is a cross-sectional view along the A-A direction in Figure 5;
  • FIG. 7 is a schematic diagram of the pixel electrode, gate line and gate electrode pattern formed in the first embodiment of the disclosure.
  • Fig. 8 is a sectional view taken along the line A-A in Fig. 7;
  • FIG. 9 is a schematic diagram of the first embodiment of the present disclosure after the active layer, the source electrode, the drain electrode and the data line pattern are formed;
  • Fig. 10 is a sectional view taken along the line A-A in Fig. 9;
  • FIG. 11 is a schematic diagram of the first embodiment of the disclosure after forming a via pattern
  • Figure 12 is a cross-sectional view along the A-A direction in Figure 11;
  • FIG. 13 is a schematic diagram of the structure of the via hole in the embodiment of the disclosure.
  • FIG. 15 is a schematic structural diagram of the third embodiment of the disclosed array substrate.
  • 60A first compensation block
  • 60B second compensation block
  • 11 gate electrode
  • a display panel of an IADS display mode has the defects of a small aperture ratio and a low yield rate.
  • FIG. 1 is a schematic diagram of the structure of an ADS display mode array substrate
  • FIG. 2 is a cross-sectional view along the A-A direction in FIG. 1.
  • the structural feature of the array substrate shown in the ADS display mode is that the common electrode is set on the base and is a plate electrode, and the pixel electrode is set on the passivation layer and is a slit electrode.
  • the film structure of the array substrate includes: Electrodes, gate lines, gate electrodes and common electrode leads, gate insulating layer (GI), active layer (Active), source electrode, drain electrode and data line, passivation layer (PVX), pixel electrode.
  • GI gate insulating layer
  • Active active layer
  • PVX passivation layer
  • the array substrate When a turn-on voltage is applied to the gate line, the data signal of the data line is written to the drain electrode through the thin film transistor, and is transferred to the pixel electrode through the single hole to complete the signal writing.
  • the array substrate includes a base 10, a common electrode 20, a gate line 30, and a gate electrode 11 disposed on the base, and a gate insulating layer 12 covering the common electrode 20, the gate line 30 and the gate electrode 11.
  • the active layer 13, the source electrode 14, the drain electrode 15 and the data line 40 are arranged on the gate insulating layer 12.
  • a conductive channel is formed between the source electrode 14 and the drain electrode 15, covering the source electrode 14, the drain electrode 15, and the data line 40 and the passivation layer 16 of the conductive channel, on which a via hole exposing the drain electrode 15 is opened, the pixel electrode 50 is arranged on the passivation layer 16, and the pixel electrode 50 passes through the via hole on the passivation layer 16 and leaks electricity Pole 15 connection.
  • the common electrode 20 is used to provide a common voltage
  • the pixel electrode 50 is used to provide a pixel voltage for display
  • the multidimensional electric field generated between the slit electrode and the plate electrode drives the liquid crystal to deflect.
  • FIG. 3 is a schematic diagram of a structure of an IADS display mode array substrate
  • FIG. 4 is a cross-sectional view along the A-A direction in FIG. 3.
  • This IADS display mode is based on the ADS display mode.
  • the positions of the common electrode and the pixel electrode are interchanged.
  • the structural feature of the array substrate is that the pixel electrode is arranged on the substrate, which is a plate electrode, and the common electrode is arranged on the passivation layer. Above is the slit electrode.
  • the film structure of the array substrate includes: substrate, pixel electrode, gate line and gate electrode, gate insulating layer, active layer, source electrode, drain electrode, data line and common electrode lead, passivation layer , Common electrode and connection electrode.
  • the array substrate includes a substrate 10, a pixel electrode 50, a gate line 30, and a gate electrode 11 disposed on the substrate, a gate insulating layer 12 covering the pixel electrode 50, the gate line 30 and the gate electrode 11, and A conductive channel is formed between the active layer 13, the source electrode 14, the drain electrode 15 and the data line 40 on the gate insulating layer 12, and the source electrode 14 and the drain electrode 15 cover the source electrode 14, the drain electrode 15, and the data line 40
  • the passivation layer 16 of the conductive channel the first via hole exposing the drain electrode 15 and the second via hole exposing the pixel electrode 50 are opened thereon, the common electrode 20 and the connecting electrode are arranged on the passivation layer 16 60.
  • the connecting electrode 60 is connected to the drain electrode 15 through the first via on the one hand, and connected
  • the inventor of the present application found that the above IADS display mode display panel has a small aperture ratio and a low yield rate, which is largely caused by the dual-hole structure. Specifically, the size, shape, and number of vias have a greater impact on the aperture ratio and yield. For high-resolution products, the impact is more important.
  • the double-hole structure of the IADS display mode requires a larger The structural space reduces the area of the pixel electrode correspondingly, so the aperture ratio of the IADS display mode display panel is relatively small.
  • the width of the signal line can be adjusted to increase the area of the pixel electrode as much as possible, this method will seriously affect the charging rate of the pixel electrode.
  • the display panel will show macroscopic spots similar to stains (Mura), which are called panel stains or panel stains in the industry, which affect product quality. Reduce the yield rate.
  • the embodiments of the present disclosure provide an array substrate, which can improve the aperture ratio and the yield rate.
  • the array substrate of the embodiment of the present disclosure includes a substrate, a pixel electrode and a thin film transistor disposed on the substrate, and a passivation layer covering the thin film transistor and the thin film transistor.
  • the passivation layer is provided with a pixel electrode and a thin film at the same time.
  • the drain electrode or the source electrode of the transistor is connected to the through hole of the drain electrode or the source electrode, and the connecting electrode is arranged on the passivation layer and at the connecting via hole. ⁇ Pole connection.
  • FIG. 5 is a schematic diagram of the structure of the first embodiment of the disclosed array substrate
  • FIG. 6 is a cross-sectional view along the A-A direction in FIG. 5.
  • the array substrate provided by this embodiment includes:
  • the gate insulating layer 12 covering the pixel electrode 50, the gate line 30 and the gate electrode 11;
  • the active layer 13, the source electrode 14, the drain electrode 15 and the data line 40 are arranged on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15;
  • the passivation layer 16 covering the active layer 13, the source electrode 14, the drain electrode 15 and the data line 40, the passivation layer 16 is provided with a via hole exposing the drain electrode 14 and the pixel electrode 50 at the same time;
  • the common electrode 20 and the connection electrode 60 are provided on the passivation layer 16, and the connection electrode 60 is simultaneously connected to the drain electrode 15 and the pixel electrode 50 through the one via via.
  • the gate electrode 11, the active layer 13, the source electrode 14 and the drain electrode 15 constitute a thin film transistor, which is arranged in the pixel area defined by the vertical intersection of the gate line 30 and the data line 40.
  • the pixel electrode 50 in the lower layer is The plate-shaped electrode, the upper common electrode 20 is a slit electrode, and the common electrode 20 and the pixel electrode 50 together form a multi-dimensional electric field to form an IADS mode array substrate.
  • the technical solution of this embodiment is further described below through the preparation process of the array substrate of this embodiment.
  • the "patterning process” referred to in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature preparation processes in related technologies.
  • the deposition may use known processes such as sputtering, evaporation, chemical vapor deposition, the coating may use a known coating process, and the etching may use a known method, which is not specifically limited herein.
  • thin film refers to a thin film formed by depositing a certain material on a substrate or using other processes.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • pixel electrodes, gate lines and gate electrode patterns are formed on the substrate.
  • Forming pixel electrodes, gate lines and gate electrode patterns on a substrate includes: sequentially depositing a first transparent conductive film and a first metal film on the substrate, and coating a layer of photoresist on the first metal film, using halftone or gray
  • the mask adjusts the photoresist stepwise exposure and development, forms unexposed areas at the gate lines and gate electrode positions, the photoresist with the first thickness, forms a partially exposed area at the pixel electrode positions, and the light with the second thickness Resist, completely exposed areas are formed in other positions without photoresist.
  • the first thickness is greater than the second thickness.
  • the fully exposed area is etched through the first etching process, and the first metal film and the first transparent conductive film in the area are etched away.
  • the photoresist in a part of the exposed area is removed by an ashing process to expose the first metal film.
  • the first metal film in a part of the exposed area is etched by the second etching process, the first metal film in this area is etched away and the first transparent conductive film is retained, and the remaining photoresist is stripped to form on the substrate 10.
  • the pattern of the pixel electrode 50, the gate line 30 and the gate electrode 11, the pixel electrode 50 is a plate-shaped electrode, and the first transparent conductive film remains under the gate line 30 and the gate electrode 11, as shown in FIGS.
  • the substrate can be glass, plastic or a flexible transparent plate
  • the first metal film can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., and can be a single-layer structure. It may also be a multilayer composite structure.
  • the first transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, and may be deposited by a radio frequency magnetron sputtering method (Sputter).
  • Forming the pattern of the active layer, the source electrode, the drain electrode, and the data line includes: sequentially depositing a gate insulating film, a semiconductor film, and a second metal film on the substrate formed with the aforementioned patterns, and coating a layer of photolithography on the second metal film.
  • the photoresist is exposed and developed stepwise using a halftone or gray tone mask, forming unexposed areas at the positions of the source electrode, drain electrode and data line.
  • the photoresist with the first thickness is in the conductive channel position.
  • a partially exposed area is formed with a second thickness of photoresist, and a fully exposed area is formed at other positions without photoresist.
  • the first thickness is greater than the second thickness.
  • the fully exposed area is etched through the first etching process, and the second metal film and semiconductor film in the area are etched away.
  • the photoresist in a part of the exposed area is removed by an ashing process to expose the second metal film.
  • the second metal film in part of the exposed area is etched by the second etching process, the second metal film in the area is etched away, the remaining photoresist is stripped, and the gate insulating layer 12 and the active layer are formed on the substrate 10.
  • the layer 13, the source electrode 14, the drain electrode 15 and the data line 40 are patterned.
  • a conductive channel is formed between the source electrode 14 and the drain electrode 15. The end of the source electrode 14 away from the conductive channel is connected to the data line 40.
  • FIG. 10 is a cross-sectional view in the AA direction in FIG.
  • the gate insulating film can be silicon nitride SiNx, silicon oxide SiOx, or silicon oxynitride Si(ON)x, and can have a single-layer, double-layer or multi-layer structure, using chemical vapor deposition (CVD) or plasma enhanced chemistry
  • the second metal film 50 can be deposited by means of vapor deposition (PECVD); the second metal film 50 can be made of metal materials, such as aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc., and can be a single layer structure or Multi-layer composite structure, deposited by radio frequency magnetron sputtering method.
  • a via pattern is formed.
  • Forming the via pattern includes: depositing a passivation film on the substrate with the aforementioned pattern, coating a layer of photoresist on the passivation film, and using a single-tone mask to expose and develop the photoresist.
  • the position of the via hole is transferred to form an exposed area without photoresist, and an unexposed area is formed at other positions, leaving the photoresist.
  • the fully exposed area is etched through an etching process to etch away the passivation film and gate insulating layer in this area to form a pattern of passivation layer 16 with a via hole, which also exposes the drain electrode 15 and the pixel electrode 50 are shown in FIG. 11 and FIG. 12, and FIG.
  • the via via is composed of two half holes
  • the passivation film in the first via portion K1 is etched away, exposing the drain electrode 15, the passivation film in the second via portion K2 and
  • the gate insulating layer is etched away, exposing the pixel electrode 50, so that the via hole composed of two half holes simultaneously exposes the drain electrode 15 and the pixel electrode 50.
  • the passivation film can be silicon nitride SiNx, silicon oxide SiOx, or silicon oxynitride Si(ON)x, and can be a single-layer, double-layer or multi-layer structure, using chemical vapor deposition (CVD) or plasma enhanced chemistry Vapor deposition (PECVD) method of deposition.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemistry Vapor deposition
  • common electrode and connection electrode patterns are formed.
  • the formation of the common electrode and the connection electrode pattern includes: depositing a second transparent conductive film on the substrate formed with the aforementioned pattern, coating a layer of photoresist on the second transparent conductive film, and applying a monotone mask to the photoresist Expose and develop, form unexposed areas at the common electrode and connecting electrode, leave photoresist, and form exposed areas at other positions without photoresist.
  • the fully exposed area is etched by an etching process to etch away the second transparent conductive film in this area to form patterns of the common electrode 20 and the connecting electrode 60.
  • the common electrode 20 is a slit electrode, and the connecting electrode 60 is set in the through The position of the hole is connected to the drain electrode 15 exposed in the first via hole portion K1 on the one hand, and connected to the pixel electrode 50 exposed in the second via hole portion K2 on the other hand, that is, the connecting electrode 60 passes through the via hole at the same time It is connected to the drain electrode 15 and the pixel electrode 50, as shown in FIGS. 5 and 6.
  • the second transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO, and can be deposited by a radio frequency magnetron sputtering method.
  • the shape of the connecting electrode 60 can be a regular shape such as a rectangle, a circle, or an ellipse when parallel to the substrate plane.
  • the array substrate of this embodiment can also be prepared by other methods.
  • the pixel electrode, the gate line and the gate electrode pattern can be completed by a secondary patterning process.
  • the pixel electrode pattern is formed through a patterning process first, and then the gate line and gate electrode pattern is formed through another patterning process.
  • the active layer, source electrode, drain electrode, and data line pattern can also be completed by a secondary patterning process.
  • the gate insulating layer and the active layer pattern are formed through one patterning process, and then the source electrode, Drain electrode and data line pattern.
  • the array substrate may also include other film layers, such as common electrode leads or flat layers. Those skilled in the art can learn from common knowledge and the prior art, which is not specifically limited here.
  • the array substrate of this embodiment has a single-hole structure, and the connection between the drain electrode and the pixel electrode is realized by using a via via.
  • the present embodiment effectively reduces the number of via holes. Since the single-hole structure only occupies a small structural space, the area of the pixel electrode is correspondingly increased, and the aperture ratio of the display panel is increased.
  • the single-hole structure of this embodiment ensures the uniformity of the diffusion of the alignment film, does not easily produce panel stains, eliminates the factors that cause display defects, improves product quality, and improves yield.
  • the patterning times of the array substrate prepared in this embodiment are the same as the patterning times of the existing manufacturing method, and the process flow is the same as the existing manufacturing process flow. Therefore, the implementation of this embodiment does not need to change the existing process flow, and does not need to change
  • the existing process equipment has good process compatibility, strong practicability and good application prospects.
  • FIG. 13 is a schematic diagram of the structure of the via hole in the embodiment of the disclosure.
  • the via via is actually composed of half of the first via portion (overlaps the drain electrode 15) and half of the second via portion (overlaps the pixel electrode 50), also called half vias ( Half Via) design. Since the active layer and the source/drain electrodes are formed by a patterning process using a halftone or gray tone mask, there is a semiconductor thin film under the drain electrode 15, and the line width CD of the semiconductor thin film is greater than that of the drain electrode 15. The line width CD, that is, the active layer protrusion 131 exists.
  • the active layer protrusion 131 appears because the metal thin film adopts the wet etching method, and the semiconductor thin film adopts the dry etching method. Therefore, it cannot be guaranteed that the ends of the two are flush, resulting in the protruding active layer protrusion 131.
  • the other half of the first via part bridges the gate insulation below the edge
  • the layer 12 will also be damaged and contracted, forming a recessed end surface 121 of the gate insulating layer, and thus will form a cross section at the second via hole portion and the first via hole portion (the area where the elliptical dashed frame is located).
  • the connecting electrode 60 After the connecting electrode 60 is formed, the cross-sections formed at the transition between the second via part and the first via part will cause the connecting electrode 60 to be at the bridge. Broken or increased resistance. Once the connection fails or the resistance increases, it will cause abnormal signal writing and bright and dark pixels, which will affect the product yield and product quality.
  • FIG. 14 is a schematic structural diagram of the second embodiment of the array substrate of the present disclosure.
  • This embodiment is an extension of the foregoing first embodiment.
  • the main structure of the array substrate of this embodiment is the same as that of the foregoing first embodiment.
  • the difference from the foregoing first embodiment is that the connection electrode of this embodiment is also provided with a first Compensation block, the first compensation block is used to improve the connection reliability of the connection electrode.
  • the first compensation block 60A of this embodiment is arranged on the side of the connecting electrode 60 adjacent to the gate line 30.
  • the orthographic projection of the first compensation block 60A on the substrate 10 includes the drain electrode 15 adjacent to the gate line 30.
  • the orthographic projection of the first compensation block 60A on the substrate covers the overlapping area between the drain electrode 15 and the pixel electrode 50
  • the connecting electrode 60 including the first compensation block 60A not only covers the cross section of the transition area of the second via portion (a deep hole with a deeper depth) and the first via portion (a shallow hole with a shallow depth), Moreover, the area outside the section is covered, the coverage width is increased, and the process margin is guaranteed. Even if the connecting electrode 60 is broken at the bridge, the first compensation block 60A covering the area outside the section will not be disconnected. Reliable connection of the connecting electrodes can completely avoid poor pixel bright and dark spots.
  • the first compensation block extends from the main body of the connection electrode toward the gate line
  • the second compensation block extends from the main body of the connection electrode in a direction away from the gate line
  • the first compensation block The size of the block and the second compensation block in the direction parallel to the grid line is smaller than the size of the main body, or the size of the first compensation block and the second compensation block in the direction parallel to the grid line The size is equal to or larger than the size of the main body.
  • the shape of the first compensation block can be rectangular, trapezoidal, semicircular, semi-elliptical, etc., when parallel to the base plane.
  • the shape of the connecting via may be a rectangle, a rectangle with rounded edges, an ellipse, a circle, etc., which is not limited in the embodiment of the present disclosure.
  • This embodiment not only has the technical effect of the aforementioned first embodiment, that is, it increases the aperture ratio and improves the yield, but also can ensure the connection reliability of the connecting electrode through the compensation design, ensure the normal writing of the signal, and avoid the bright and dark pixels of the pixel. Bad, to ensure product yield and product quality.
  • FIG. 15 is a schematic structural diagram of the third embodiment of the disclosed array substrate.
  • This embodiment is an extension of the foregoing first embodiment.
  • the main structure of the array substrate of this embodiment is the same as that of the foregoing first embodiment.
  • the difference from the foregoing first embodiment is that the connection electrode of this embodiment is also provided with a first Compensation block and second compensation block.
  • the first compensation block 60A of this embodiment is arranged on the side of the connecting electrode 60 adjacent to the gate line 30, and the second compensation block 60B is arranged on the side of the connecting electrode 60 away from the gate line 30, that is, the side of the connecting electrode 60 Compensation blocks are provided on both sides.
  • the structure of the first compensation block 60A is the same as that of the foregoing second embodiment, and will not be repeated here.
  • the orthographic projection of the second compensation block 60B on the substrate 10 includes a part of the orthographic projection of the edge of the drain electrode 15 away from the gate line 30 on the substrate 10, in the direction parallel to the gate line 30 (perpendicular to the data line 40),
  • the orthographic projection of the two compensation blocks 60B on the substrate 10 covers the orthographic projection of the boundary between the drain electrode 15 and the pixel electrode 50 on the substrate 10 on the side far from the gate line.
  • the second compensation block 60B and The orthographic projection of the connecting electrode of the first compensation block 60A on the substrate covers the orthographic projection of the overlapping area between the drain electrode 15 and the pixel electrode 50 on the substrate 10.
  • the connecting electrode 60 including the first compensation block 60A and the second compensation block 60B not only covers the second via portion (a deep hole with a deeper depth), and the first via portion (a shallow hole with a shallow depth).
  • the cross-section of the transition area which covers the area outside the cross-section, increases the coverage width, ensures the process margin, and maximizes the reliable connection of the connecting electrodes, which can completely avoid poor pixel bright and dark spots.
  • the shape of the first compensation block and the second compensation block can be rectangular, trapezoidal, semi-circular, semi-elliptical, etc., when parallel to the base plane. In actual implementation, it is also possible to set only the second compensation block according to layout requirements.
  • the first compensation block extends from the main body of the connection electrode toward the gate line
  • the second compensation block extends from the main body of the connection electrode in a direction away from the gate line
  • the first compensation block The size of the block and the second compensation block in the direction parallel to the grid line is smaller than the size of the main body, or the size of the first compensation block and the second compensation block in the direction parallel to the grid line The size is equal to or larger than the size of the main body.
  • This embodiment not only has the technical effect of the aforementioned first embodiment, that is, it increases the aperture ratio and improves the yield, but also can ensure the connection reliability of the connecting electrode through the compensation design, ensure the normal writing of the signal, and avoid the bright and dark pixels of the pixel. Bad, to ensure product yield and product quality.
  • this embodiment provides a method for manufacturing an array substrate, including:
  • connection electrode is formed on the passivation layer and at the connection via, and the connection electrode is simultaneously connected to the pixel electrode and the drain electrode through the via via.
  • step S1 includes:
  • step S11 includes:
  • step S12 includes:
  • the second metal film in a part of the exposed area is etched by the second etching process, and the remaining photoresist is stripped to form a gate insulating layer, an active layer, a source electrode, a drain electrode, and a data line, and the source electrode and leakage current A conductive channel is formed between the electrodes.
  • step S2 includes:
  • the passivation film and the gate insulating layer in the fully exposed area are etched by an etching process to form a passivation layer provided with a via hole, and the via hole simultaneously exposes the drain electrode and the pixel electrode.
  • the via via includes a first via portion and a second via portion, the passivation layer in the first via portion is etched away, exposing the drain electrode, and the second via The passivation layer and the gate insulating layer in the hole portion are etched away, exposing the pixel electrode.
  • step S3 includes:
  • the second transparent conductive film in the fully exposed area is etched by an etching process to form a common electrode and a connecting electrode.
  • the common electrode is a slit electrode, and the connecting electrode is simultaneously connected to the pixel electrode and the leakage through the via hole. ⁇ Pole connection.
  • the shape of the connecting electrode 60 can be a regular shape such as a rectangle, a circle, or an ellipse when parallel to the substrate plane.
  • connection electrode is further provided with a first compensation block, and the first compensation block is used to improve the connection reliability of the connection electrode.
  • the first compensation block is arranged on the side of the connecting electrode adjacent to the gate line, and the orthographic projection of the first compensation block on the substrate includes at least a part of the orthographic projection of the edge of the drain electrode adjacent to the gate line on the substrate, which is parallel to the gate line. In the direction, the orthographic projection of the first compensation block on the substrate covers the orthographic projection on the substrate of the overlap region between the drain electrode and the pixel electrode near the border of the gate line.
  • connection electrode is further provided with a second compensation block, and the second compensation block is used to improve the connection reliability of the connection electrode.
  • the second compensation block is arranged on the side of the connection electrode away from the gate line, and in the direction parallel to the data line, the orthographic projection of the second compensation block on the substrate includes at least the orthographic projection of the edge of the drain electrode away from the gate line on the substrate. In a part, in a direction parallel to the gate line, the orthographic projection of the second compensation block on the substrate covers the orthographic projection of the overlap area between the drain electrode and the pixel electrode on the boundary substrate on the side away from the gate line.
  • the connecting electrode is also provided with a first compensation block and a second compensation block at the same time.
  • the shape of the first compensation block and the second compensation block may be rectangular, trapezoidal, semicircular, semi-elliptical, or the like.
  • This embodiment provides a method for preparing an array substrate.
  • the connection between the drain electrode and the pixel electrode is realized through a via via.
  • this embodiment effectively reduces the number of vias.
  • the number increases the aperture ratio of the display panel.
  • this embodiment improves the product quality and improves the yield rate.
  • the number of patterning times in this embodiment is the same as that of the existing preparation, and the process flow is the same as the existing preparation process flow. Therefore, the implementation of this embodiment does not need to change the existing process flow or the existing process equipment. It has good process compatibility, strong practicability and good application prospects.
  • the embodiment of the present disclosure also provides a display panel including the aforementioned array substrate.
  • the display panel can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the first via hole partially exposes the drain electrode, and the second via hole partially exposes the pixel electrode” and “the connection via hole exposes the drain electrode and the pixel electrode” refers to before the connection electrode is formed.
  • the connection vias expose the drain electrode and the pixel electrode to facilitate connection with the connection electrode.
  • the connection via is filled with other components, such as the connection electrode. The final product does not expose the drain electrode and the pixel electrode. .
  • the shape of the connecting via may be a rectangle, a rectangle with rounded edges, an ellipse, a circle, etc., which is not limited in the embodiment of the present disclosure.
  • the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display panel, which realize the connection between the drain electrode and the pixel electrode through a via via.
  • the embodiments of the present disclosure effectively reduce the number of via holes and increase the aperture ratio of the display panel.
  • the single-hole structure of the embodiment of the present disclosure eliminates factors that cause display defects, improves product quality, and improves yield.
  • the implementation of the present disclosure does not need to change the existing process flow, does not need to change the existing process equipment, has good process compatibility, strong practicability and good application prospects.
  • the terms “installed”, “connected”, and “connected” should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate piece, and it can be inside the two components. Connected.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate piece, and it can be inside the two components. Connected.
  • the specific meaning of the above-mentioned terms in the present disclosure can be understood in specific situations.

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Abstract

一种阵列基板及其制备方法、显示面板。阵列基板包括：基底(10)；设置在基底(10)上的像素电极(50)和薄膜晶体管；覆盖薄膜晶体管和像素电极(50)的钝化层(16)，钝化层(16)上开设有同时暴露出像素电极(50)和薄膜晶体管的漏电极(15)或源电极(14)的一个转接过孔(K1，K2)；设置在钝化层(16)上且在转接过孔(K1，K2)处的连接电极(60)，连接电极(60)通过转接过孔(K1，K2)同时与像素电极(50)和漏电极(15)或源电极(14)连接。通过设置一个转接过孔(K1，K2)实现漏电极(15)或源电极(14)与像素电极(50)之间的连接，有效减少了过孔数量，增加了显示面板的开口率，提高了产品品质，提高了良品率。

Description

阵列基板及其制备方法、显示面板 技术领域
本公开涉及一种阵列基板及其制备方法、显示面板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有体积小、功耗低、无辐射等特点，近年来得到迅速发展。LCD的主体结构包括对盒(CELL)的薄膜晶体管阵列(Thin Film Transistor，TFT)基板和彩膜(Color Filter，CF)基板，液晶(Liquid Crystal，LC)分子填充在阵列基板和彩膜基板之间，通过控制公共电极和像素电极来形成驱动液晶偏转的电场，实现灰阶显示。按照显示模式，LCD可以分为：扭曲向列(Twisted Nematic，TN)显示模式、平面转换(In Plane Switching，IPS)显示模式和高级超维场转换(Advanced Super Dimension Switch，ADS)显示模式等。其中，ADS显示模式已成为比较成熟的显示模式，具有广视角、高开口率、高穿透率、高分辨率、响应速度快、低功耗、低色差等优点。
近年来，在ADS显示模式基础上，现有技术提出了IADS(Interchange Advanced Super Dimension Switch)显示模式。研究表明，当采用双栅像素架构时，IADS模式可提升光效，从而提升像素透过率。而双栅像素架构可减小源驱动集成电路IC的数量，降低成本。因而，IADS显示模式逐渐得到广泛应用。
发明内容
本公开的实施例提供一种阵列基板及其制备方法、显示面板，能够增加开口率，提升良品率。
一方面，本公开实施例提供了一种阵列基板，包括：
基底；
设置在所述基底上的像素电极和薄膜晶体管；
覆盖所述薄膜晶体管和所述像素电极的钝化层，所述钝化层上开设有同时暴露出所述像素电极和所述薄膜晶体管的漏电极或源电极的转接过孔；
设置在所述钝化层上且在所述连接过孔处的连接电极，所述连接电极通 过所述转接过孔与所述像素电极，和所述漏电极或所述源电极连接。
可选地，所述连接过孔在所述基底上的正投影与所述像素电极在所述基底上的正投影以及所述漏电极或源电极在所述基底上的正投影重叠。
可选地，根据本公开实施例的阵列基板还包括栅线和数据线，所述薄膜晶体管包括栅电极、有源层、源电极和漏电极，所述像素电极、栅线和栅电极设置在所述基底上，所述像素电极、所述栅线和所述栅电极上覆盖有栅绝缘层，所述有源层、源电极、漏电极和数据线设置在所述栅绝缘层上，所述源电极与漏电极之间形成导电沟道。
可选地，所述连接电极在邻近栅线的一侧设置有第一补偿块，第一补偿块在所述基底上的正投影包含所述漏电极或所述源电极邻近栅线一侧的边缘在基底上的正投影的至少一部分，和/或，所述连接电极远离栅线的一侧设置有第二补偿块，第二补偿块在基底上的正投影包含漏电极或源电极远离栅线一侧的边缘在基底上的正投影的至少一部分。
可选地，所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸。
可选地，所述连接电极在所述基底上的正投影覆盖所述漏电极或所述源电极与所述像素电极之间的重叠区域在所述基板上的正投影。
可选地，所述第一补偿块和/或第二补偿块的形状包括矩形、梯形、半圆形或半椭圆形。
可选地，所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分暴露出所述漏电极，所述第二过孔部分暴露出所述像素电极。
另一方面，本公开的实施例还提供了一种显示面板，包括上述阵列基板。
再一方面，本公开的实施例还提供了一种阵列基板的制备方法，包括：
形成像素电极和薄膜晶体管；
形成覆盖所述薄膜晶体管的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极或源电极的转接过孔；
在所述钝化层上且在所述连接过孔处形成连接电极，所述连接电极通过所述转接过孔同时与所述像素电极和漏电极或源电极连接。
可选地，在基底上形成像素电极和薄膜晶体管，包括：
通过一次构图工艺形成像素电极、栅线和栅电极；
通过一次构图工艺形成栅绝缘层、有源层、源电极、漏电极和数据线，所述源电极与漏电极之间形成导电沟道。
可选地，所述连接电极在邻近栅线的一侧设置有第一补偿块，第一补偿块在所述基底上的正投影包含所述漏电极或所述源电极邻近栅线一侧的边缘在基底上的正投影的至少一部分，和/或，所述连接电极远离栅线的一侧设置有第二补偿块，第二补偿块在基底上正投影包含漏电极或源电极远离栅线一侧的边缘在基底上的正投影的至少一部分。
可选地，所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸。
可选地，所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分暴露出所述漏电极，所述第二过孔部分暴露出所述像素电极。
可选地，所述通过一次构图工艺形成像素电极、栅线和栅电极包括：在所述基底上依次沉积第一透明导电薄膜和第一金属薄膜；在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在待形成所述栅线和栅电极的位置处形成未曝光区域，具有第一厚度的光刻胶，在待形成的像素电极的位置处形成部分曝光区域，具有第二厚度的光刻胶，在其它位置处形成完全曝光区域，无光刻胶，第一厚度大于第二厚度；通过第一次刻蚀工艺刻蚀掉完全曝光区域的所述第一金属薄膜和所述第一透明导电薄膜；通过灰化工艺去除所述部分曝光区域的光刻胶，暴露出所述第一金属薄膜；以及通过第二次刻蚀工艺刻蚀掉所述部分曝光区域的第一金属薄膜，剥离剩余的光刻胶，在基底上形成所述像素电极、栅线和栅电极。
可选地，所述通过一次构图工艺形成栅绝缘层、有源层、源电极、漏电极和数据线，所述源电极与漏电极之间形成导电沟道包括：在形成有所述像素电极、栅线和栅电极的基底上依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜；在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在待形成源电极、漏电极和数据线的位置处形成未曝光区域，具有第一厚度的光刻胶，在待形成导电沟道的位置处形成部分曝光区域，具有第二厚度的光刻胶，在其它位置处形成完全曝光区域， 无光刻胶，第一厚度大于第二厚度；通过第一次刻蚀工艺刻蚀掉所述完全曝光区域的第二金属薄膜和半导体薄膜；通过灰化工艺去除所述部分曝光区域的光刻胶，暴露出第二金属薄膜；通过第二次刻蚀工艺刻蚀掉所述部分曝光区域的第二金属薄膜，剥离剩余的光刻胶，形成栅绝缘层、有源层、源电极、漏电极和数据线，源电极与漏电极之间形成导电沟道。
可选地，所述形成覆盖所述薄膜晶体管的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极或源电极的转接过孔包括：在形成有所述薄膜晶体管和所述像素电极的基底上沉积钝化薄膜；在钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在转接过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶；通过刻蚀工艺刻蚀掉完全曝光区域的钝化薄膜和栅绝缘层，形成开设有转接过孔的钝化层，转接过孔同时暴露出漏电极和像素电极，所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分中的钝化层被刻蚀掉，暴露出所述漏电极，所述第二过孔部分中的钝化层和栅绝缘层被刻蚀掉，暴露出所述像素电极。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为一种ADS显示模式阵列基板的结构示意图；
图2为图1中A-A向的剖面图；
图3为一种IADS显示模式阵列基板的结构示意图；
图4为图3中A-A向的剖面图；
图5为本公开阵列基板第一实施例的结构示意图；
图6为图5中A-A向的剖面图；
图7为本公开第一实施例形成像素电极、栅线和栅电极图案后的示意图；
图8为图7中A-A向的剖面图；
图9为本公开第一实施例形成有源层、源电极、漏电极和数据线图案后的示意图；
图10为图9中A-A向的剖面图；
图11为本公开第一实施例形成转接过孔图案后的示意图；
图12为图11中A-A向的剖面图；
图13为本公开实施例转接过孔的结构示意图；
图14为本公开阵列基板第二实施例的结构示意图；
图15为本公开阵列基板第三实施例的结构示意图。
附图标记说明:
10—基底；20—公共电极；30—栅线；
40—数据线；50—像素电极；60—连接电极；
60A—第一补偿块；60B—第二补偿块；11—栅电极；
12—栅绝缘层；13—有源层；14—源电极；
15—漏电极；16—钝化层；121—凹进端面；
131—有源层凸部；K1—第一过孔部分；K2—第二过孔部分。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
在除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
经本申请发明人研究发现，一种IADS显示模式的显示面板存在开口率较小和良品率较低的缺陷。
下面结合附图和实施例对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。需要说明的是，在 不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图1为一种ADS显示模式阵列基板的结构示意图，图2为图1中A-A向的剖面图。图示ADS显示模式的阵列基板的结构特点是，公共电极设置在基底上，为板状电极，像素电极设置在钝化层上，为狭缝电极，阵列基板的膜层结构包括：基底，公共电极，栅线、栅电极和公共电极引线，栅绝缘层(GI)，有源层(Active)、源电极、漏电极和数据线，钝化层(PVX)，像素电极。栅线施加开启电压时，数据线的数据信号通过薄膜晶体管写入到漏电极，经单孔转接到像素电极，完成信号写入。如图1和图2所示，阵列基板包括基底10，设置在基底上的公共电极20、栅线30和栅电极11，覆盖公共电极20、栅线30和栅电极11的栅绝缘层12，设置在栅绝缘层12上的有源层13、源电极14、漏电极15和数据线40，源电极14与漏电极15之间形成导电沟道，覆盖源电极14、漏电极15、数据线40和导电沟道的钝化层16，其上开设有暴露出漏电极15的过孔，设置在钝化层16上的像素电极50，像素电极50通过钝化层16上的过孔与漏电极15连接。其中，公共电极20用于提供公共电压，像素电极50用于提供显示用像素电压，狭缝电极与板状电极之间产生的多维电场驱动液晶偏转。
图3为一种IADS显示模式阵列基板的结构示意图，图4为图3中A-A向的剖面图。这种IADS显示模式是在ADS显示模式基础上，将公共电极和像素电极的位置互换，阵列基板的结构特点是，像素电极设置在基底上，为板状电极，公共电极设置在钝化层上，为狭缝电极，阵列基板的膜层结构包括：基底，像素电极，栅线和栅电极，栅绝缘层，有源层、源电极、漏电极、数据线和公共电极引线，钝化层，公共电极和连接电极。栅线施加开启电压时，数据线的数据信号通过薄膜晶体管写入到漏电极，经双孔转接到像素电极，完成信号写入。如图3和4所示，阵列基板包括基底10，设置在基底上的像素电极50、栅线30和栅电极11，覆盖像素电极50、栅线30和栅电极11的栅绝缘层12，设置在栅绝缘层12上的有源层13、源电极14、漏电极15和数据线40，源电极14与漏电极15之间形成导电沟道，覆盖源电极14、漏电极15、数据线40和导电沟道的钝化层16，其上开设有暴露出漏电极15的第一过孔和暴露出像素电极50的第二过孔，设置在钝化层16上的公共电极20和连接电极60，连接电极60一方面通过第一过孔与漏电极15连接，另一方面通过第二过孔与像素电极50连接，即像素电极50与漏电极15之间 通过双孔结构实现连接。
经本申请发明人研究发现，以上IADS显示模式的显示面板存在开口率较小和良品率较低的原因，很大程度是由双孔结构造成的。具体地，过孔尺寸、形状和数量对开口率和良品率影响较大，对于高分辨产品，影响更加重要，相对于ADS显示模式的单孔结构，IADS显示模式的双孔结构需要较大的结构空间，相应减小了像素电极的面积，因而IADS显示模式显示面板的开口率较小。虽然可以通过调整信号线宽度来尽量增加像素电极的面积，但该方式会严重影响像素电极的充电率。同时，因显示区域像素电极的数量成百上千万，大屏幕产品更是有上亿个像素电极，相对于ADS显示模式的单孔结构，IADS显示模式的过孔数量翻倍，影响了取向膜(PI)扩散均一性，在取向膜不均一的位置，显示面板宏观上会表现出类似于污渍的斑点(Mura)，业内称之为面板污点(Panel Stain)或者面板污渍，影响产品品质，降低良品率。
为此，本公开实施例提供了一种阵列基板，能够提升开口率以及良品率。本公开实施例阵列基板包括基底，设置在所述基底上的像素电极和薄膜晶体管，覆盖所述薄膜晶体管和薄膜晶体管的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极或源电极的转接过孔，设置在所述钝化层上且在所述连接过孔处的连接电极，所述连接电极通过所述转接过孔同时与像素电极和漏电极连接。
下面通过具体实施例详细说明本公开实施例的技术方案。
第一实施例
图5为本公开阵列基板第一实施例的结构示意图，图6为图5中A-A向的剖面图。如图5和图6所示，本实施例所提供的阵列基板包括：
基底10；
设置在基底10上的像素电极50、栅线30和栅电极11；
覆盖像素电极50、栅线30和栅电极11的栅绝缘层12；
设置在栅绝缘层12上的有源层13、源电极14、漏电极15和数据线40，源电极14与漏电极15之间形成导电沟道；
覆盖有源层13、源电极14、漏电极15和数据线40的钝化层16，钝化层16上开设有同时暴露出漏电极14和像素电极50的一个转接过孔；
设置在钝化层16上的公共电极20和连接电极60，连接电极60通过该 一个转接过孔同时与漏电极15和像素电极50连接。
本实施例中，栅电极11、有源层13、源电极14和漏电极15组成薄膜晶体管，设置在栅线30和数据线40垂直交叉所限定出的像素区域内，下层的像素电极50为板状电极，上层的公共电极20为狭缝电极，公共电极20与像素电极50一起形成多维电场，构成IADS模式阵列基板。
下面通过本实施例阵列基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
第一次构图工艺中，在基底上形成像素电极、栅线和栅电极图案。在基底上形成像素电极、栅线和栅电极图案包括：在基底上依次沉积第一透明导电薄膜和第一金属薄膜，在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在栅线和栅电极位置形成未曝光区域，具有第一厚度的光刻胶，在像素电极位置形成部分曝光区域，具有第二厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。其中，第一厚度大于第二厚度。通过第一次刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第一金属薄膜和第一透明导电薄膜。通过灰化工艺去除部分曝光区域的光刻胶，暴露出第一金属薄膜。通过第二次刻蚀工艺对部分曝光区域的第一金属薄膜进行刻蚀，刻蚀掉该区域的第一金属薄膜而保留第一透明导电薄膜，剥离剩余的光刻胶，在基底10上形成像素电极50、栅线30和栅电极11图案，像素电极50为板状电极，栅线30和栅电极11的下方保留有第一透明导电薄膜，如图7和图8所示，图8为图7中A-A向的剖面图。其中，基底可以采用玻璃、塑料或者柔性透明板，第一金属薄膜采用金属材料，如铝、铜、钼、钛、铌、银、金、钽、钨、铬等材料，可以是单层结构，也可以是多层复合结构，第一透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO， 可以采用射频磁控溅射方法(Sputter)沉积。
第二次构图工艺中，形成有源层、源电极、漏电极和数据线图案。形成有源层、源电极、漏电极和数据线图案包括：在形成有前述图案的基底上依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜，在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在源电极、漏电极和数据线位置形成未曝光区域，具有第一厚度的光刻胶，在导电沟道位置形成部分曝光区域，具有第二厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶。其中，第一厚度大于第二厚度。通过第一次刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二金属薄膜和半导体薄膜。通过灰化工艺去除部分曝光区域的光刻胶，暴露出第二金属薄膜。通过第二次刻蚀工艺对部分曝光区域的第二金属薄膜进行刻蚀，刻蚀掉该区域的第二金属薄膜，剥离剩余的光刻胶，在基底10上形成栅绝缘层12、有源层13、源电极14、漏电极15和数据线40图案，源电极14与漏电极15之间形成导电沟道，源电极14远离导电沟道的一端与数据线40连接，源电极14、漏电极15和数据线40的下方保留有半导体薄膜，如图9和图10所示，图10为图9中A-A向的剖面图。其中，栅绝缘薄膜可以采用氮化硅SiNx、氧化硅SiOx或氮氧化硅Si(ON)x，可以为单层、双层或者多层结构，采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积；第二金属薄膜50可以采用金属材料，如铝、铜、钼、铌、钛、银、金、钽、钨、铬等材料，可以是单层结构，也可以是多层复合结构，采用射频磁控溅射方法沉积。
第三次构图工艺中，形成转接过孔图案。形成转接过孔图案包括：在形成有前述图案的基底上沉积钝化薄膜，在钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在转接过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶。通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的钝化薄膜和栅绝缘层，形成开设有一个转接过孔的钝化层16图案，转接过孔同时暴露出漏电极15和像素电极50，如图11和图12所示，图12为图11中A-A向的剖面图。本实施例中，转接过孔由两个半孔组成，第一过孔部分K1内的钝化薄膜被刻蚀掉，暴露出漏电极15，第二过孔部分K2内的钝化薄膜和栅绝缘层被刻蚀掉，暴露出像素电极50，使得两个半孔组成的转接过孔同时暴露出漏电极15和像素电极50。 其中，钝化薄膜可以采用氮化硅SiNx、氧化硅SiOx或氮氧化硅Si(ON)x，可以为单层、双层或者多层结构，采用化学气相沉积(CVD)方式或等离子体增强化学气相沉积(PECVD)方式沉积。
第四次构图工艺中，形成公共电极和连接电极图案。形成公共电极和连接电极图案包括：在形成有前述图案的基底上沉积第二透明导电薄膜，在第二透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在公共电极和连接电极位置形成未曝光区域，保留光刻胶，在其它位置形成曝光区域，无光刻胶。通过刻蚀工艺对完全曝光区域进行刻蚀，刻蚀掉该区域的第二透明导电薄膜，形成公共电极20和连接电极60图案，公共电极20为狭缝电极，连接电极60设置在转接过孔所在位置，一方面与第一过孔部分K1中暴露出的漏电极15连接，另一方面与第二过孔部分K2暴露出的像素电极50连接，即连接电极60通过转接过孔同时与漏电极15和像素电极50连接，如图5和图6所示。其中，第二透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，可以采用射频磁控溅射方法沉积。实际实施时，在平行于基底平面，连接电极60的形状可以是矩形、圆形或椭圆形等规则形状。
虽然前面以四次构图工艺为例，说明了本实施例阵列基板的制备过程，但实际实施时，本实施例阵列基板也可以通过其它方法制备。例如，像素电极、栅线和栅电极图案可以采用二次构图工艺完成，先通过一次构图工艺形成像素电极图案，然后通过另一次构图工艺形成栅线和栅电极图案。又如，有源层、源电极、漏电极和数据线图案也可以采用二次构图工艺完成，先通过一次构图工艺形成栅绝缘层和有源层图案，然后通过另一次构图工艺形成源电极、漏电极和数据线图案。此外，前述第一次、第二次构图工艺中，采用半色调或灰色调掩膜版进行阶梯曝光、二次刻蚀以及灰化工艺等，是本领域常用的处理工艺，这里不再赘述。阵列基板还可以包括其他膜层，如公共电极引线或平坦层等，本领域技术人员能够根据公知常识以及现有技术获知，这里不作具体限定。
通过本实施例阵列基板的制备过程可以看出，本实施例阵列基板为单孔结构，利用一个转接过孔实现了漏电极与像素电极之间的连接。相对于现有结构的双孔设计，本实施例有效减少了过孔数量，由于单孔结构仅占用较小的结构空间，相应增加了像素电极的面积，增加了显示面板的开口率。同时，本实施例单孔结构保证了取向膜扩散均一性，不易产生面板污渍，消除了导 致显示缺陷的因素，提高了产品品质，提高了良品率。进一步地，本实施例制备阵列基板的构图次数与现有制备方式的构图次数相同，且工艺流程与现有制备工艺流程相同，因此本实施例的实施不需要改变现有工艺流程，不需改变现有工艺设备，工艺兼容性好，实用性强，具有良好的应用前景。
第二实施例
图13为本公开实施例转接过孔的结构示意图。如图13所示，转接过孔实际上由一半第一过孔部分(搭接漏电极15)和一半第二过孔部分(搭接像素电极50)组成，也称之为半过孔(Half Via)设计。由于有源层与源电极/漏电极是采用一张半色调或灰色调掩膜版通过一次构图工艺形成，因此在漏电极15下方存在半导体薄膜，且半导体薄膜的线宽CD大于漏电极15的线宽CD，即存在有源层凸部131。出现有源层凸部131是由于金属薄膜采用湿刻方式，半导体薄膜则采用干刻方式，因而不能保证两者的端部平齐，造成凸出的有源层凸部131。同时，在刻蚀转接过孔的一半第二过孔部分(具有较深深度的深孔)时，另一半第一过孔部分(具有较浅深度的浅孔)跨接边缘下方的栅绝缘层12也会受损内缩，形成栅绝缘层凹进端面121，因而会在第二过孔部分、第一过孔部分转接处(椭圆形虚线框所在区域)形成断面。考虑到界面不平和应力效应等因素，如断面处豁口较大，在形成连接电极60后，第二过孔部分、第一过孔部分转接处形成的断面会导致连接电极60在跨接处断裂或电阻加大。一旦连接失效或电阻加大，会导致信号写入异常，出现像素亮暗点，影响产品良率和产品品质。
为此，本实施例提供了一种带有补偿块的连接电极。图14为本公开阵列基板第二实施例的结构示意图。本实施例是前述第一实施例的一种扩展，本实施例阵列基板的主体结构与前述第一实施例相同，与前述第一实施例不同的是，本实施例连接电极还设置有第一补偿块，第一补偿块用于提高连接电极的连接可靠性。如图14所示，本实施例第一补偿块60A设置在连接电极60邻近栅线30的一侧，第一补偿块60A在基底10上的正投影包含漏电极15邻近栅线30一侧的边缘在基底10上的正投影的至少一部分，在平行于栅线30(垂直于数据线40)方向，第一补偿块60A在基底上的正投影覆盖漏电极15与像素电极50之间重叠区域在靠近所述栅线一侧的边界在基底10上的正投影，这样包括第一补偿块60A的连接电极在基底10上的正投影覆盖漏电极15与像素电极50之间重叠区域在靠近栅线一侧的边界在基底10上的 正投影。这样，包含第一补偿块60A的连接电极60不仅覆盖了第二过孔部分(具有较深深度的深孔)、第一过孔部分(具有较浅深度的浅孔)转接区域的断面，而且覆盖了断面之外的区域，增加了覆盖宽度，保证了工艺余量(Margin)，即使连接电极60在跨接处断裂，覆盖断面之外区域的第一补偿块60A不会断开，保证了连接电极的可靠连接，可完全避免像素亮暗点不良。
例如，所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸，或者所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸等于或大于所述主体的尺寸。
实际实施时，在平行于基底平面，第一补偿块的形状可以是矩形、梯形、半圆形或半椭圆形等形状。
在平行于基底的平面中，连接过孔的形状可以是矩形、边缘修圆的矩形、椭圆形、圆形等形状，本公开的实施例并不对此进行限制。
本实施例不仅具有前述第一实施例的技术效果，即增加了开口率和提高了良品率，而且通过补偿设计可保证连接电极的连接可靠性，确保信号正常写入，避免了像素亮暗点不良，保证了产品良率和产品品质。
第三实施例
图15为本公开阵列基板第三实施例的结构示意图。本实施例是前述第一实施例的一种扩展，本实施例阵列基板的主体结构与前述第一实施例相同，与前述第一实施例不同的是，本实施例连接电极还设置有第一补偿块和第二补偿块。如图15所示，本实施例第一补偿块60A设置在连接电极60邻近栅线30的一侧，第二补偿块60B设置在连接电极60远离栅线30的一侧，即连接电极60的两侧均设置有补偿块。第一补偿块60A的结构与前述第二实施例相同，这里不再赘述。第二补偿块60B在基底10上的正投影包含漏电极15远离栅线30一侧的边缘在基底10上的正投影的一部分，在平行于栅线30(垂直于数据线40)方向，第二补偿块60B在基底10上的正投影覆盖漏电极15与像素电极50之间重叠区域在远离所述栅线一侧的边界在基底10上的正投影，这样，包括第二补偿块60B和第一补偿块60A的连接电极在基底上的正投影覆盖漏电极15与像素电极50之间重叠区域在基底10上的正投影。这样，包含第一补偿块60A和第二补偿块60B的连接电极60不仅覆盖了第 二过孔部分(具有较深的深度的深孔)、第一过孔部分(具有较浅深度的浅孔)转接区域的断面，而且覆盖了断面之外的区域，增加了覆盖宽度，保证了工艺余量，最大限度地保证了连接电极的可靠连接，可完全避免像素亮暗点不良。本实施例中，在平行于基底平面，第一补偿块和第二补偿块的形状可以是矩形、梯形、半圆形或半椭圆形等形状。实际实施时，也可以根据布局需要，仅设置第二补偿块。
例如，所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸，或者所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸等于或大于所述主体的尺寸。
本实施例不仅具有前述第一实施例的技术效果，即增加了开口率和提高了良品率，而且通过补偿设计可保证连接电极的连接可靠性，确保信号正常写入，避免了像素亮暗点不良，保证了产品良率和产品品质。
第四实施例
基于前述实施例的技术构思，本实施例提供了一种阵列基板的制备方法，包括：
S1、形成像素电极和薄膜晶体管；
S2、形成覆盖所述薄膜晶体管和所述像素电极的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极的转接过孔；
S3、在所述钝化层上且在所述连接过孔处形成连接电极，所述连接电极通过所述转接过孔同时与所述像素电极和漏电极连接。
其中，步骤S1包括：
S11、通过一次构图工艺形成像素电极、栅线和栅电极；
S12、通过一次构图工艺形成有源层、源电极、漏电极和数据线，所述源电极与漏电极之间形成导电沟道。
其中，步骤S11包括：
S111、在基底上依次沉积第一透明导电薄膜和第一金属薄膜；
S112、在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在栅线和栅电极位置形成未曝光区域，具有第一厚度的光刻胶，在像素电极位置形成部分曝光区域，具有第二厚度的光 刻胶，在其它位置形成完全曝光区域，无光刻胶，第一厚度大于第二厚度；
S113、通过第一次刻蚀工艺刻蚀掉完全曝光区域的第一金属薄膜和第一透明导电薄膜；
S114、通过灰化工艺去除部分曝光区域的光刻胶，暴露出第一金属薄膜；
S115、通过第二次刻蚀工艺刻蚀掉部分曝光区域的第一金属薄膜，剥离剩余的光刻胶，在基底上形成像素电极、栅线和栅电极。
其中，步骤S12包括：
S121、依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜；
S122、在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在源电极、漏电极和数据线位置形成未曝光区域，具有第一厚度的光刻胶，在导电沟道位置形成部分曝光区域，具有第二厚度的光刻胶，在其它位置形成完全曝光区域，无光刻胶，第一厚度大于第二厚度；
S123、通过第一次刻蚀工艺刻蚀掉完全曝光区域的第二金属薄膜和半导体薄膜；
S124、通过灰化工艺去除部分曝光区域的光刻胶，暴露出第二金属薄膜；
S125、通过第二次刻蚀工艺刻蚀掉部分曝光区域的第二金属薄膜，剥离剩余的光刻胶，形成栅绝缘层、有源层、源电极、漏电极和数据线，源电极与漏电极之间形成导电沟道。
其中，步骤S2包括：
S21、沉积钝化薄膜；
S22、在钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在转接过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶；
S23、通过刻蚀工艺刻蚀掉完全曝光区域的钝化薄膜和栅绝缘层，形成开设有转接过孔的钝化层，转接过孔同时暴露出漏电极和像素电极。
其中，所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分中的钝化层被刻蚀掉，暴露出所述漏电极，所述第二过孔部分中的钝化层和栅绝缘层被刻蚀掉，暴露出所述像素电极。
其中，步骤S3包括：
S31、沉积第二透明导电薄膜；
S32、在第二透明导电薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在公共电极和连接电极位置形成未曝光区域，保留光刻胶，在其它位置形成曝光区域，无光刻胶；
S33、通过刻蚀工艺刻蚀掉完全曝光区域的第二透明导电薄膜，形成公共电极和连接电极，公共电极为狭缝电极，连接电极通过所述转接过孔同时与所述像素电极和漏电极连接。
其中，在平行于基底平面，连接电极60的形状可以是矩形、圆形或椭圆形等规则形状。
在一个实施例中，连接电极还设置有第一补偿块，第一补偿块用于提高连接电极的连接可靠性。第一补偿块设置在连接电极邻近栅线的一侧，第一补偿块在基底上的正投影包含漏电极邻近栅线一侧的边缘在基底上的正投影的至少一部分，在平行于栅线方向，第一补偿块在基底上的正投影覆盖漏电极与像素电极之间重叠区域靠近栅线一侧边界在基底上的正投影。
在另一个实施例中，连接电极还设置有第二补偿块，第二补偿块用于提高连接电极的连接可靠性。第二补偿块设置在连接电极远离栅线的一侧，在平行于数据线方向，第二补偿块在基底上的正投影包含漏电极远离栅线一侧的边缘在基底上的正投影的至少一部分，在平行于栅线方向，第二补偿块在基底上的正投影覆盖漏电极与像素电极之间重叠区域在远离栅线一侧边界基底上的正投影。
在又一个实施例中，连接电极还同时设置有第一补偿块和第二补偿块。
其中，在平行于基底平面，第一补偿块和第二补偿块的形状可以是矩形、梯形、半圆形或半椭圆形等形状。
有关阵列基板的具体制备过程，已在之前的实施例中详细说明，这里不再赘述。
本实施例提供了一种阵列基板的制备方法，通过一个转接过孔即实现了漏电极与像素电极之间的连接，相对于现有结构的双孔设计，本实施例有效减少了过孔数量，增加了显示面板的开口率。同时，本实施例提高了产品品质，提高了良品率。进一步地，本实施例构图次数与现有制备的构图次数相同，且工艺流程与现有制备工艺流程相同，因此本实施例的实施不需要改变现有工艺流程，不需改变现有工艺设备，工艺兼容性好，实用性强，具有良好的应用前景。
第五实施例
本公开实施例还提供了一种显示面板，包括前述的阵列基板。显示面板可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
应该注意的是，本公开中，“第一过孔部分暴露出漏电极，第二过孔部分暴露出像素电极”以及“连接过孔暴露出漏电极和像素电极”指的是形成连接电极之前连接过孔暴露漏电极和像素电极，以便于与连接电极连接，而在最终的产品中，连接过孔中是被填充了其他部件，例如连接电极，最终产品中并没有暴露漏电极和像素电极。
在平行于基底的平面中，连接过孔的形状可以是矩形、边缘修圆的矩形、椭圆形、圆形等形状，本公开的实施例并不对此进行限制。
本公开实施例提供了一种阵列基板及其制备方法、显示面板，通过一个转接过孔实现漏电极与像素电极之间的连接。相对于现有双孔结构，本公开实施例有效减少了过孔数量，增加了显示面板的开口率。同时，本公开实施例单孔结构消除了导致显示缺陷的因素，提高了产品品质，提高了良品率。实施本公开不需要改变现有工艺流程，不需改变现有工艺设备，工艺兼容性好，实用性强，具有良好的应用前景。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。本公开的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
在本公开实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间件间接相连，可以是两个元件内部的连通。 对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
本申请要求于2019年01月14日提交的中国专利申请第201910030803.4的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括：
    基底；
    设置在所述基底上的像素电极和薄膜晶体管；
    覆盖所述薄膜晶体管和所述像素电极的钝化层，所述钝化层上开设有同时暴露出所述像素电极和所述薄膜晶体管的漏电极或源电极的转接过孔；
    设置在所述钝化层上且在所述连接过孔处的连接电极，所述连接电极通过所述转接过孔与所述像素电极，和所述漏电极或所述源电极连接。
  2. 根据权利要求1所述的阵列基板，其中所述连接过孔在所述基底上的正投影与所述像素电极在所述基底上的正投影以及所述漏电极或源电极在所述基底上的正投影重叠。
  3. 根据权利要求1或2所述的阵列基板，还包括栅线和数据线，所述薄膜晶体管包括栅电极、有源层、源电极和漏电极，所述像素电极、栅线和栅电极设置在所述基底上，所述像素电极、所述栅线和所述栅电极上覆盖有栅绝缘层，所述有源层、源电极、漏电极和数据线设置在所述栅绝缘层上，所述源电极与漏电极之间形成导电沟道。
  4. 根据权利要求3所述的阵列基板，其中所述连接电极在邻近栅线的一侧设置有第一补偿块，第一补偿块在所述基底上的正投影包含所述漏电极或所述源电极邻近栅线一侧的边缘在基底上的正投影的至少一部分，和/或，所述连接电极远离栅线的一侧设置有第二补偿块，第二补偿块在基底上的正投影包含漏电极或源电极远离栅线一侧的边缘在基底上的正投影的至少一部分。
  5. 根据权利要求4所述的阵列基板，其中所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸。
  6. 根据权利要求5所述的阵列基板，其中所述连接电极在所述基底上的正投影覆盖所述漏电极或所述源电极与所述像素电极之间的重叠区域在所述基板上的正投影。
  7. 根据权利要求4-6中任一项所述的阵列基板，其中所述第一补偿块和/或第二补偿块的形状包括矩形、梯形、半圆形或半椭圆形。
  8. 根据权利要求1-7中任一所述的阵列基板，其中所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分暴露出所述漏电极，所述第二过孔部分暴露出所述像素电极。
  9. 一种显示面板，包括如权利要求1-8中任一所述的阵列基板。
  10. 一种阵列基板的制备方法，包括：
    形成像素电极和薄膜晶体管；
    形成覆盖所述薄膜晶体管的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极或源电极的转接过孔；
    在所述钝化层上且在所述连接过孔处形成连接电极，所述连接电极通过所述转接过孔同时与所述像素电极和漏电极或源电极连接。
  11. 根据权利要求10所述的制备方法，其中所述在基底上形成像素电极和薄膜晶体管，包括：
    通过一次构图工艺形成像素电极、栅线和栅电极；
    通过一次构图工艺形成栅绝缘层、有源层、源电极、漏电极和数据线，所述源电极与漏电极之间形成导电沟道。
  12. 根据权利要求10所述的制备方法，其中所述连接电极在邻近栅线的一侧设置有第一补偿块，第一补偿块在所述基底上的正投影包含所述漏电极或所述源电极邻近栅线一侧的边缘在基底上的正投影的至少一部分，和/或，所述连接电极远离栅线的一侧设置有第二补偿块，第二补偿块在基底上的正投影包含漏电极或源电极远离栅线一侧的边缘在基底上的正投影的至少一部分。
  13. 根据权利要求12所述的制备方法，其中所述第一补偿块从所述连接电极的主体朝向所述栅线延伸，所述第二补偿块从所述连接电极的主体向远离所述栅线的方向延伸，所述第一补偿块和所述第二补偿块在平行于所述栅线方向上的尺寸小于所述主体的尺寸。
  14. 根据权利要求10-14中任一所述的制备方法，其中所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分暴露出所述漏电极，所述第二过孔部分暴露出所述像素电极。
  15. 根据权利要求11所述的制备方法，其中通过一次构图工艺形成像素 电极、栅线和栅电极包括：
    在所述基底上依次沉积第一透明导电薄膜和第一金属薄膜；
    在第一金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在待形成所述栅线和栅电极的位置处形成未曝光区域，具有第一厚度的光刻胶，在待形成的像素电极的位置处形成部分曝光区域，具有第二厚度的光刻胶，在其它位置处形成完全曝光区域，无光刻胶，第一厚度大于第二厚度；
    通过第一次刻蚀工艺刻蚀掉完全曝光区域的所述第一金属薄膜和所述第一透明导电薄膜；
    通过灰化工艺去除所述部分曝光区域的光刻胶，暴露出所述第一金属薄膜；以及
    通过第二次刻蚀工艺刻蚀掉所述部分曝光区域的第一金属薄膜，剥离剩余的光刻胶，在基底上形成所述像素电极、栅线和栅电极。
  16. 根据权利要求11所述的制备方法，其中所述通过一次构图工艺形成栅绝缘层、有源层、源电极、漏电极和数据线，所述源电极与漏电极之间形成导电沟道包括：
    在形成有所述像素电极、栅线和栅电极的基底上依次沉积栅绝缘薄膜、半导体薄膜和第二金属薄膜；
    在第二金属薄膜上涂覆一层光刻胶，采用半色调或灰色调掩膜版对光刻胶进行阶梯曝光并显影，在待形成源电极、漏电极和数据线的位置处形成未曝光区域，具有第一厚度的光刻胶，在待形成导电沟道的位置处形成部分曝光区域，具有第二厚度的光刻胶，在其它位置处形成完全曝光区域，无光刻胶，第一厚度大于第二厚度；
    通过第一次刻蚀工艺刻蚀掉所述完全曝光区域的第二金属薄膜和半导体薄膜；
    通过灰化工艺去除所述部分曝光区域的光刻胶，暴露出第二金属薄膜；
    通过第二次刻蚀工艺刻蚀掉所述部分曝光区域的第二金属薄膜，剥离剩余的光刻胶，形成栅绝缘层、有源层、源电极、漏电极和数据线，源电极与漏电极之间形成导电沟道。
  17. 根据权利要求10所述的制备方法，其中形成覆盖所述薄膜晶体管的钝化层，所述钝化层上开设有同时暴露出像素电极和薄膜晶体管的漏电极或源电极的转接过孔包括：
    在形成有所述薄膜晶体管和所述像素电极的基底上沉积钝化薄膜；
    在钝化薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在转接过孔位置形成曝光区域，无光刻胶，在其它位置形成未曝光区域，保留光刻胶；
    通过刻蚀工艺刻蚀掉完全曝光区域的钝化薄膜和栅绝缘层，形成开设有转接过孔的钝化层，转接过孔同时暴露出漏电极和像素电极，
    其中，所述转接过孔包括第一过孔部分和第二过孔部分，所述第一过孔部分中的钝化层被刻蚀掉，暴露出所述漏电极，所述第二过孔部分中的钝化层和栅绝缘层被刻蚀掉，暴露出所述像素电极。
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