WO2022061767A1

WO2022061767A1 - Chip packaging structure, preparation method for chip packaging structure, and device interconnection system

Info

Publication number: WO2022061767A1
Application number: PCT/CN2020/117899
Authority: WO
Inventors: 代仁军; 周国名
Original assignee: 华为技术有限公司
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2022-03-31
Also published as: CN116235298A; CN116235298A8

Abstract

The embodiments of the present application relate to the technical field of chip heat dissipation and provide a chip packaging structure, a preparation method for the chip packaging structure, and a device interconnection system. The chip packaging structure comprises: a substrate, a chip, a plastic sealing layer, a heat dissipation channel, a first port and a second port, wherein the chip is integrated on a surface of the substrate; the plastic sealing layer covers the surface of the substrate and wraps the chip; the heat dissipation channel is located in the plastic sealing layer; and the first port and the second port are both provided in the plastic sealing layer, and are respectively in communication with the heat dissipation channel.

Description

Chip package structure, preparation method of chip package structure, and device interconnection system

technical field

The present application relates to the technical field of chip heat dissipation, and in particular, to a chip packaging structure, a preparation method of the chip packaging structure, and a device interconnection system.

Background technique

With the increase in the number and speed of chip cores, the power consumption of the chip is getting higher and higher, so the problem of chip heat dissipation is particularly prominent. At present, there are two main ways to dissipate heat from the chip. One is air cooling, which uses flowing airflow to dissipate the heat emitted by the chip; the other is liquid cooling, which uses flowing water to dissipate heat from the chip.

FIG. 1 is an existing liquid-cooled heat dissipation structure. The heat dissipation structure includes a heat-absorbing copper base 1. A heat-dissipating water channel 2 that can flow through water is formed in the heat-absorbing copper base 1. The heat-dissipating water channel 2 and the liquid inlet end 3 and the outlet The liquid end 4 is connected.

2 is the application of the liquid cooling structure of FIG. 1 to the chip heat dissipation structure, wherein the heat absorbing copper base 1 is in contact with the surface of the heat dissipation cover 8 on the chip 7 , and the chip 7 is integrated on the surface of the substrate 5 . In this case, the heat dissipated by the chip 7 will pass through the plastic sealing layer 6 and the heat dissipation cover 8, and then the heat will be driven by the water flowing in the heat dissipation water channel 2, so as to realize the cooling of the chip.

When the liquid cooling structure dissipates heat to the chip, the heat dissipation path between the heat source chip 7 and the heat dissipation water channel 2 is relatively long, and needs to pass through the plastic sealing layer 6 and the heat dissipation cover 8 . Since the plastic sealing layer 6 and the heat dissipation cover 8 will generate a large thermal resistance, the heat dissipation efficiency of the chip will be seriously affected.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a chip package structure, a method for manufacturing the chip package structure, and a device interconnection system. The main purpose is to shorten the heat dissipation path and improve the heat dissipation efficiency of the chip.

To achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the present application provides a chip packaging structure, the chip packaging structure includes: a substrate, a chip and a plastic packaging layer, a heat dissipation channel, and a first port and a second port; wherein the chip is integrated on the surface of the substrate, and the plastic packaging layer The surface of the substrate is covered and the chip is wrapped, the heat dissipation channel is located in the plastic sealing layer, the first port and the second port are both opened on the plastic sealing layer, and are respectively communicated with the heat dissipation channel.

In the chip packaging structure provided by the embodiments of the present application, the heat dissipation channel is arranged in the plastic packaging layer. Compared with the existing solution of disposing the heat dissipation channel on the surface of the heat dissipation cover, the present application significantly shortens the path between the heat source chip and the heat dissipation channel, so that the heat dissipated by the chip can be transferred to the heat dissipation path through the heat dissipation path with low thermal resistance. The cooling medium flowing in the heat dissipation channel improves the heat dissipation efficiency of the chip. In addition, since the heat dissipation channel is arranged in the plastic sealing layer, the requirement for the external heat dissipation space of the entire chip packaging structure is reduced, and the utilization rate of the external space is improved.

In a possible implementation manner of the first aspect, the heat dissipation channel is disposed close to the chip. By placing the heat dissipation channel close to the chip, the heat dissipation path will be further shortened and the heat dissipation efficiency will be improved.

In a possible implementation manner of the first aspect, the heat dissipation channel is disposed above the upper surface of the chip, and the heat dissipation channel extends along the upper surface of the chip. Usually, the heat on the upper surface of the chip is relatively large, so the heat dissipation channel is arranged above the upper surface of the chip, and the heat dissipation channel extends along the upper surface of the chip, which will quickly dissipate the heat on the upper surface of the chip. The channel is arranged above the upper surface of the chip, which is also convenient to implement from the aspect of the manufacturing process.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation pipe embedded in the plastic sealing layer, and the heat dissipation pipe is in contact with the upper surface of the chip. In this way, the cooling medium and the chip are only separated by the pipe wall of the heat dissipation pipe, and the heat dissipation efficiency is higher.

In a possible implementation manner of the first aspect, the chip packaging structure further includes: a heat dissipation cover covering the surface of the plastic sealing layer; the heat dissipation channel is a heat dissipation pipe embedded in the plastic sealing layer and connected to the heat dissipation cover. On the premise of effectively improving the heat dissipation efficiency, the heat dissipation structure is convenient for manufacture and implementation.

In a possible implementation manner of the first aspect, the heat dissipation pipe connected to the heat dissipation cover is in contact with the upper surface of the chip. By contacting the heat dissipation pipe with the upper surface of the chip, the cooling medium and the chip are only separated by the pipe wall of the heat dissipation pipe, and the heat dissipation efficiency is high.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation groove opened on a surface of the plastic encapsulation layer close to the upper surface of the chip. In this case, the cooling medium is in direct contact with the chip, which will further improve the heat dissipation effect. The cooling medium needs to be a non-conductive medium that cannot corrode the chip.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation cavity opened in the plastic sealing layer.

In a possible implementation manner of the first aspect, a heat dissipation channel is also formed inside a portion of the plastic sealing layer covering the surface of the substrate. Since metal traces are integrated on the substrate, the metal traces will also dissipate heat during operation, and at the same time, the heat dissipated by the chip will also be conducted to the substrate. The substrate is rapidly dissipated and cooled to improve the heat dissipation effect of the entire chip package structure.

In a possible implementation manner of the first aspect, there are multiple heat dissipation channels, the multiple heat dissipation channels are located in the same plane, and the surface on which the multiple heat dissipation channels are located is parallel to the upper surface of the chip. By arranging multiple heat dissipation channels, the heat conduction area will be increased, and the heat dissipation efficiency will be further improved.

In a possible implementation manner of the first aspect, multiple heat dissipation channels share a first port and share a second port. Using one first port and one second port can simplify the structure of the entire chip package structure.

In a possible implementation manner of the first aspect, the cross section of the heat dissipation channel is a flat structure. Setting the cross-section of the heat dissipation channel into a flat structure can increase the contact area with the plastic sealing layer, thereby increasing the heat conduction area and improving the heat dissipation efficiency.

In a second aspect, the present application provides a preparation method of a chip packaging structure, the preparation method comprising:

relatively fixing the forming member and the substrate with integrated chip;

A plastic encapsulation layer is formed so that the plastic encapsulation layer encapsulates the chip and the forming member, and the forming member is used to assist in forming the heat dissipation channel.

In the preparation method of the chip package structure provided by the embodiment of the present application, the heat dissipation channel can be assisted to form by the forming member, and the heat dissipation channel is located in the plastic sealing layer. Compared with the existing solution of arranging the heat dissipation channel on the surface of the heat dissipation cover, the present application significantly shortens the path between the chip and the heat dissipation channel, so that the heat dissipated by the chip is transferred to the heat dissipation path through the heat dissipation path with low thermal resistance. The cooling medium in the channel, thereby improving the heat dissipation efficiency of the chip. In addition, since the heat dissipation channel is arranged in the plastic sealing layer, the requirement for the external heat dissipation space of the entire chip packaging structure is reduced, and the utilization rate of the external space is improved.

In a possible implementation manner of the second aspect, the forming member is a heat dissipation pipe; the relatively fixing of the forming member and the substrate integrated with the chip includes: laying at least one heat dissipation pipe on the upper surface of the chip. Before injection molding, a heat dissipation pipe is arranged on the upper surface of the chip, and finally the heat dissipation pipe is formed in the plastic sealing layer to form a heat dissipation channel, and the heat dissipation pipe is close to the upper surface of the chip. The process is not only simple, but also the cooling medium in the heat pipe and the chip are only separated by the pipe wall of the heat pipe, and the heat dissipation efficiency is high.

In a possible implementation manner of the second aspect, the forming member is a heat dissipation pipe; the relatively fixing of the forming member to the chip-integrated substrate includes: relatively fixing the heat dissipation cover to the chip-integrated substrate, and the heat dissipation cover faces the upper surface of the chip A heat pipe is attached to the side of the . By connecting the heat pipe with the heat dissipation cover, the heat pipe forms a heat dissipation channel. And the process is convenient to implement.

In a possible implementation manner of the second aspect, the heat dissipation cover is relatively fixed to the substrate integrated with the chip, and a heat dissipation pipe is connected to the side of the heat dissipation cover facing the upper surface of the chip, including: disposing the heat dissipation cover connected with the heat dissipation pipe on a The plastic sealing mold is placed in the injection groove of the plastic sealing mold; the plastic sealing mold is placed on the surface of the chip-integrated substrate, so that the heat dissipation cover connected with the heat-dissipating pipe and the chip-integrated substrate are relatively fixed. The heat dissipation cover connected with the heat dissipation pipe is directly set in the plastic sealing mold, and the heat dissipation cover and the substrate are relatively fixed by the plastic sealing mold. In this way, after the injection molding material is injected into the injection groove, the heat dissipation pipe will be directly embedded in the plastic sealing layer. inside, and the heat dissipation cover is connected with the plastic encapsulation layer.

In a possible implementation manner of the second aspect, the forming part is a core mold that needs to be removed; after the molding layer is formed, the preparation method further includes: removing the core mold to form a heat dissipation channel in the molding layer.

In a possible implementation manner of the second aspect, relatively fixing the forming member to the substrate integrated with the chip includes: arranging the core mold in the injection groove of the plastic sealing mold, and the core mold extends along the upper surface of the chip; The plastic encapsulation mold of the core mold is placed on the surface of the substrate integrated with the chip, and the core mold is in contact with the upper surface of the chip. In this case, after the core mold is removed, the formed heat dissipation channel is a heat dissipation groove opened on the surface of the plastic packaging layer close to the upper surface of the chip.

In a possible implementation manner of the second aspect, relatively fixing the forming member to the substrate integrated with the chip includes: arranging the core mold in the injection groove of the plastic sealing mold, and the core mold extends along the upper surface of the chip; The plastic encapsulation mold of the core mold is placed on the surface of the substrate integrated with the chip, and there is a gap between the core mold and the upper surface of the chip. In this way, after the core mold is removed, the formed heat dissipation channel is a heat dissipation cavity opened in the plastic sealing layer.

In a possible implementation manner of the second aspect, the relatively fixing of the forming member to the chip-integrated substrate includes: relatively fixing a plurality of forming members to the chip-integrated substrate, the plurality of forming members are located in the same plane, and the plurality of forming members are located in the same plane. The face on which the formation is located is parallel to the top surface of the chip. By arranging a plurality of forming parts, a plurality of heat dissipation channels will be formed, so as to further improve the heat dissipation efficiency.

In a third aspect, the present application further provides a device interconnection system, including a cabinet and the chip packaging structure in any implementation manner of the above-mentioned first aspect or the chip packaging structure obtained by any implementation manner of the above-mentioned second aspect. The structure is set on the cabinet.

The device interconnection system provided by the embodiment of the present application includes the chip packaging structure of the above-mentioned embodiment. Therefore, the device interconnection system provided by the embodiment of the present application and the chip packaging structure of the above-mentioned technical solution can solve the same technical problem and achieve the same expectation. Effect.

Description of drawings

1 is a schematic diagram of a heat dissipation structure in the prior art;

FIG. 2 is a schematic diagram of applying the heat dissipation structure shown in FIG. 1 to a chip packaging structure;

3 is a partial structural diagram of a device interconnection system according to an embodiment of the application;

4 is a schematic diagram of a connection relationship between a chip packaging structure and a PCB according to an embodiment of the application;

FIG. 5 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;

6 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;

7 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a chip packaging structure according to an embodiment of the present application;

9a is a cross-sectional view of a heat dissipation channel according to an embodiment of the application;

9b is a cross-sectional view of a heat dissipation channel according to an embodiment of the application;

9c is a cross-sectional view of a heat dissipation channel according to an embodiment of the present application;

FIG. 10 is another perspective view of the chip packaging structure according to the embodiment of the application;

11 is a schematic diagram of a chip packaging structure according to an embodiment of the application;

Fig. 12 is the A-A sectional view of Fig. 11;

Fig. 13 is the B-B sectional view of Fig. 11;

FIG. 14 is another cross-sectional view of the chip package structure according to the embodiment of the application;

15 is a schematic diagram of a chip packaging structure according to an embodiment of the application;

Fig. 16 is the C-C sectional view of Fig. 15;

FIG. 17 is another cross-sectional view of the chip packaging structure according to the embodiment of the application;

18 is a schematic diagram of a chip packaging structure according to an embodiment of the application;

Fig. 19 is the D-D sectional view of Fig. 18;

Fig. 20 is the E-E sectional view of Fig. 18;

21 is a schematic diagram of a chip packaging structure according to an embodiment of the application;

Fig. 22 is the F-F sectional view of Fig. 21;

Figure 23 is a G-G sectional view of Figure 21;

24 is a flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present application;

25 is a flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present application;

FIG. 26 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application;

27 is a schematic structural diagram of a plastic packaging mold used in the method for preparing a chip packaging structure according to an embodiment of the present application;

28 is a flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present application;

FIG. 29 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application;

30 is a flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present application;

FIG. 31 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application;

32 is a schematic structural diagram of a plastic packaging mold and a core mold used in a method for preparing a chip packaging structure according to an embodiment of the present application;

33 is a flowchart of a method for manufacturing a chip packaging structure according to an embodiment of the present application;

FIG. 34 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application;

FIG. 35 is a schematic structural diagram of a plastic packaging mold and a core mold used in a method for manufacturing a chip packaging structure according to an embodiment of the present application.

Reference number:

1- heat-absorbing copper seat; 2- cooling water channel; 3- liquid inlet; 4- liquid outlet; 5- substrate; 6- plastic sealing layer; 61- cooling channel; 611- cooling pipe; 612- cooling groove; 613- Heat dissipation cavity; 7-chip; 8-heat dissipation cover; 01-chip packaging structure; 02-PCB; 03-electrical connection structure; 04-cabinet; 9-first port; 10-second port; 11-plastic encapsulation mold; 110 -Injection slot; 112-Core mold; 113-Slot; 12-Moulding material.

detailed description

In the equipment interconnection system, as shown in Figures 3 and 4, it includes a cabinet 04, a printed circuit board (PCB) 02 carried on the cabinet 04, and a chip package structure 01 integrated on the PCB02. The package structure 01 is electrically connected to the PCB02 through the electrical connection structure 03 . Thus, the chip package structure 01 can realize signal transmission with other chips or other modules on the PCB 02 .

The electrical connection structure 03 may be a ball grid array (BGA), a copper pillar bump (copper pillar bump) arranged in a plurality of arrays, or a connector (socket).

The above-mentioned equipment interconnection system may include a server (server), a data center (Data Center), or other large-scale interconnection equipment.

In these large-scale device interconnection systems, as the number of chip cores and computing speed increase, the heat dissipated is also increasing. In order to improve the heat dissipation efficiency, and then improve the performance of the device interconnection system.

The present application provides a chip package structure 01 with a heat dissipation structure, and the chip package structure 01 is explained in detail below.

5 is a schematic diagram of a chip package structure 01 , which includes a substrate 5 and a chip 7 integrated on the surface of the substrate 5 . In order to improve the strength of the entire chip package structure 01 and to protect and reinforce the chip 7 integrated on the substrate 5 , as shown in FIG. 5 , the surface of the substrate 5 is covered with a plastic sealing layer 6 , which wraps the chip 7 . The plastic sealing layer 6 is made of insulating materials such as resin materials.

In the chip package structure 01 shown in FIG. 5 , only one chip is shown, and in an actual structure, a plurality of chips integrated on the surface of the substrate 5 may be included.

The above-mentioned chip 7 may be a wafer, a die obtained by cutting the wafer, or a plurality of stacked dies.

In addition, bosses are formed on the surface P1 of the molding layer 6 shown in FIG. 5 at the position where the chip 7 is located. In an alternative embodiment, as shown in FIG. 6 , the surface P1 of the plastic sealing layer 6 may also be flat. The present application does not make any special limitation on the outer contour shape of the plastic encapsulation layer 6 .

The chip package structure 01 shown in FIG. 7 further includes a heat dissipation channel 61 , the heat dissipation channel 61 is located in the plastic sealing layer 6 , and a cooling medium can flow through the heat dissipation channel 61 . In this way, the heat dissipated by the chip 7 will be conducted into the plastic sealing layer 6 , and the heat will be taken away by the cooling medium flowing in the heat dissipation channel 61 , so as to realize the heat dissipation and cooling of the chip 7 .

In addition, the plastic sealing layer 6 is also provided with a first port and a second port which are communicated with the heat dissipation channel 61 . For example, when the first port is the inlet and the second port is the outlet, the cooling medium flowing in from the first port will absorb the heat radiated by the chip 7 and be discharged through the second port.

It can be seen from FIG. 7 that the heat dissipation channel 61 is located in the plastic sealing layer 6 . In this way, compared with the existing heat dissipation structure disposed above the heat dissipation cover, the heat dissipation path will be significantly shortened, and the chip 7 can be transferred to the cooling medium located in the heat dissipation channel 61 through the heat dissipation path with low thermal resistance, so as to improve the performance of the cooling medium. cooling efficiency.

In addition, compared with the prior art, under the premise that the power of the brake pump used to provide pressure to the cooling medium is the same and the flow rate of the cooling medium is the same, more heat can be dissipated to the chip, so that the chip can work at At higher frequencies, the performance of the chip can be better played.

The cooling medium referred to in this application may be a gas, such as air. It can also be a liquid, such as water. Of course, other refrigerating gases or refrigerating liquids can also be selected. Alternatively, the cooling medium can be liquid at the inlet, and after absorbing heat in the heat dissipation channel, it becomes gas and flows out from the outlet.

In an alternative embodiment, referring to FIG. 7 , the heat dissipation channel 61 is close to the chip 7 , is located above the upper surface M1 of the chip 7 , and extends along the upper surface of the chip 7 , which further shortens the heat dissipation path. In order to further improve the heat dissipation effect on the chip 7, as shown in FIG. 8, a heat dissipation channel 61 can also be formed at the position of the plastic sealing layer 6 close to the side M2 of the chip 7. In this way, the heat dissipation of the chip 7 can be dissipated from multiple surfaces, and the heat dissipation effect is also improved. will be significantly increased accordingly.

It should be noted that the chip upper surface M1 referred to in this application refers to the surface of the chip 7 that is far from the substrate 5 . The chip side M2 refers to the side adjacent to the upper surface M1.

On the substrate 5, there will be metal traces to electrically connect the chips 7 that need to be interconnected. When the chips 7 are working, the metal traces will emit a large amount of heat. In addition, part of the heat on the chip 7 is also conducted to the substrate 5 . In order to dissipate heat to the substrate 5 , as shown in FIG. 8 , a heat dissipation channel 61 is also formed in the part of the plastic sealing layer 6 covering the surface of the substrate 5 , that is, through the cooling in the heat dissipation channel 61 located above the substrate 5 . The medium takes away the heat dissipated by the substrate 5 .

Therefore, it can be seen from the structure shown in FIG. 8 that the heat dissipation structure involved in the present application can not only achieve multi-directional heat dissipation for the chip 7 , but also has a heat dissipation effect on the substrate 5 . In this way, the heat dissipation effect of the entire chip structure 01 will be significantly improved.

The cross section of the heat dissipation channel may be a circular structure or a flat structure. Besides, the cross section of the heat dissipation channel can also be in other shapes.

Fig. 9a shows a heat dissipation channel with an elliptical cross section, Fig. 9b shows a heat dissipation channel with a rectangular cross section, and Fig. 9c shows a heat dissipation channel with a trapezoidal cross section. In FIGS. 9a and 9b, the dimension shown by S1 is the dimension parallel to the direction of the upper surface of the chip, and the dimension shown by S2 is the dimension of the direction perpendicular to the upper surface of the chip. And S1 is greater than S2 to form a flat structure. In Figure 9c, the lower bottom surface of the trapezoidal structure is close to the chip.

In FIG. 9a, FIG. 9b and FIG. 9c, since the wall surface of the heat dissipation channel close to the chip has a larger heat conduction area, the heat dissipation effect will be correspondingly improved.

In an alternative embodiment, if a plurality of chips are integrated on the substrate, a plurality of heat dissipation channels for dissipating heat for the plurality of chips can be connected in series.

The above-mentioned heat dissipation channels may exist in various layouts. In an alternative embodiment, referring to FIG. 10 , a plurality of heat dissipation channels 61 on the upper surface of the chip are arranged in parallel, and the plurality of heat dissipation channels 61 are in the same plane, and the plane is parallel to the upper surface of the chip. Each heat dissipation channel extends in a straight line. In another optional embodiment, the heat dissipation channel 61 may also extend in a curve to increase the heat conduction area, and it may also ensure that the flow of the cooling medium is uniform everywhere, so as to achieve the effect of uniform heat dissipation. If there are multiple heat dissipation channels extending above the substrate, the heat dissipation channels located at the position are also arranged in parallel.

In order to simplify the structure, as shown in FIG. 10 , there is only one first port 9 opened on the plastic sealing layer, and only one second port 10 opened on the plastic sealing layer. In this way, the cooling medium entering from a first port 9 will be divided into multiple branches and enter the heat dissipation channel, and the cooling medium carrying heat will be merged through the heat dissipation channels of the multiple branches and discharged from a second port 10 . In an alternative embodiment, the number of the first port 9 and the second port 10 may be multiple, respectively.

In order to further improve the heat dissipation effect, the device interconnection system may further include a cooling structure, and the cooling structure is used to cool down the cooling medium entering the heat dissipation channel. In this way, by introducing a cooling medium with a lower temperature into the heat dissipation channel, a larger temperature difference can be achieved and a better cooling effect can be achieved.

If the cooling medium is gas, the refrigeration structure can be a refrigeration air conditioner. If the cooling medium is liquid, the cooling structure can use a cooling tower. In alternative embodiments, other structures capable of refrigerating gas or liquid may also be used.

The arrangement positions of the first port 9 and the second port 10 , as shown in FIG. 10 , can be arranged on the side surface of the plastic sealing layer 6 . It can also be arranged on the top surface of the plastic encapsulation layer. The present application does not specifically limit the setting positions of the first port 9 and the second port 10 .

There are various achievable structures for forming the heat dissipation channel 61 , and the present application provides several possible implementation manners, which will be introduced separately below.

11 and 12 , a structure for forming a heat dissipation channel is given. The heat dissipation channel is a heat dissipation pipe 611 embedded in the plastic sealing layer 6 , and the heat dissipation pipe 611 is in contact with the upper surface of the chip 7 .

Since the heat dissipation pipe 611 is close to the upper surface of the chip 7 , that is, the heat dissipation path between the chip and the cooling medium only includes the wall thickness of the heat dissipation pipe, which shortens the heat dissipation path and reduces the thermal resistance. After the cooling medium is introduced into the heat dissipation pipe 611 , the heat dissipated by the chip 7 will be quickly conducted to the heat dissipation pipe 611 , so that the cooling medium can take away the heat.

The material of the heat pipe can be made of copper, iron, etc. with high thermal conductivity.

FIG. 13 is a cross-sectional view taken along line B-B of FIG. 11 . It can be seen from this figure that the heat dissipation pipe 611 extends to the top of the substrate 5 , and the heat dissipation pipe 611 is close to the substrate 5 . The heat on the substrate 5 will diffuse to the heat dissipation pipe 611 as soon as possible, and be carried away by the cooling medium circulating in the heat dissipation pipe 611 .

The cross section of the heat dissipation pipe 611 shown in FIG. 13 is a circular structure. The cross section of the heat dissipation pipe 611 shown in FIG. 14 is an elliptical structure.

In the chip package structure shown in FIG. 11 to FIG. 14 , a heat dissipation cover may also be included, and the heat dissipation cover covers the surface of the plastic sealing layer. It is also possible not to include a heat dissipation cover.

The material of the heat dissipation cover can be selected from metals such as iron and aluminum. In this case, the heat dissipation effect can be increased through the metal heat dissipation cover. In addition, the heat dissipation cover can also dissipate heat evenly for better heat dissipation.

15 and 16, another formation structure of the heat dissipation channel is given. The surface of the plastic sealing layer 6 is covered with a heat dissipation cover 8, and the heat dissipation channel is a heat dissipation channel embedded in the plastic sealing layer 6 and connected to the heat dissipation cover 8. Tube 611.

In an alternative embodiment, the heat dissipation cover 8 is an injection molded part, and the heat dissipation pipe 611 can be integrally formed with the heat dissipation cover 8 . In another alternative embodiment, the heat dissipation pipe 611 is fixedly connected with the heat dissipation cover 8 through a connection structure (eg, welding).

In the structure shown in FIG. 15 and FIG. 16 , the heat dissipation pipe 611 is located in the plastic sealing layer 6 and is close to the chip 7 . The heat dissipated by the chip 7 is quickly transferred to the cooling medium flowing in the heat dissipation pipe.

The heat pipe 611 shown in FIG. 16 is not in contact with the upper surface of the chip 7 but has a gap. The wall surface of the heat pipe 611 shown in FIG. 17 close to the upper surface of the chip 7 is attached to the upper surface of the chip 7 . Thus, the heat dissipation path will be further shortened and the heat dissipation efficiency will be improved.

Referring to FIGS. 18 and 19 , another structure for forming a heat dissipation channel is given, and the heat dissipation channel is a heat dissipation cavity 613 opened in the plastic sealing layer 6 . It can be seen from Fig. 19 that there is a layer of plastic encapsulation layer structure between the heat dissipation cavity 613 and the chip 7.

FIG. 20 is a cross-sectional view at E-E of FIG. 18 . It can be seen from this figure that the heat dissipation cavity 613 extends above the substrate 5 , that is, the heat dissipation cavity 613 and the substrate 5 are also separated by a layer of plastic sealing layer 6 .

In the above-mentioned structures shown in FIG. 7 and FIG. 15 using the heat dissipation pipe as the heat dissipation channel, the cooling medium flowing in the heat dissipation pipe and the chip are separated by at least the pipe wall of the heat dissipation pipe. In the structure shown in FIG. 18 using a heat dissipation cavity as a heat dissipation channel, the cooling medium flowing in the heat dissipation cavity and the chip are separated by a plastic sealing layer. Therefore, there is no special limitation on the cooling medium. Even if a corrosive or conductive medium is used as the cooling medium, it will not cause damage to the chip and affect the performance of the chip.

Referring to FIGS. 21 and 22 , another formation structure of the heat dissipation channel is given, and the heat dissipation channel is a heat dissipation groove 612 opened on the surface of the plastic sealing layer 6 close to the upper surface of the chip 7 . It can also be understood in this way. It can be seen from FIG. 21 that the heat dissipation groove 612 penetrates to the surface of the plastic sealing layer 6 that is close to the chip 7 .

In this case, the cooling medium flowing in the heat dissipation slot 612 will directly contact the chip 7. In order to protect the chip, a non-corrosive and non-conductive cooling medium should be selected.

FIG. 23 is a cross-sectional view at G-G in FIG. 21 . It can be seen from this figure that the heat dissipation groove 612 extends to the top of the substrate 5 , and the heat dissipation groove 612 also penetrates to the surface of the plastic sealing layer 6 close to the substrate 5 . Therefore, a non-corrosive and non-conductive cooling medium needs to be selected to prevent damage to the substrate. When there are multiple chips, when this heat dissipation structure is adopted, the electrical connection of chips that do not require electrical connection is not promoted because the cooling medium is conductive, which affects the performance of the chip packaging structure. Likewise, the cooling medium circulating in the heat dissipation slot 612 will not cause damage to chips, metal traces or other modules on the substrate.

The above are only some examples of the heat dissipation channel. For example, the heat dissipation channel may also include: a heat dissipation pipe embedded in the plastic sealing layer, and a heat dissipation cavity opened in the plastic sealing layer. It may also include: a heat dissipation groove opened on the surface of the plastic sealing layer close to the upper surface of the chip, and a heat dissipation pipe connected with the heat dissipation cover.

The embodiment of the present application also provides a method for preparing a chip packaging structure. Referring to FIG. 24 , the preparation method includes the following steps:

S1, relatively fixing the forming member and the substrate on which the chip is integrated.

S2, forming a plastic encapsulation layer, so that the plastic encapsulation layer wraps the chip and the forming part, and the forming part is used to assist in forming a heat dissipation channel.

The structure of the formed member is different, and the structure of the formed heat dissipation channel is different. For example, the forming member may be a heat dissipation pipe, which ultimately forms a heat dissipation channel. The forming part may also be a core mold that needs to be removed, and the space after the core mold is removed forms a heat dissipation channel.

The corresponding preparation methods when using different structural forming members are explained in detail below.

In addition, in the process of forming the plastic sealing layer, a plastic sealing mold can be used to complete, and the shape of the plastic sealing layer is different depending on the shape of the plastic sealing layer.

When the formed heat dissipation channel is a heat dissipation pipe, the method for preparing the chip package structure includes the following steps:

In step S101 of FIG. 25 and 26 a of FIG. 26 , at least one heat pipe 611 is arranged on the upper surface of the chip 7 .

When forming the plastic sealing layer again, it can be completed by using the plastic sealing mold 11 shown in FIG. 27 . The plastic sealing mold 11 has an injection groove 110 and a groove 113 that communicates with the injection groove 110. During the specific preparation, the groove 113 is buckled. on the surface of the substrate.

In step S102 of FIG. 25 and 26b of FIG. 26 , the mold 11 is placed on the surface of the substrate 5 integrated with the chip 7 so that the heat pipe 611 and the chip 7 are located in the injection groove 110 of the mold 11.

In step S103 of FIG. 25 and 26 c of FIG. 26 , the molding material 12 is injected into the injection groove 110 .

After the injection molding of the molding material is completed, it is usually necessary to apply pressure, so that the density of the molding material is higher and the sealing effect is better.

As shown in step S104 of FIG. 25 and 26d of FIG. 26 , the plastic sealing mold 11 is removed to form the plastic sealing layer 6 on the surface of the substrate 5 , and the plastic sealing layer 6 wraps the chip 7 , and the plastic sealing layer 6 is disposed close to the surface of the chip 7 . There are heat pipes 611 .

That is to say, before plastic sealing, the heat pipe is firstly arranged on the upper surface of the chip, and then the injection molding process is performed, so that the heat pipe is arranged in the formed plastic sealing layer. The manufacturing process is simple and the implementation is convenient. In addition, the heat dissipation pipe is directly in contact with the upper surface of the chip, the heat dissipation path is short, and the heat dissipation effect is good.

When the formed heat dissipation channel is a heat dissipation pipe, the method for preparing the chip package structure may also include the following steps:

As shown in step S201 of FIG. 28 and 29a of FIG. 29 , the heat dissipation cover 8 is set in the plastic sealing mold 11 , and a heat dissipation pipe 611 is connected to the side of the heat dissipation cover 8 facing the chip. The plastic sealing mold 11 may adopt the plastic sealing mold structure shown in FIG. 27 .

As shown in step S202 in FIG. 28 and 29b in FIG. 29 , the plastic sealing mold 11 is placed on the surface of the substrate 5 integrated with the chip 7 , so that the heat dissipation cover 8 connected with the heat pipe 611 and the chip 7 are located on the surface of the plastic sealing mold 11 . into the injection groove 110 .

In step S203 of FIG. 28 and 29c of FIG. 29 , the molding material 12 is injected into the injection groove 110 .

As shown in step S204 of FIG. 28 and 29d of FIG. 29 , the plastic sealing mold 11 is removed to form the plastic sealing layer 6 on the surface of the substrate 5 , and the plastic sealing layer 6 wraps the chip 7 , and the heat dissipation cover 8 is provided on the upper surface of the chip close to the chip There are heat pipes 611 .

The preparation method is that before plastic sealing, the heat dissipation cover connected with the heat dissipation pipe is first set in the plastic sealing mold, and then the plastic sealing mold including the heat dissipation cover and the heat dissipation pipe is placed on the base plate, and then the injection molding process is carried out. The heat dissipation pipe is arranged in the formed plastic encapsulation layer. The manufacturing process is also simple and the implementation is convenient.

When the formed part is a core mold that needs to be removed, the following method can be used to prepare the chip package structure.

As shown in step S301 of FIG. 30 and 31a of FIG. 31 , the plastic sealing mold 11 is placed on the surface of the substrate 5 integrated with the chip 7 , so that the chip 7 is located in the injection groove 110 of the plastic sealing mold 11 , and the injection groove 110 is provided with There is at least one core mold 112 extending along the upper surface of the chip 7 , and there is a space between the core mold 112 and the upper surface of the chip 7 .

FIG. 32 is a diagram showing the connection relationship between the plastic sealing mold 11 and the core mold 112 in the preparation method. Referring to FIG. 31 and FIG. 32 , if there is a distance between the core mold 112 and the upper surface of the chip 7 , the core mold 112 and the notch 113 The distance between a1 and the thickness dimension of the chip 7 is a2, and a1 is greater than a2.

In step S302 of FIG. 30 , and 31 b of FIG. 31 , the molding material 12 is injected into the injection tank, so that the molding material 12 is filled in the injection tank at positions other than the core mold 112 .

As shown in step S303 of FIG. 30 and 31 c of FIG. 31 , the plastic sealing mold 11 is removed, and the core mold 112 is removed to form the plastic sealing layer 6 on the surface of the substrate 5 , and the plastic sealing layer 6 wraps the chip 7 , and the plastic sealing layer 6 A heat dissipation cavity 613 is formed.

Since the distance between the core mold disposed in the injection groove and the notch is greater than the thickness of the chip, there is a plastic sealing material between the finally formed heat dissipation cavity 613 and the surface of the chip 7 .

The above-mentioned core mold 112 can be a bag filled with gas. Before injection molding, the bag filled with gas is placed in the injection groove, and then the plastic sealing material is injected. Pull out the bag to form a cooling cavity. Of course, the core mold of this structure is only an example, and other structures can also be used. For example, a chemical may be used to chemically react with the mandrel so that the mandrel is removed.

When the formed part is a core mold that needs to be removed, the following method can also be used to prepare the chip package structure.

As shown in step S401 of FIG. 33 and 34a of FIG. 34 , the plastic sealing mold 11 is placed on the surface of the substrate 5 integrated with the chip 7 , so that the chip 7 is located in the injection groove 110 of the plastic sealing mold 11 , and the injection groove 110 is provided with There is at least one core mold 112 extending along the upper surface of the chip 7 , and the core mold 112 is in contact with the upper surface of the chip 7 .

FIG. 35 is a diagram showing the connection relationship between the plastic sealing mold 11 and the core mold 112 in the preparation method. Referring to FIG. 34 and FIG. 35 , if the core mold 112 needs to be in contact with the upper surface of the chip 7 , the connection between the core mold 112 and the notch 113 is required. At the distance a1, the thickness dimension of the chip 7 is a2, and a1 is equal to a2.

In step S402 of FIG. 33 , and 34 b of FIG. 34 , the molding material 12 is injected into the injection tank, so that the molding material 12 is filled in the injection tank at positions other than the core mold 112 .

As shown in step S403 of FIG. 33 and 34c of FIG. 34 , the plastic sealing mold 11 and the core mold 112 are removed to form the plastic sealing layer 6 on the surface of the substrate 5 , and the plastic sealing layer 6 wraps the chip 7 . The heat dissipation groove 612 on the surface close to the upper surface of the chip 7 .

In order to increase the number of heat dissipation channels and improve the heat dissipation efficiency, whether the forming part is a heat dissipation pipe or a core mold, multiple forming parts can be provided. As shown in FIG. 32 and FIG. And the surface on which the plurality of forming parts 112 are located is parallel to the upper surface of the chip. Further, a plurality of parallel heat dissipation channels are formed.

In the description of this specification, the particular features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only specific implementations of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A chip packaging structure, characterized in that it includes:

substrate;

a chip, integrated on the surface of the substrate;

a plastic sealing layer covering the surface of the substrate and wrapping the chip;

a heat dissipation channel, located in the plastic sealing layer;

The first port and the second port are both opened on the plastic sealing layer and communicated with the heat dissipation channel respectively.
The chip package structure according to claim 1, wherein the heat dissipation channel is disposed close to the chip.
The chip package structure according to claim 1 or 2, wherein the heat dissipation channel is disposed above the upper surface of the chip, and the heat dissipation channel extends along the upper surface of the chip.
The chip packaging structure according to any one of claims 1-3, wherein the heat dissipation channel is a heat dissipation pipe embedded in the plastic sealing layer, and the heat dissipation pipe is in contact with the upper surface of the chip.
The chip packaging structure according to any one of claims 1-4, wherein the chip packaging structure further comprises:

a heat dissipation cover, covering the surface of the plastic sealing layer;

The heat dissipation channel is a heat dissipation pipe embedded in the plastic sealing layer and connected with the heat dissipation cover.
The chip packaging structure according to any one of claims 1-5, wherein the heat dissipation channel is a heat dissipation groove opened on a surface of the plastic sealing layer close to the upper surface of the chip.
The chip packaging structure according to any one of claims 1-6, wherein the heat dissipation channel is a heat dissipation cavity opened in the plastic sealing layer.
The chip packaging structure according to any one of claims 1 to 7, wherein the heat dissipation channel is also formed in the interior of the part of the plastic packaging layer covering the surface of the substrate.
The chip package structure according to any one of claims 1 to 8, wherein there are multiple heat dissipation channels, the multiple heat dissipation channels are located in the same plane, and the plurality of heat dissipation channels are located in the same plane. The face is parallel to the upper surface of the chip.
The chip package structure according to claim 9, wherein a plurality of the heat dissipation channels share one of the first ports and one of the second ports.
A method for preparing a chip packaging structure, comprising:

relatively fixing the forming member and the substrate with integrated chip;

A plastic encapsulation layer is formed, so that the plastic encapsulation layer wraps the chip and the forming member, and the forming member is used to assist in forming a heat dissipation channel.
The method for manufacturing a chip package structure according to claim 11, wherein the forming member is a heat dissipation pipe;

relatively fixing the forming member to the substrate on which the chip is integrated, including:

At least one heat pipe is laid on the upper surface of the chip.
The method for preparing a chip package structure according to claim 11 or 12, wherein the forming member is a heat dissipation pipe;

relatively fixing the forming member to the substrate on which the chip is integrated, including:

The heat dissipation cover is relatively fixed to the substrate on which the chip is integrated, and a heat dissipation pipe is connected to the side of the heat dissipation cover facing the upper surface of the chip.
The method for manufacturing a chip package structure according to claim 13, wherein a heat dissipation cover is relatively fixed to the substrate on which the chip is integrated, and a side of the heat dissipation cover facing the upper surface of the chip is connected to There are heat pipes including:

disposing the heat dissipation cover connected with the heat dissipation pipe in the injection groove of the plastic sealing mold;

The plastic packaging mold is placed on the surface of the substrate integrated with the chip, so that the heat dissipation cover connected with the heat dissipation pipe and the substrate integrated with the chip are relatively fixed.
The method for manufacturing a chip package structure according to claim 11, wherein the forming part is a core mold that needs to be removed;

After forming the plastic encapsulation layer, the preparation method further includes:

The core mold is removed to form the heat dissipation channel in the molding layer.
The method for manufacturing a chip package structure according to claim 15, wherein the relatively fixing the forming member to the substrate on which the chip is integrated comprises:

The core mold is arranged in the injection groove of the plastic sealing mold, and the core mold extends along the upper surface of the chip;

Then, the plastic encapsulation mold with the core mold inside is placed on the surface of the substrate on which the chip is integrated, and the core mold is in contact with the upper surface of the chip.
The method for manufacturing a chip package structure according to claim 15, wherein the relatively fixing the forming member to the substrate on which the chip is integrated comprises:

The core mold is arranged in the injection groove of the plastic sealing mold, and the core mold extends along the upper surface of the chip;

Then, the plastic encapsulation mold with the core mold inside is placed on the surface of the substrate integrated with the chip, and there is a gap between the core mold and the upper surface of the chip.
The method for preparing a chip package structure according to any one of claims 11-17, wherein the relatively fixing of the forming member and the substrate integrated with the chip comprises:

A plurality of the forming parts are relatively fixed to the substrate integrated with the chip, the forming parts are located in the same plane, and the surface on which the forming parts are located is parallel to the upper surface of the chip.
A device interconnection system, characterized in that it includes:

cabinet;

a printed circuit board, arranged on the cabinet;

The chip package structure according to any one of claims 1 to 10, or the chip package structure obtained by the preparation method of the chip package structure according to any one of claims 11 to 18;

Wherein, the chip package structure is integrated on the printed circuit board.