CN116235298A

CN116235298A - Chip packaging structure, preparation method of chip packaging structure and equipment interconnection system

Info

Publication number: CN116235298A
Application number: CN202080105365.4A
Authority: CN
Inventors: 代仁军; 周国名
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2023-06-06
Also published as: CN116235298A8; WO2022061767A1

Abstract

The embodiment of the application provides a chip packaging structure, a preparation method of the chip packaging structure and an equipment interconnection system, and relates to the technical field of chip heat dissipation. The chip packaging structure comprises: the device comprises a substrate, a chip, a plastic sealing layer, a heat dissipation channel, a first port and a second port; the chip is integrated on the surface of the substrate, the plastic sealing layer covers the surface of the substrate and wraps the chip, the heat dissipation channel is located in the plastic sealing layer, and the first port and the second port are both formed in the plastic sealing layer and are respectively communicated with the heat dissipation channel.

Description

Chip packaging structure, preparation method of chip packaging structure and equipment interconnection system

Technical Field

The present disclosure relates to the field of chip heat dissipation technologies, and in particular, to a chip package structure, a method for manufacturing the chip package structure, and an equipment interconnection system.

Background

With the increase of the core number and the speed of the chip, the power consumption of the chip is higher and higher, and then the problem of heat dissipation of the chip is particularly prominent. At present, two main modes of heat dissipation of a chip exist, one is air cooling, namely, the heat dissipated by the chip is dissipated by utilizing flowing air flow; the other is liquid cooled, i.e. the chips are cooled by flowing water.

Fig. 1 is a conventional liquid cooling heat dissipation structure, which includes a heat absorption copper seat 1, a heat dissipation water channel 2 through which water can flow is formed in the heat absorption copper seat 1, and the heat dissipation water channel 2 is communicated with a liquid inlet end 3 and a liquid outlet end 4.

Fig. 2 shows the liquid cooling heat dissipation structure of fig. 1 applied to a chip heat dissipation structure, wherein a heat absorbing copper base 1 contacts with a surface of a heat dissipation cover 8 on a chip 7, and the chip 7 is integrated on a surface of a substrate 5. In this way, the heat emitted by the chip 7 passes through the plastic sealing layer 6 and the heat radiating cover 8, and then is driven by the water flowing in the heat radiating water channel 2, so as to realize the cooling of the chip.

When the liquid cooling heat radiation structure radiates heat to the chip, a heat radiation path between the heat source chip 7 and the heat radiation water channel 2 is long, and the heat radiation path needs to pass through the plastic layer 6 and the heat radiation cover 8. The heat dissipation efficiency of the chip is seriously affected because the plastic layer 6 and the heat dissipation cover 8 generate larger heat resistance.

Disclosure of Invention

The embodiment of the application provides a chip packaging structure, a preparation method of the chip packaging structure and an equipment interconnection system. The main purpose is to shorten the heat dissipation path and improve the heat dissipation efficiency of the chip.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, the present application provides a chip packaging structure, including: the device comprises a substrate, a chip, a plastic sealing layer, a heat dissipation channel, a first port and a second port; the chip is integrated on the surface of the substrate, the plastic sealing layer covers the surface of the substrate and wraps the chip, the heat dissipation channel is located in the plastic sealing layer, and the first port and the second port are both formed in the plastic sealing layer and are respectively communicated with the heat dissipation channel.

According to the chip packaging structure, the heat dissipation channel is arranged in the plastic packaging layer. Compared with the prior art that the heat dissipation channel is arranged on the surface of the heat dissipation cover, the heat dissipation structure obviously shortens the path between the heat generation source chip and the heat dissipation channel, so that heat emitted by the chip can be transferred to the cooling medium flowing in the heat dissipation channel through the heat dissipation path with low thermal resistance, and further the heat dissipation efficiency of the chip is improved. In addition, the heat dissipation channel is arranged in the plastic packaging layer, so that the requirement on the external heat dissipation space of the whole chip packaging structure is reduced, and the utilization rate of the external space is improved.

In a possible implementation manner of the first aspect, the heat dissipation channel is disposed close to the chip. By arranging the heat dissipation channel close to the chip, the heat dissipation path is further shortened, and the heat dissipation efficiency is improved.

In a possible implementation manner of the first aspect, the heat dissipation channel is disposed above the chip upper surface, and the heat dissipation channel extends along the chip upper surface. Generally, the heat of the upper surface of the chip is relatively large, so that the heat dissipation channel is arranged above the upper surface of the chip, and extends along the upper surface of the chip, so that the heat of the upper surface of the chip can be rapidly diffused.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation tube embedded in the plastic package layer, and the heat dissipation tube is in contact with the upper surface of the chip. In this way, the cooling medium and the chip are separated by the wall of the radiating pipe, and the radiating efficiency is higher.

In a possible implementation manner of the first aspect, the chip package structure further includes: the heat dissipation cover is covered on the surface of the plastic sealing layer; the heat dissipation channel is a heat dissipation pipe embedded in the plastic package layer and connected with the heat dissipation cover. On the premise of effectively improving the heat dissipation efficiency, the heat dissipation structure is convenient to manufacture and implement.

In a possible implementation manner of the first aspect, the radiating pipe connected to the radiating cover is in contact with the upper surface of the chip. The cooling medium is separated from the chip only by the pipe wall of the cooling pipe by contacting the cooling pipe with the upper surface of the chip, so that the cooling efficiency is high.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation groove formed on a surface of the plastic sealing layer, which is close to the upper surface of the chip. In this way, the cooling medium directly contacts the chip, and the heat dissipation effect is further improved. The cooling medium needs to be a medium which cannot corrode the chip and is non-conductive.

In a possible implementation manner of the first aspect, the heat dissipation channel is a heat dissipation cavity formed in the plastic package layer.

In a possible implementation manner of the first aspect, a heat dissipation channel is also formed inside a portion of the molding layer covering the surface of the substrate. Because the metal wiring can be integrated on the substrate, when the chip packaging structure works, the metal wiring can also emit heat, meanwhile, the heat emitted by the chip can be conducted onto the substrate, and a heat dissipation channel is arranged in the plastic sealing layer on the substrate, so that the substrate can be quickly cooled, and the heat dissipation effect of the whole chip packaging structure is improved.

In a possible implementation manner of the first aspect, the heat dissipation channels are multiple, the multiple heat dissipation channels are located in the same plane, and a surface where the multiple heat dissipation channels are located is parallel to the upper surface of the chip. Through setting up a plurality of heat dissipation channels, can increase the heat conduction area, further improve radiating efficiency.

In a possible implementation manner of the first aspect, the plurality of heat dissipation channels share one first port, and share one second port. The structure of the whole chip packaging structure can be simplified by adopting the first port and the second port.

In a possible implementation manner of the first aspect, the cross section of the heat dissipation channel is in a flat structure. The cross section of the heat dissipation channel is arranged into a flat structure, so that the contact area between the heat dissipation channel and the plastic sealing layer can be increased, the heat conduction area is further increased, and the heat dissipation efficiency is improved.

In a second aspect, the present application provides a method for manufacturing a chip package structure, the method comprising:

relatively fixing the forming piece and the substrate integrated with the chip;

and forming a plastic sealing layer so that the plastic sealing layer wraps the chip and the forming piece, wherein the forming piece is used for assisting in forming the heat dissipation channel.

In the method for manufacturing the chip packaging structure provided by the embodiment of the application, the forming piece can assist in forming the heat dissipation channel, and the heat dissipation channel is located in the plastic packaging layer. Compare current scheme with the heat dissipation passageway setting at the heat dissipation lid surface, this application obvious shortened the route between chip to the heat dissipation passageway to make the heat that the chip gives out heat transfer through the heat dissipation route of low thermal resistance give the coolant that flows through in the heat dissipation passageway, and then improve the radiating efficiency to the chip. In addition, the heat dissipation channel is arranged in the plastic packaging layer, so that the requirement on the external heat dissipation space of the whole chip packaging structure is reduced, and the utilization rate of the external space is improved.

In a possible implementation manner of the second aspect, the forming member is a radiating pipe; relatively fixing the forming member and the substrate integrated with the chip, comprising: at least one radiating pipe is laid on the upper surface of the chip. Before injection molding, the radiating pipe is arranged on the upper surface of the chip, and finally the radiating pipe is formed in the plastic packaging layer to form a radiating channel, and the radiating pipe is close to the upper surface of the chip. The process is simple, and the cooling medium in the radiating pipe is separated from the chip only by the pipe wall of the radiating pipe, so that the radiating efficiency is high.

In a possible implementation manner of the second aspect, the forming member is a radiating pipe; relatively fixing the forming member and the substrate integrated with the chip, comprising: the heat dissipation cover and the substrate integrated with the chip are relatively fixed, and the side face of the heat dissipation cover, which faces the upper surface of the chip, is connected with a heat dissipation pipe. The radiating pipe is connected with the radiating cover so that the radiating pipe forms a radiating channel. And the process is convenient to implement.

In a possible implementation manner of the second aspect, the heat dissipation cover and the substrate integrated with the chip are relatively fixed, and a heat dissipation tube is connected to a side of the heat dissipation cover facing the upper surface of the chip, including: a heat radiation cover connected with a heat radiation pipe is arranged in an injection molding groove of the plastic package mold; and placing the plastic package die on the surface of the substrate integrated with the chip so that the heat dissipation cover connected with the heat dissipation pipe is relatively fixed with the substrate integrated with the chip. The heat dissipation cover connected with the heat dissipation pipe is directly arranged in the plastic package die, and the relative fixation of the heat dissipation cover and the substrate is realized through the plastic package die, so that after the material is injected into the injection molding groove, the heat dissipation pipe is directly inlaid in the plastic package layer, and the heat dissipation cover is connected with the plastic package layer.

In a possible implementation manner of the second aspect, the forming member is a mandrel that needs to be removed; after forming the plastic layer, the preparation method further comprises the following steps: the mandrel is removed to form a heat dissipation channel within the molding layer.

In a possible implementation manner of the second aspect, the fixing the forming member relative to the substrate integrated with the chip includes: the method comprises the steps that a core mould is arranged in an injection groove of a plastic package mould, and extends along the upper surface of the core mould; and placing the plastic package mold with the core mold inside on the surface of the substrate integrated with the chip, wherein the core mold is in contact with the upper surface of the chip. In this way, after the core mold is removed, the formed heat dissipation channel is a heat dissipation groove formed on the surface of the plastic sealing layer, which is close to the upper surface of the chip.

In a possible implementation manner of the second aspect, the fixing the forming member relative to the substrate integrated with the chip includes: the method comprises the steps that a core mould is arranged in an injection groove of a plastic package mould, and extends along the upper surface of the core mould; and placing the plastic package mold with the core mold inside on the surface of the substrate integrated with the chip, wherein a space is reserved between the core mold and the upper surface of the chip. Therefore, after the core mold is removed, the formed heat dissipation channel is a heat dissipation cavity formed in the plastic package layer.

In a possible implementation manner of the second aspect, the fixing the forming member relative to the substrate integrated with the chip includes: the plurality of forming pieces and the substrate integrated with the chip are relatively fixed, the plurality of forming pieces are positioned in the same plane, and the surfaces of the plurality of forming pieces are parallel to the upper surface of the chip. Through setting up a plurality of formations, and then can form a plurality of heat dissipation channels to further improve radiating efficiency.

In a third aspect, the present application further provides an equipment interconnection system, including a cabinet and the chip packaging structure in any implementation manner of the first aspect or the chip packaging structure made in any implementation manner of the second aspect, where the chip packaging structure is disposed on the cabinet.

The device interconnection system provided by the embodiment of the application includes the chip packaging structure of the embodiment, so that the device interconnection system provided by the embodiment of the application and the chip packaging structure of the technical scheme can solve the same technical problems and achieve the same expected effect.

Drawings

FIG. 1 is a schematic diagram of a heat dissipation structure in the prior art;

FIG. 2 is a schematic diagram of the heat dissipation structure shown in FIG. 1 applied to a chip package structure;

FIG. 3 is a partial block diagram of a device interconnect system of an embodiment of the present application;

fig. 4 is a schematic diagram illustrating a connection relationship between a chip package structure and a PCB according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 9a is a cross-sectional view of a heat dissipation channel according to an embodiment of the present application;

FIG. 9b is a cross-sectional view of a heat dissipation channel according to an embodiment of the present application;

FIG. 9c is a cross-sectional view of a heat dissipation channel according to an embodiment of the present application;

FIG. 10 is another view of a chip package structure according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 12 is a section A-A of FIG. 11;

FIG. 13 is a section B-B of FIG. 11;

FIG. 14 is another cross-sectional view of a chip package structure according to an embodiment of the present application;

FIG. 15 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 16 is a section C-C of FIG. 15;

FIG. 17 is another cross-sectional view of a chip package structure according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 19 is a section D-D of FIG. 18;

FIG. 20 is a section E-E of FIG. 18;

FIG. 21 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 22 is a cross-sectional view of F-F of FIG. 21;

FIG. 23 is a section G-G of FIG. 21;

FIG. 24 is a flow chart of a method for fabricating a chip package structure according to an embodiment of the present application;

FIG. 25 is a flow chart of a method for manufacturing a chip package structure according to an embodiment of the present application;

fig. 26 is a schematic structural diagram corresponding to each step in the method for manufacturing a chip package structure according to the embodiment of the present application;

fig. 27 is a schematic structural diagram of a plastic package mold used in the method for manufacturing a chip package structure according to an embodiment of the present application;

FIG. 28 is a flow chart of a method for fabricating a chip package structure according to an embodiment of the present application;

fig. 29 is a schematic structural diagram corresponding to each step in the method for manufacturing a chip package structure according to the embodiment of the present application;

FIG. 30 is a flow chart of a method for fabricating a chip package structure according to an embodiment of the present application;

fig. 31 is a schematic structural diagram corresponding to each step in the method for manufacturing a chip package structure according to the embodiment of the present application;

fig. 32 is a schematic structural diagram of a plastic molding die and a core die used in the method for manufacturing a chip package structure according to an embodiment of the present application;

FIG. 33 is a flow chart of a method for fabricating a chip package structure according to an embodiment of the present application;

fig. 34 is a schematic structural diagram corresponding to each step in the method for manufacturing a chip package structure according to the embodiment of the present application;

fig. 35 is a schematic structural diagram of a plastic molding die and a core die used in the method for manufacturing a chip package structure according to an embodiment of the present application.

Reference numerals:

1-a heat absorption copper seat; 2-a heat dissipation water channel; 3-a liquid inlet end; 4-a liquid outlet end; 5-a substrate; 6-plastic sealing layer; 61-heat dissipation channels; 611-radiating pipes; 612—a heat sink; 613-a heat dissipation cavity; 7-chip; 8-a heat dissipation cover; 01-chip package structure; 02-PCB; 03-an electrical connection structure; 04-cabinet; 9-a first port; 10-a second port; 11-plastic packaging the die; 110-an injection molding groove; 112-mandrel; 113-notch; 12-plastic packaging material.

Detailed Description

In the device interconnection system, as shown in fig. 3 and 4, the device interconnection system includes a cabinet 04, a printed circuit board (printed circuit board, PCB) 02 carried on the cabinet 04, and a chip package structure 01 integrated on the PCB02, the chip package structure 01 being electrically connected to the PCB02 through an electrical connection structure 03. Thereby enabling the chip package structure 01 to perform signal transmission with other chips or other modules on the PCB 02.

The electrical connection structure 03 may be a Ball Grid Array (BGA), or may be a plurality of copper pillar bumps (copper pillar bump) arranged in an array, or may be a connector (socket).

The device interconnection system may include a server (server), a Data Center (Data Center), or other large-scale interconnection devices.

In these large-scale device interconnection systems, as the number of cores and the operation speed of chips are increased, the amount of heat dissipated is also increasing. In order to improve the heat dissipation efficiency, the performance of the device interconnection system is further improved.

The present application provides a chip package structure 01 having a heat dissipation structure, and the chip package structure 01 is explained in detail below.

Fig. 5 shows a schematic diagram of a chip package structure 01, which includes a substrate 5 and a chip 7 integrated on a surface of the substrate 5. In order to enhance the strength of the entire chip package structure 01 and to protect and reinforce the chip 7 integrated on the substrate 5, as shown in fig. 5, a plastic layer 6 is coated on the surface of the substrate 5, and the plastic layer 6 encapsulates the chip 7. The plastic sealing layer 6 is made of insulating materials such as resin materials.

In the chip package structure 01 shown in fig. 5, only one chip is shown, and in a practical structure, a plurality of chips integrated on the surface of the substrate 5 may be included.

The chip 7 may be a wafer (wafer), a die (die) obtained by dicing a wafer, or a plurality of die stacked.

The surface P1 of the molding layer 6 shown in fig. 5 has a bump formed at a position where the chip 7 is provided. In an alternative embodiment, as shown in fig. 6, the surface P1 of the plastic layer 6 may be made planar. The outer contour shape of the plastic layer 6 is not particularly limited in this application.

The chip package structure 01 shown in fig. 7 further includes a heat dissipation channel 61, where the heat dissipation channel 61 is located in the plastic layer 6, and the cooling medium can flow through the heat dissipation channel 61. In this way, the heat emitted by the chip 7 is conducted into the plastic layer 6, and the heat is taken away by the cooling medium flowing in the heat dissipation channel 61, so as to realize heat dissipation and temperature reduction of the chip 7.

In addition, the plastic layer 6 is further provided with a first port and a second port which are communicated with the heat dissipation channel 61. For example, when the first port is an inlet and the second port is an outlet, the cooling medium flowing in from the first port absorbs heat emitted from the chip 7 and is discharged through the second port.

As can be seen from fig. 7, the heat dissipation channel 61 is located within the plastic envelope 6. In this way, the heat dissipation path is significantly shortened as compared with the conventional heat dissipation structure provided above the heat dissipation cover, and the chip 7 can be transferred to the cooling medium located in the heat dissipation channel 61 through the heat dissipation path with low thermal resistance, so as to improve the heat dissipation efficiency.

In addition, compared with the prior art, on the premise that the power of the brake pump for providing pressure for the cooling medium is the same and the flow rate of the cooling medium is the same, more heat can be emitted to the chip, so that the chip works at a higher frequency and the performance of the chip is better exerted.

The cooling medium referred to herein may be a gas, such as air. But may also be a liquid, such as water. Of course, other refrigerant gases or refrigerant liquids may be selected. Alternatively, the cooling medium may be a liquid at the inlet, and the cooling medium may be changed into a gas after absorbing heat in the heat dissipation passage, and then flow out from the outlet.

In an alternative embodiment, referring to fig. 7, the heat dissipation path 61 is located near the chip 7 and above the upper surface M1 of the chip 7 and extends along the upper surface of the chip 7, which further shortens the heat dissipation path. In order to further improve the heat dissipation effect on the chip 7, as shown in fig. 8, a heat dissipation channel 61 may be formed at a position of the plastic sealing layer 6 close to the side surface M2 of the chip 7, so that heat can be dissipated from multiple surfaces to the chip 7, and the heat dissipation effect is correspondingly improved.

It should be noted that: the chip upper surface M1 referred to in the present application means: the surface of the chip 7 facing away from the substrate 5. Chip side M2 refers to: a face adjacent to the upper face M1.

On the substrate 5, there are metal traces for electrically connecting the chips 7 to be interconnected, and the metal traces emit a large amount of heat during operation of the chips 7. In addition, part of the heat on the chip 7 is also conducted to the substrate 5. In order to be able to dissipate heat from the substrate 5, as shown in fig. 8, a heat dissipation channel 61 is also formed inside the portion of the plastic layer 6 that covers the surface of the substrate 5, i.e. the heat dissipated from the substrate 5 is carried away by the cooling medium in the heat dissipation channel 61 located above the substrate 5.

Therefore, as can be seen from the structure shown in fig. 8, the heat dissipation structure according to the present application can not only realize multidirectional heat dissipation to the chip 7, but also has a heat dissipation effect to the substrate 5. In this way, the heat dissipation effect of the entire chip structure 01 can be significantly improved.

The cross section of the heat dissipation channel can be of a round structure or a flat structure. In addition, the cross section of the heat dissipation channel can be other shapes.

Fig. 9a shows a heat dissipation channel having an oval cross section, fig. 9b shows a heat dissipation channel having a rectangular cross section, and fig. 9c shows a heat dissipation channel having a trapezoid cross section. In fig. 9a and 9b, S1 shows a dimension parallel to the direction of the upper surface of the chip, and S2 shows a dimension perpendicular to the direction of the upper surface of the chip. And S1 is greater than S2 to form a flat structure. In fig. 9c, the lower bottom surface of the trapezoid is close to the chip.

In fig. 9a, 9b and 9c, the wall surface of the heat dissipation channel, which is close to the chip, has a larger heat conduction area, so that the heat dissipation effect is correspondingly improved.

In an alternative embodiment, if a plurality of chips are integrated on the substrate, a plurality of heat dissipation channels for dissipating heat from the plurality of chips may be connected in series.

The heat dissipation channels can exist in various arrangement modes. In an alternative embodiment, referring to fig. 10, a plurality of heat dissipation channels 61 are arranged in parallel on the upper surface of the chip, and the plurality of heat dissipation channels 61 are in the same plane, and the plane is parallel to the upper surface of the chip. Each heat dissipation channel extends in a straight line. In another alternative embodiment, the heat dissipation channel 61 may also extend in a curve to increase the heat conduction area, and may also ensure that the flow of the cooling medium is uniform throughout to achieve a uniform heat dissipation effect. If there are also a plurality of heat dissipation channels extending to the upper side of the substrate, the heat dissipation channels located at the positions are also arranged in parallel.

For simplicity of construction, as shown in fig. 10, the first port 9 opened on the plastic layer has only one, and the second port 10 opened on the plastic layer has only one. In this way, the cooling medium entering from one first port 9 is divided into multiple branches into heat dissipation channels, and the cooling medium carrying heat is merged through the heat dissipation channels of the multiple branches and discharged from one second port 10. In alternative embodiments, the number of second ports 10 of the first ports 9 may be plural, respectively.

To further enhance the heat dissipation effect, the device interconnection system may further include a cooling structure for cooling the cooling medium entering the heat dissipation channel. Thus, by guiding the cooling medium with lower temperature into the heat dissipation channel, larger temperature difference and better cooling effect can be achieved.

If the cooling medium is gas, the refrigeration structure can adopt a refrigeration air conditioner. If the cooling medium is liquid, the refrigeration structure may employ a cooling tower. In alternative embodiments, other configurations capable of cooling a gas or liquid may be employed.

The first port 9 and the second port 10 may be disposed at the side of the plastic layer 6 as shown in fig. 10. And can also be arranged on the top surface of the plastic sealing layer. The positions of the first port 9 and the second port 10 are not particularly limited in this application.

There are a variety of possible structures for forming the heat dissipation channel 61, and several possible embodiments are presented in this application, and are described separately below.

Referring to fig. 11 and 12, a structure of a heat dissipation channel is shown, the heat dissipation channel is a heat dissipation tube 611 embedded in the plastic layer 6, and the heat dissipation tube 611 is in contact with the upper surface of the chip 7.

Since the heat dissipation pipe 611 is close to the upper surface of the chip 7, that is, the heat dissipation path between the chip and the cooling medium includes only the wall thickness of the heat dissipation pipe, the heat dissipation path is shortened, and thermal resistance is reduced. After the cooling medium is introduced into the cooling tube 611, the heat emitted by the chip 7 is rapidly transferred to the cooling tube 611, so that the cooling medium takes away the heat.

The material of the radiating pipe can be copper, iron and the like with high heat conductivity coefficient.

Fig. 13 is a sectional view at B-B of fig. 11, from which it can be seen that the radiating pipe 611 extends above the substrate 5, and the radiating pipe 611 is proximate to the substrate 5. The heat on the substrate 5 is quickly spread to the radiating pipe 611 and is taken away by the cooling medium flowing in the radiating pipe 611.

The radiating pipe 611 shown in fig. 13 has a circular cross-section. The cross section of the radiating pipe 611 shown in fig. 14 has an oval structure.

In the chip package structure shown in fig. 11 to 14, a heat dissipation cover may be also included, and the heat dissipation cover covers the surface of the plastic layer. A heat dissipating cover may not be included.

The material of the heat dissipation cover can be iron, aluminum or other metals. In this way, the heat dissipation effect can be increased through the heat dissipation cover made of metal materials. In addition, the heat dissipation cover can also evenly dissipate heat so as to achieve a better heat dissipation effect.

Referring to fig. 15 and 16, another structure of forming a heat dissipation channel is shown, and a heat dissipation cover 8 is covered on the surface of the plastic sealing layer 6, and the heat dissipation channel is a heat dissipation tube 611 embedded in the plastic sealing layer 6 and connected with the heat dissipation cover 8.

In an alternative embodiment, the heat dissipation cover 8 is an injection molded part, and the heat dissipation pipe 611 may be integrally formed with the heat dissipation cover 8. In an alternative embodiment, the radiating pipe 611 is fixedly connected to the radiating cover 8 by a connection structure (e.g., welding).

In the structure shown in fig. 15 and 16, since the radiating pipe 611 is located inside the plastic layer 6, and is close to the chip 7. The heat emitted from the chip 7 is rapidly transferred to the cooling medium flowing in the radiating pipe.

The heat dissipation pipe 611 shown in fig. 16 is not in contact with the upper surface of the chip 7, and has a space therebetween. The wall surface of the radiating pipe 611 near the upper surface of the chip 7 shown in fig. 17 is attached to the upper surface of the chip 7. Therefore, the heat dissipation path can be further shortened, and the heat dissipation efficiency can be improved.

Referring to fig. 18 and 19, another structure of a heat dissipation channel is shown, and the heat dissipation channel is a heat dissipation cavity 613 formed in the plastic layer 6. As can be seen in fig. 19, a plastic sealing layer structure is provided between the heat dissipation cavity 613 and the chip 7.

Fig. 20 is a cross-sectional view at E-E of fig. 18, from which it can be seen that the heat dissipation chamber 613 extends above the substrate 5, i.e. between the heat dissipation chamber 613 and the substrate 5 is also separated by a layer of plastic layer 6.

In the above-described structure using the radiating pipe as the radiating passage shown in fig. 7 and 15, the cooling medium flowing in the radiating pipe is separated from the chip by at least the pipe wall of the radiating pipe. In the structure shown in fig. 18 using the heat dissipation chamber as the heat dissipation channel, the cooling medium flowing in the heat dissipation chamber is separated from the chip by the molding layer. Therefore, the cooling medium is not particularly limited, and even if corrosive or conductive medium is adopted as the cooling medium, the chip is not damaged, and the performance of the chip is not affected.

Referring to fig. 21 and 22, another structure of a heat dissipation channel is shown, wherein the heat dissipation channel is a heat dissipation groove 612 formed on a surface of the plastic layer 6 close to the upper surface of the chip 7. It will also be appreciated that the heat sink 612 extends through to the surface of the plastic layer 6 proximate to the chip 7 as can be seen in fig. 21.

In this way, the cooling medium flowing through the heat sink 612 is in direct contact with the chip 7, and a non-corrosive and non-conductive cooling medium is selected to protect the chip.

Fig. 23 is a sectional view at G-G of fig. 21, from which it can be seen that the heat sink 612 extends above the substrate 5, and the heat sink 612 also penetrates to the surface of the plastic layer 6 proximate to the substrate 5. Therefore, it is necessary to select a cooling medium that is non-corrosive and non-conductive to prevent damage to the substrate. When the heat dissipation structure is adopted, the plurality of chips are not conductive to promote the electric connection of the chips which do not need electric connection because of the conductive cooling medium, and the performance of the chip packaging structure is not affected. Likewise, the cooling medium flowing in the heat sink 612 does not damage the chips, metal traces, or other modules on the substrate.

The above-described embodiments are only some of the heat dissipation channels, for example, the heat dissipation channels may also include: the heat dissipation tube is inlaid in the plastic package layer, and the heat dissipation cavity is formed in the plastic package layer. May also include: a heat dissipation groove arranged on the surface of the plastic sealing layer close to the upper surface of the chip, and a heat dissipation pipe connected with the heat dissipation cover.

The embodiment of the application also provides a preparation method of the chip packaging structure, and referring to fig. 24, the preparation method comprises the following steps:

s1, fixing the forming piece and the substrate integrated with the chip relatively.

S2, forming a plastic sealing layer so that the plastic sealing layer wraps the chip and the forming piece, wherein the forming piece is used for assisting in forming a heat dissipation channel.

The adopted forming piece structure is different, and the structure of the formed heat dissipation channel is different. For example, the forming member may be a radiating pipe which finally forms a radiating passage. The forming member may be a core mold to be removed, and the space after the core mold is removed forms a heat dissipation channel.

The corresponding preparation method when using different structural components is explained in detail below.

In addition, in the process of forming the plastic sealing layer, the plastic sealing layer can be completed by adopting a plastic sealing die, the shapes of the plastic sealing die are different, and the appearance outlines of the finally formed plastic sealing layers are also different.

When the formed heat dissipation channel is a heat dissipation tube, the method for preparing the chip packaging structure comprises the following steps:

as in step S101 of fig. 25, and 26a of fig. 26, at least one radiating pipe 611 is disposed on the upper surface of the chip 7.

When the plastic sealing layer is formed again, the plastic sealing mold 11 shown in fig. 27 can be adopted, the plastic sealing mold 11 is internally provided with an injection molding groove 110 and a notch 113 communicated with the injection molding groove 110, and the notch 113 is buckled on the surface of the substrate during specific preparation.

As shown in step S102 of fig. 25, and 26b of fig. 26, the plastic molding die 11 is placed on the surface of the substrate 5 integrated with the chip 7 such that the radiating pipe 611 and the chip 7 are located in the injection groove 110 of the plastic molding die 11.

As shown in step S103 of fig. 25 and 26c of fig. 26, the molding material 12 is injected into the injection groove 110.

After the injection molding of the molding material is completed, pressure is usually required to be applied, so that the density of the molding material is higher and the packaging effect is better.

As shown in step S104 of fig. 25 and 26d of fig. 26, the molding die 11 is removed to form a molding layer 6 on the surface of the substrate 5, the molding layer 6 wraps the chip 7, and the surface of the molding layer 6 close to the chip 7 is provided with a heat dissipation tube 611.

That is, before plastic packaging, the heat dissipating tube is arranged on the upper surface of the chip, and then the injection molding process is performed, so that the heat dissipating tube is arranged in the formed plastic packaging layer. The manufacturing process is simple and the implementation is convenient. And the radiating pipe is directly contacted with the upper surface of the chip, so that the radiating path is short and the radiating effect is good.

When the formed heat dissipation channel is a heat dissipation tube, the method for preparing the chip packaging structure may also include the following steps:

as shown in step S201 of fig. 28 and 29a of fig. 29, the heat dissipation cover 8 is disposed in the molding die 11, and the heat dissipation pipe 611 is connected to the side of the heat dissipation cover 8 facing the chip. The plastic sealing mold 11 may adopt a plastic sealing mold structure shown in fig. 27.

As shown in step S202 of fig. 28, and 29b of fig. 29, the molding die 11 is placed on the surface of the substrate 5 integrated with the chip 7 such that the heat dissipation cover 8 to which the heat dissipation pipe 611 is connected and the chip 7 are both located in the injection groove 110 of the molding die 11.

As shown in step S203 of fig. 28 and 29c of fig. 29, the molding material 12 is injected into the injection groove 110.

As shown in step S204 of fig. 28 and 29d of fig. 29, the molding die 11 is removed to form a molding layer 6 on the surface of the substrate 5, the molding layer 6 wraps the chip 7, and the heat dissipation cover 8 is provided with a heat dissipation tube 611 near the upper surface of the chip.

Before plastic packaging, the heat radiating cover connected with the heat radiating pipe is arranged in a plastic packaging mould, then the plastic packaging mould containing the heat radiating cover and the heat radiating pipe is arranged on a substrate, and then an injection molding process is carried out, so that the heat radiating pipe is arranged in the formed plastic packaging layer. The manufacturing process is also simple and convenient to implement.

When the formed member is a core mold to be removed, the chip package structure may be prepared as follows.

As shown in step S301 of fig. 30 and 31a of fig. 31, the molding die 11 is placed on the surface of the substrate 5 integrated with the die 7 such that the die 7 is positioned in the injection groove 110 of the molding die 11, and at least one core die 112 extending along the upper surface of the die 7 is provided in the injection groove 110 with a space between the core die 112 and the upper surface of the die 7.

Fig. 32 is a diagram showing a connection relationship between the molding die 11 and the core die 112 in the manufacturing method, and in combination with fig. 31 and fig. 32, a distance a1 between the core die 112 and the notch 113 is required to be set between the core die 112 and the upper surface of the chip 7, the thickness dimension of the chip 7 is a2, and a1 is greater than a2.

As in step S302 of fig. 30, and 31b of fig. 31, the molding material 12 is injected into the injection groove so that the molding material 12 fills the injection groove at a position other than the core mold 112.

As shown in step S303 of fig. 30 and 31c of fig. 31, the molding die 11 is removed and the core die 112 is removed to form a molding layer 6 on the surface of the substrate 5, the molding layer 6 wraps the chip 7, and a heat dissipation cavity 613 is formed in the molding layer 6.

Since the distance between the core mold disposed in the injection molding groove and the notch is greater than the chip thickness dimension, there is a molding material between the finally formed heat dissipation cavity 613 and the surface of the chip 7.

The core mold 112 may be a bag filled with air, and before injection molding and packaging, the bag filled with air is disposed in an injection molding groove, and then the plastic packaging material is injected to form a plastic sealing layer, and then the air in the bag is released, and then the bag is pulled out to form a heat dissipation cavity. Of course, the mandrel of this construction is just one example, and other constructions can be employed. For example, a chemical may be used to chemically react with the mandrel to cause the mandrel to be removed.

When the formed member is a core mold to be removed, the chip package structure may also be prepared by the following method.

As shown in step S401 of fig. 33, and 34a of fig. 34, the molding die 11 is placed on the surface of the substrate 5 integrated with the die 7 such that the die 7 is positioned in the injection groove 110 of the molding die 11, and at least one core die 112 extending along the upper surface of the die 7 is provided in the injection groove 110, and the core die 112 is in contact with the upper surface of the die 7.

Fig. 35 is a diagram showing a connection relationship between the molding die 11 and the core die 112 in the manufacturing method, and when the core die 112 is required to be in contact with the upper surface of the die 7 in combination with fig. 34 and 35, the distance a1 between the core die 112 and the notch 113 is set to a2, and the thickness dimension of the die 7 is set to a1 to a2.

As in step S402 of fig. 33, and 34b of fig. 34, the molding material 12 is injected into the injection groove so that the molding material 12 fills the injection groove at a position other than the core mold 112.

As shown in step S403 of fig. 33 and 34c of fig. 34, the molding die 11 is removed and the core die 112 is removed to form the molding layer 6 on the surface of the substrate 5, and the molding layer 6 wraps the chip 7, and the heat dissipation grooves 612 on the surface of the molding layer 6 close to the upper surface of the chip 7.

In order to increase the number of heat dissipation channels and improve heat dissipation efficiency, a plurality of forming members may be provided, regardless of whether the forming members are heat dissipation pipes or core molds, as shown in fig. 32 and 35, the plurality of forming members 112 are located in the same plane, and the surfaces of the plurality of forming members 112 are parallel to the upper surface of the chip. And a plurality of parallel heat dissipation channels are formed.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A chip package structure, comprising:

a substrate;

a chip integrated on the surface of the substrate;

a plastic layer covering the surface of the substrate and wrapping the chip;

the heat dissipation channel is positioned in the plastic package layer;

the first port and the second port are both arranged on the plastic sealing layer and are respectively communicated with the heat dissipation channel.
The chip package structure of claim 1, wherein the heat dissipation channel is disposed proximate to the chip.
The chip package structure according to claim 1 or 2, wherein the heat dissipation channel is disposed above the chip upper surface, and the heat dissipation channel extends along the chip upper surface.
The chip package structure according to any one of claims 1 to 3, wherein the heat dissipation channel is a heat dissipation pipe embedded in the plastic package layer, and the heat dissipation pipe is in contact with the upper surface of the chip.
The chip package structure according to any one of claims 1 to 4, further comprising:

the heat dissipation cover is covered on the surface of the plastic sealing layer;

the heat dissipation channel is a heat dissipation pipe which is inlaid in the plastic package layer and connected with the heat dissipation cover.
The chip package structure according to any one of claims 1 to 5, wherein the heat dissipation channel is a heat dissipation groove formed on a face of the plastic layer proximate to the upper surface of the chip.
The chip package structure according to any one of claims 1 to 6, wherein the heat dissipation channel is a heat dissipation cavity formed in the plastic package layer.
The chip packaging structure according to any one of claims 1 to 7, wherein the heat dissipation channel is also formed inside a portion of the plastic layer that covers the substrate surface.
The chip package structure according to any one of claims 1 to 8, wherein the heat dissipation channels are plural, the heat dissipation channels are located in the same plane, and a plane where the heat dissipation channels are located is parallel to the upper surface of the chip.
The chip package structure of claim 9, wherein a plurality of the heat dissipation channels share one of the first ports and share one of the second ports.
The preparation method of the chip packaging structure is characterized by comprising the following steps:

relatively fixing the forming piece and the substrate integrated with the chip;

and forming a plastic sealing layer so that the chip and the forming piece are wrapped by the plastic sealing layer, wherein the forming piece is used for assisting in forming a heat dissipation channel.
The method of manufacturing a chip package according to claim 11, wherein the forming member is a heat dissipating tube;

relatively fixing the forming member and the substrate integrated with the chip, comprising:

at least one radiating pipe is laid on the upper surface of the chip.
The method of manufacturing a chip package according to claim 11 or 12, wherein the forming member is a heat dissipating tube;

relatively fixing the forming member and the substrate integrated with the chip, comprising:

and the radiating cover and the substrate integrated with the chip are relatively fixed, and a radiating pipe is connected to the side surface of the radiating cover, which faces the upper surface of the chip.
The method of manufacturing a chip package according to claim 13, wherein a heat dissipating cap is fixed to the substrate on which the chip is integrated, and a heat dissipating tube is connected to a side of the heat dissipating cap facing the upper surface of the chip, comprising:

the heat dissipation cover connected with the heat dissipation pipe is arranged in an injection groove of the plastic package die;

and placing the plastic package die on the surface of the substrate integrated with the chip so that the heat dissipation cover connected with the heat dissipation pipe and the substrate integrated with the chip are relatively fixed.
The method of manufacturing a chip package according to claim 11, wherein the forming member is a core mold to be removed;

after forming the plastic layer, the preparation method further comprises the following steps:

and removing the core mold to form the heat dissipation channel in the plastic sealing layer.
The method of manufacturing a chip package structure according to claim 15, wherein relatively fixing the formation member and the substrate integrated with the chip, comprises:

the core mould is arranged in an injection groove of the plastic package mould, and extends along the upper surface of the chip;

and placing the plastic package mold with the core mold arranged inside on the surface of the substrate integrated with the chip, wherein the core mold is in contact with the upper surface of the chip.
The method of manufacturing a chip package structure according to claim 15, wherein relatively fixing the formation member and the substrate integrated with the chip, comprises:

the core mould is arranged in an injection groove of the plastic package mould, and extends along the upper surface of the chip;

and placing the plastic package mold with the core mold arranged inside on the surface of the substrate integrated with the chip, wherein a space is reserved between the core mold and the upper surface of the chip.
The method of manufacturing a chip package according to any one of claims 11 to 17, wherein relatively fixing the formation member and the substrate integrated with the chip, comprises:

and relatively fixing the forming pieces and the substrate integrated with the chip, wherein the forming pieces are positioned in the same plane, and the surfaces of the forming pieces are parallel to the upper surface of the chip.
A device interconnect system, comprising:

a cabinet;

the printed circuit board is arranged on the cabinet;

the chip packaging structure according to any one of claims 1 to 10, or the chip packaging structure produced by the production method of the chip packaging structure according to any one of claims 11 to 18;

wherein the chip package structure is integrated on the printed circuit board.