CN111128917A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN111128917A CN111128917A CN201911392937.7A CN201911392937A CN111128917A CN 111128917 A CN111128917 A CN 111128917A CN 201911392937 A CN201911392937 A CN 201911392937A CN 111128917 A CN111128917 A CN 111128917A
- Authority
- CN
- China
- Prior art keywords
- chip
- flow guide
- substrate
- heat dissipation
- guide assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: the base plate is provided with flow guide holes penetrating through the front surface and the back surface of the base plate; a first chip electrically connected to the substrate; the flow guide assembly is arranged on the substrate, a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide hole; the second chip is arranged on one side, away from the first chip, of the flow guide assembly and is electrically connected with the substrate; and the plastic packaging body is used for packaging the first chip, the flow guide assembly and the second chip. The chip packaging structure provided by the invention realizes internal heat dissipation of the multi-chip packaging body with higher efficiency, and effectively solves the problem of insufficient heat dissipation efficiency of the surface heat dissipation structure; the circuit leading-out of the two chips is not interfered by the flow guide assembly, and the number of the I/O ports of the chips is not limited.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof.
Background
With the popularity of wireless electronic devices, the feature size of integrated circuits is continuously shrinking, and the interconnection density of devices is continuously increasing. Three-dimensional chip packaging has been a development trend, but such packaging forms also introduce the problem of poor heat dissipation while improving the integration of the package. At present, the traditional heat dissipation structure and device design mainly focus on heat dissipation improvement on the surface of the package body, and the heat dissipation improvement in the package body is very limited.
To solve the problem of heat dissipation inside the package, chinese patent document CN105140205A discloses a double-sided heat dissipation semiconductor stacked package structure, which includes: the chip comprises a first metal frame pin, a first chip, a first welding wire, a first metal sheet, a second metal frame pin, a second chip, a second welding wire and a second metal sheet; the soldering flux is arranged above the first metal sheet and is connected with the second chip; the first chip forms circuit communication with the first metal sheet through the first pin of the first frame, and the second chip forms circuit communication with other pins of the first frame through the first pin of the second frame, the second metal sheet and the other pins of the first frame. This scheme is through arranging the metal fin in between the chip of piling up the encapsulation, realizes piling up the heat in the chip and draws forth, compares traditional heat radiation structure and can increase the radiating efficiency, still has following problem: (1) heat dissipation is performed only through heat transfer of the metal sheet, particularly, the metal sheet between the two chips is packaged between the chips, so that the heat of the metal sheet can not be effectively conducted, and the heat dissipation efficiency is not high; (2) the packaging form can limit the number of I/O ports of the chip due to the existence of metal sheets and frames, and is not in line with the development trend of semiconductors nowadays.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defects of low internal heat dissipation efficiency and limited number of chip I/O ports of the multi-chip package in the prior art, thereby providing a chip package structure with a heat dissipation pipeline and a manufacturing method thereof.
In a first aspect, the present invention provides a chip package structure, including:
the base plate is provided with flow guide holes penetrating through the front surface and the back surface of the base plate;
a first chip electrically connected to the substrate;
the flow guide assembly is arranged on the substrate, a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide hole;
the second chip is arranged on one side, away from the first chip, of the flow guide assembly and is electrically connected with the substrate;
and the plastic packaging body is used for packaging the first chip, the flow guide assembly and the second chip.
Further, the first chip and the substrate are soldered to a first substrate pad provided on the substrate through a first solder bump provided on the first chip.
Furthermore, the second chip is connected with the substrate through a second chip bonding pad arranged on the second chip and a second substrate bonding pad arranged on the substrate in a routing manner.
Further, the flow guide assembly includes:
the first flow guide piece is arranged on the substrate and provided with a first heat dissipation pipeline running through the front surface and the back surface of the substrate, and the first heat dissipation pipeline is communicated with the flow guide hole;
and the second flow guide piece is arranged on one side, deviating from the substrate, of the first chip and is provided with a second heat dissipation pipeline, and two ends of the second heat dissipation pipeline are respectively communicated with the two first heat dissipation pipelines.
Further, the chip package structure further includes: and the second flow guide piece is respectively bonded with the first flow guide piece and the first chip through the first bonding layer.
Further, the chip package structure further includes: and the second chip is bonded with the second flow guide part through the second adhesive layer.
In a second aspect, the present invention provides a method for manufacturing a chip package structure, including:
providing a substrate, and forming a plurality of flow guide holes penetrating through the front surface and the back surface of the substrate on the substrate;
mounting a first chip on the substrate, and electrically connecting the first chip with the substrate;
connecting a flow guide assembly on the substrate to enable a heat dissipation pipeline inside the flow guide assembly to be communicated with the flow guide hole;
mounting a second chip on one side of the flow guide assembly, which is far away from the first chip, so that the second chip is electrically connected with the substrate;
and manufacturing a plastic package body to encapsulate the first chip, the flow guide assembly and the second chip.
Further, when a first chip is mounted on the substrate, the first solder bump on the first chip is soldered to the first substrate pad on the substrate.
And further, when a second chip is mounted on one side of the diversion assembly, which is far away from the first chip, a second chip bonding pad on the second chip is connected with a second substrate bonding pad arranged on the substrate in a routing way.
Furthermore, the flow guide component comprises a first flow guide part and a second flow guide part, the first flow guide part is provided with a first heat dissipation pipeline running through the front surface and the back surface of the first flow guide part, the second flow guide part is provided with a second heat dissipation pipeline,
when connecting water conservancy diversion subassembly on the base plate, include:
connecting the first flow guide piece with the substrate to enable the first heat dissipation pipeline to be communicated with the flow guide hole;
and connecting a second flow guide part with the first flow guide part, so that two ends of the second heat dissipation pipeline are respectively communicated with the two first heat dissipation pipelines.
The technical scheme of the invention has the following advantages:
1. according to the chip packaging structure provided by the invention, the flow guide assembly is arranged between the first chip and the second chip, and the flow guide assembly is internally provided with the heat dissipation pipeline capable of circulating heat dissipation liquid or gas and communicated with the flow guide hole on the substrate, so that internal heat dissipation of the multi-chip packaging body with higher efficiency is realized, and the problem of insufficient heat dissipation efficiency of the surface heat dissipation structure is effectively solved; the first chip and the second chip are respectively electrically connected with the substrate, circuit leading-out of the two chips is not interfered by the flow guide assembly, and the number of I/O ports of the chips is not limited.
2. The chip packaging structure provided by the invention has the advantages that the flow guide assembly comprises the first flow guide part and the second flow guide part, the modular design is realized, the first flow guide part is used for being connected with the substrate to realize the communication between the first heat dissipation pipeline and the flow guide hole, the second flow guide part is used for being connected with the first flow guide part to realize the communication between the first heat dissipation pipelines, heat dissipation liquid or gas can sequentially pass through the flow guide hole, the first heat dissipation pipeline, the second heat dissipation pipeline, the first heat dissipation pipeline and the flow guide hole, heat dissipation flow channels are formed on the top surface and the side surface of the first chip and the bottom surface of the second chip, and the heat dissipation efficiency of the chip in the packaging body is improved.
3. According to the chip packaging structure provided by the invention, the first bonding layer is arranged, the second flow guide piece is respectively bonded with the first flow guide piece and the first chip, and the second bonding layer is arranged, so that the second chip is bonded with the second flow guide piece.
4. According to the manufacturing method of the chip packaging structure, the first chip, the flow guide assembly and the second chip are sequentially connected on the substrate, the packaging body is manufactured and packaged, the flow guide assembly among the chips inside the packaging body is arranged, the heat dissipation inside the multi-chip packaging body is increased, the circuit leading-out of the two chips cannot be interfered by the flow guide assembly, and the number of I/O ports of the chips cannot be limited.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
FIG. 2 is a top view of the structure after installation of a first baffle member in accordance with one embodiment of the present invention;
FIG. 3 is a schematic view of the internal structure of a second baffle member according to an embodiment of the present invention;
FIG. 4 is a bottom view of a second baffle member in accordance with an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of the step S1 according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of the step S2 according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of the step S3 according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of the step S4 according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of the step S5 according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram obtained in step S6 according to an embodiment of the present invention.
Description of reference numerals:
1-a substrate; 2-diversion holes; 3-a first chip; 4-a second chip; 5-plastic packaging body; 6-first substrate pad; 7-second substrate pad; 8-a first solder bump; 9-bottom filling layer; 10-a first flow guide; 11-a first heat dissipation pipe; 12-a second flow guide; 13-a second heat dissipation pipe; 14-a first adhesive layer; 15-a second chip pad; 16-a second adhesive layer; 17-electrically conductive wires.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, the present invention provides a chip package structure, including: the base plate 1 is provided with flow guide holes 2 penetrating through the front surface and the back surface of the base plate; a first chip 3 electrically connected to the substrate 1; the flow guide assembly is arranged on the substrate 1, a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide hole 2; the second chip 4 is arranged on one side of the flow guide assembly, which is far away from the first chip 3, and is electrically connected with the substrate 1; and the plastic package body 5 is used for encapsulating the first chip 3, the flow guide assembly and the second chip 4.
According to the chip packaging structure provided by the invention, the flow guide assembly is arranged between the first chip 3 and the second chip 4, the heat dissipation pipeline capable of circulating heat dissipation liquid or gas is arranged in the flow guide assembly and is communicated with the flow guide hole 2 on the substrate 1, so that internal heat dissipation of a multi-chip packaging body with higher efficiency is realized, and the problem of insufficient heat dissipation efficiency of a surface heat dissipation structure is effectively solved; the first chip 3 and the second chip 4 are respectively electrically connected with the substrate 1, and circuit leading-out of the two chips is not interfered by the flow guide assembly, so that the number of I/O ports of the chips is not limited.
The substrate 1 is a circuit board for providing electrical connection, protection, and support for the chip. The surface of the chip is provided with a substrate 1 bonding pad used for being electrically connected with the chips, and the chips are connected with the substrate 1 to realize interconnection among the chips and lead-out of the chips. In the present application, the pad on the substrate 1 for electrical connection with the first chip 3 is referred to as a first substrate pad 6, and the pad for electrical connection with the second chip 4 is referred to as a second substrate pad 7. A plurality of flow guide holes 2 penetrating through the front surface and the back surface of the substrate 1 are formed in the substrate 1, the number, the size and the shape of the flow guide holes 2 are not limited, and the flow guide holes 2 can be formed through a mechanical method or a chemical etching method.
The first chip 3 has solder bumps, referred to as first solder bumps 8, on its functional surface, and can lead out circuits inside the first chip 3 to the surface, and the first chip 3 has insulation on all surfaces except the functional surface. The first solder bump 8 may be made of one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium, and may be made of Sn-containing solder or In solder. The first chip 3 can be mounted or flipped, for example, the first chip 3 is placed on the upper surface of the substrate 1 with the functional surface facing down, and the first chip 3 is soldered to the first substrate pad 6 through the first solder bump 8 on the functional surface to achieve electrical communication (as shown in fig. 1); or the functional surface of the first chip 3 is upward and is arranged on the upper surface of the substrate 1, and the first chip 3 is connected with the first substrate pad 6 through a first solder bump 8 on the functional surface in a routing way or through TSV. The first chip 3 is preferably connected in a flip-chip manner, and the underfill layer 9 is manufactured after the first chip 3 is flip-chip mounted to fill the gap between the first chip 3 and the substrate 1. The material of the underfill layer 9 is selected from insulating materials, such as polymer materials or molding compound materials. When the substrate 1 is provided with the plurality of flow guide holes 2, the first chip 3 is located in an area surrounded by the plurality of flow guide holes 2.
The flow guide assembly is communicated with the flow guide hole 2 through the heat dissipation pipeline arranged in the flow guide assembly, and heat dissipation liquid or gas is introduced into the heat dissipation pipeline through the flow guide hole 2, so that the heat dissipation of the interior of the packaging body is increased. For example, the heat dissipation liquid can be water, liquid nitrogen, freon or aqueous ammonia etc. and can set up according to actual need, and the heat dissipation gas can be air, nitrogen gas, argon gas etc. can set up according to actual need. The heat dissipation liquid or gas is introduced by a water pump, an air pump or a fan blade. As an optional embodiment of the above air guide assembly, the air guide assembly includes: the first flow guide part 10 is arranged on the substrate 1 and is provided with a first heat dissipation pipeline 11 penetrating through the front surface and the back surface of the substrate 1, the first heat dissipation pipeline 11 is communicated with the flow guide hole 2, and preferably, the first heat dissipation pipeline 11 is positioned on the side surface of the first chip 3; the second flow guiding element 12 is disposed on one side of the first chip 3 away from the substrate 1, and is provided with a second heat dissipation pipeline 13, two ends of the second heat dissipation pipeline 13 are respectively communicated with the two first heat dissipation pipelines 11, and preferably, the second heat dissipation pipeline 13 is located right above the first chip 3. The first flow-guiding member 10 and the second flow-guiding member 12 may be made of a high thermal conductivity material such as ceramic, silicon, etc. The preparation method can adopt the following steps: providing a high-thermal-conductivity material as a base material, performing semi-pipeline-shaped pattern etching on the surface of the base material by using a semiconductor etching process, and butting the base materials with the semi-pipelines on the surfaces in a face-to-face mode to form a flow guide part with an internal heat dissipation pipeline. The flow guide assembly comprises a first flow guide part 10 and a second flow guide part 12, the modular design is realized, the first flow guide part 10 is used for being connected with the substrate 1 to realize the communication of the first heat dissipation pipeline 11 and the flow guide hole 2, the second flow guide part 12 is used for being connected with the first flow guide part 10 to realize the communication between the first heat dissipation pipelines 11, heat dissipation liquid or gas can sequentially pass through the flow guide hole 2, the first heat dissipation pipeline 11, the second heat dissipation pipeline 13, the first heat dissipation pipeline 11 and the flow guide hole 2 to form heat dissipation flow channels on the top surface and the side surface of the first chip 3, and the heat dissipation efficiency of the chip inside the packaging body is improved.
As shown in fig. 2, which is a top view of the structure after the first flow guiding member 10 is installed, the first flow guiding member 10 may be a cubic structure, the first heat dissipation pipeline 11 penetrates through the front and back surfaces of the first flow guiding member, and preferably, the upper surface of the first flow guiding member 10 is flush with the upper surface of the first chip 3, so that the first heat dissipation pipeline 11 on the first flow guiding member 10 is aligned with the flow guiding hole 2 and then is bonded to the substrate 1. As shown in fig. 3 and 4, the second diversion part 12 may be a cubic structure, and has a second heat dissipation pipeline 13 inside, a pipe orifice of the second heat dissipation pipeline 13 is located on a lower surface of the cubic structure, and the second heat dissipation pipeline 13 is located corresponding to the first heat dissipation pipeline 11. Preferably, a first adhesive layer 14 is disposed on a lower surface of the second flow guide member 12, and the second flow guide member 12 is bonded to the first flow guide member 10 and the first chip 3 through the first adhesive layer 14. It should be emphasized that the present application does not limit the specific shape of the first flow guiding element 10 and the second flow guiding element 12 and the arrangement of the internal heat dissipation pipes, for example, the first flow guiding element 10 may be a separate flow guiding cylinder with an opening communicating with the flow guiding hole 2, or the first flow guiding element 10 and the second flow guiding element 12 may be an integrated structure, which are all within the scope of the present application, and preferably, as shown in fig. 1, the first heat dissipation pipes 11 located at the left and right sides of the first chip 3 communicate with the second heat dissipation pipes 13 located at the top of the first chip 3 to form an inverted U shape.
The functional surface of the second chip 4 is provided with a pad, referred to as a second chip pad 15, for communicating with an internal circuit, and the internal circuit of the second chip 4 can be led out to the surface, and the surfaces of the second chip 4 except the functional surface are insulated. The second chip 4 can be mounted or flipped, for example, the functional surface of the second chip 4 faces upward and is placed on the upper surface of the second flow guiding element 12, and the second chip 4 is connected with the second substrate pad 7 by a second chip pad 15 on the functional surface in a wire bonding manner, so as to realize electrical communication (as shown in fig. 1); or a plastic package material and a conductive column positioned in the plastic package material are manufactured on the second chip bonding pad 15, a rewiring layer is manufactured on the upper surface of the plastic package material, the functional surface of the second chip 4 faces downwards, the second chip 4 is connected with the rewiring layer through the second chip bonding pad 15 on the functional surface, and then the second chip is electrically connected with the substrate 1 through the conductive column and the second substrate bonding pad 7 in sequence. The second chip 4 is preferably connected by adopting a routing mode, the lower surface of the second chip 4 is provided with a second bonding layer 16, the second chip 4 is bonded with the second flow guide part 12 through the second bonding layer 16, and the conducting wire 17 for routing connection can be made of copper, tungsten, aluminum, gold or silver. In this way, the second chip 4 and the second flow guiding element 12 can be connected more closely, heat dissipation of the second chip 4 is increased, and the flow guiding pipeline in the flow guiding element can also play a role in dissipating heat of the conducting wire 17 connecting the second chip pad 15 and the second substrate pad 7.
The plastic package body 5 may be made of polymer materials such as epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, and the like, or may be made of other suitable plastic package materials. The first chip 3, the flow guide piece and the second chip 4 are subjected to integral plastic package, particularly when the second chip 4 and the substrate 1 are connected through routing, the conductive wire 17 is subjected to plastic package, and the stability and the reliability of a packaging structure are guaranteed.
It should be emphasized that the present invention does not limit the number of chips in the package structure, i.e. the number of packaged chips is not limited to two, and for example, the multilayer chips and the multilayer flow guiding assemblies may be stacked in the manner of arranging the chips and the flow guiding assemblies as described above, all of which are within the scope of the present invention.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps:
providing a substrate 1, and forming a plurality of flow guide holes 2 penetrating through the front surface and the back surface of the substrate 1 on the substrate 1;
mounting a first chip 3 on a substrate 1, and electrically connecting the first chip 3 with the substrate 1;
the base plate 1 is connected with a flow guide assembly, so that a heat dissipation pipeline in the flow guide assembly is communicated with the flow guide hole 2;
a second chip 4 is pasted on one side of the flow guide assembly, which is far away from the first chip 3, so that the second chip 4 is electrically connected with the substrate 1;
and manufacturing a plastic package body 5 to encapsulate the first chip 3, the flow guide assembly and the second chip 4.
According to the manufacturing method of the chip packaging structure, the first chip 3, the flow guide assembly and the second chip 4 are sequentially connected on the substrate 1, and the packaging body is manufactured and packaged, so that the flow guide assembly among the chips inside the packaging body is arranged, the heat dissipation inside the multi-chip packaging body is increased, the circuit leading-out of the two chips is not interfered by the flow guide assembly, and the number of I/O ports of the chips is not limited.
The above steps will be described in detail with reference to a specific method of fabricating the chip package structure shown in fig. 1.
The manufacturing method of the chip packaging structure shown in fig. 1 comprises the following steps:
step S1, providing a substrate 1, and forming a plurality of flow guiding holes 2 penetrating through the front and back surfaces of the substrate 1.
As shown in fig. 5, the substrate 1 has a first substrate pad 6 and a second substrate pad 7, the substrate 1 has a guiding hole 2, and the guiding hole 2 may be formed by a mechanical method or a chemical etching method, for example, by a mechanical drilling method, a laser drilling method, a dry etching method, or the like.
In step S2, the first chip 3 is flip-chip mounted on the substrate 1, and the underfill layer 9 is formed by soldering the first solder bumps 8 to the first substrate pads 6.
As shown in fig. 6, the first chip 3 is placed on the upper surface of the substrate 1 with the functional surface facing down, and the first solder bumps 8 on the functional surface of the first chip 3 are soldered to the pads 6 of the first substrate to achieve electrical communication. An underfill layer 9 is fabricated after the first chip 3 is flipped to fill the gap between the first chip 3 and the substrate 1.
Step S3, bonding the first flow guide member 10 to the substrate 1 to connect the first heat dissipation pipeline 11 to the flow guide hole 2.
As shown in fig. 7, the lower end opening of the first heat dissipation pipe 11 of the first flow guiding member 10 is aligned with the flow guiding hole 2, and the lower surface of the first flow guiding member 10 is bonded to the upper surface of the substrate 1 by using an adhesive material, wherein the adhesive material is an insulating adhesive material.
Step S4, bonding the second flow guiding element 12 to the first flow guiding element 10 and the first chip 3, so that two ends of the second heat dissipation pipeline 13 are respectively communicated with the two first heat dissipation pipelines 11.
As shown in fig. 8, openings at two ends of the second heat dissipation pipeline 13 of the second flow guiding element 12 are aligned with openings at upper ends of the two first heat dissipation pipelines 11, respectively, and a lower surface of the second flow guiding element 12 is bonded to an upper surface of the first chip 3 and an upper surface of the first flow guiding element 10 by using a bonding material, where the bonding material is an insulating bonding material. Thus, heat dissipation channels are formed on the top surface and the side surface of the first chip 3, and heat dissipation liquid or gas can sequentially pass through the left side flow guide hole 2, the left side first heat dissipation pipeline 11, the second heat dissipation pipeline 13, the right side first heat dissipation pipeline 11 and the right side flow guide hole 2.
In step S5, the second chip 4 is attached to the upper surface of the second diversion member 12 such that the surface thereof having the second chip pad 15 faces upward.
As shown in fig. 9, the second chip 4 is placed on the upper surface of the second flow guide 12 with its functional surface facing upward, and the lower surface of the second chip 4 is bonded to the upper surface of the second flow guide 12 by an adhesive material, which is an insulating adhesive material.
Step S6, a conductive line 17 is made to connect the second chip pad 15 and the second substrate pad 7.
As shown in fig. 10, the second chip pad 15 on the functional surface of the second chip 4 is wire bonded to the second substrate pad 7 to achieve electrical connection.
Step S7, fabricating a plastic package body 5 encapsulating the first chip 3, the first current guiding element 10, the second current guiding element 12, the second chip 4 and the conductive wire 17.
And (3) manufacturing a plastic package body 5 on the substrate 1, the first flow guide part 10, the second flow guide part 12, the second chip 4 and the conducting wire 17 by using plastic package to realize integral package, and finally forming a chip package structure shown in fig. 1.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A chip package structure, comprising:
the base plate is provided with flow guide holes penetrating through the front surface and the back surface of the base plate;
a first chip electrically connected to the substrate;
the flow guide assembly is arranged on the substrate, a heat dissipation pipeline is arranged in the flow guide assembly, and the heat dissipation pipeline is communicated with the flow guide hole;
the second chip is arranged on one side, away from the first chip, of the flow guide assembly and is electrically connected with the substrate;
and the plastic packaging body is used for packaging the first chip, the flow guide assembly and the second chip.
2. The chip package structure according to claim 1, wherein the first chip is soldered to the substrate via a first solder bump disposed on the first chip to a first substrate pad disposed on the substrate.
3. The chip package structure according to claim 1 or 2, wherein the second chip is wire bonded to the substrate through a second chip pad disposed on the second chip and a second substrate pad disposed on the substrate.
4. The chip package structure according to any one of claims 1 to 3, wherein the flow guide member comprises:
the first flow guide piece is arranged on the substrate and provided with a first heat dissipation pipeline running through the front surface and the back surface of the substrate, and the first heat dissipation pipeline is communicated with the flow guide hole;
and the second flow guide piece is arranged on one side, deviating from the substrate, of the first chip and is provided with a second heat dissipation pipeline, and two ends of the second heat dissipation pipeline are respectively communicated with the two first heat dissipation pipelines.
5. The chip package structure according to claim 4, further comprising: and the second flow guide piece is respectively bonded with the first flow guide piece and the first chip through the first bonding layer.
6. The chip package structure according to any one of claims 1 to 5, further comprising: and the second chip is bonded with the second flow guide part through the second adhesive layer.
7. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a substrate, and forming a plurality of flow guide holes penetrating through the front surface and the back surface of the substrate on the substrate;
mounting a first chip on the substrate, and electrically connecting the first chip with the substrate;
connecting a flow guide assembly on the substrate to enable a heat dissipation pipeline inside the flow guide assembly to be communicated with the flow guide hole;
mounting a second chip on one side of the flow guide assembly, which is far away from the first chip, so that the second chip is electrically connected with the substrate;
and manufacturing a plastic package body to encapsulate the first chip, the flow guide assembly and the second chip.
8. The method of claim 7, wherein the first solder bump on the first chip is soldered to the first substrate pad on the substrate when the first chip is mounted on the substrate.
9. The manufacturing method of the chip packaging structure according to claim 7 or 8, wherein when a second chip is mounted on a side of the flow guide assembly away from the first chip, a second chip bonding pad on the second chip is wire-bonded to a second substrate bonding pad arranged on the substrate.
10. The method for manufacturing a chip package according to any one of claims 7-9, wherein the flow guide assembly comprises a first flow guide member and a second flow guide member, the first flow guide member defines a first heat dissipation channel through the front and back surfaces thereof, the second flow guide member defines a second heat dissipation channel,
when connecting water conservancy diversion subassembly on the base plate, include:
connecting the first flow guide piece with the substrate to enable the first heat dissipation pipeline to be communicated with the flow guide hole;
and connecting a second flow guide part with the first flow guide part, so that two ends of the second heat dissipation pipeline are respectively communicated with the two first heat dissipation pipelines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911392937.7A CN111128917A (en) | 2019-12-30 | 2019-12-30 | Chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911392937.7A CN111128917A (en) | 2019-12-30 | 2019-12-30 | Chip packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111128917A true CN111128917A (en) | 2020-05-08 |
Family
ID=70504857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911392937.7A Pending CN111128917A (en) | 2019-12-30 | 2019-12-30 | Chip packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111128917A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584448A (en) * | 2020-05-19 | 2020-08-25 | 上海先方半导体有限公司 | Chip embedded micro-channel module packaging structure and manufacturing method |
| CN111698824A (en) * | 2020-05-22 | 2020-09-22 | 中国电子科技集团公司第二十九研究所 | Integrated interconnection structure of self-airtight packaging functional module and implementation method |
| CN112490208A (en) * | 2020-12-31 | 2021-03-12 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging structure with inductor |
| WO2022061767A1 (en) * | 2020-09-25 | 2022-03-31 | 华为技术有限公司 | Chip packaging structure, preparation method for chip packaging structure, and device interconnection system |
| CN115132709A (en) * | 2022-06-27 | 2022-09-30 | 深圳宏芯宇电子股份有限公司 | Chip stacking and packaging structure |
| CN116153884A (en) * | 2023-04-18 | 2023-05-23 | 上海韬润半导体有限公司 | Flip chip packaging structure and packaging method |
| CN116675175A (en) * | 2023-08-04 | 2023-09-01 | 青岛泰睿思微电子有限公司 | Multifunctional image light sense packaging equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956347A (en) * | 2014-03-24 | 2014-07-30 | 中山新诺科技股份有限公司 | 3D packaging chip |
| CN104124218A (en) * | 2014-08-04 | 2014-10-29 | 华进半导体封装先导技术研发中心有限公司 | Heat dissipation structure for 2.5D/3DTSV high-power chip package |
| CN104134637A (en) * | 2014-08-04 | 2014-11-05 | 华进半导体封装先导技术研发中心有限公司 | Radiating structure for high-power logic chip PoP |
| CN106449569A (en) * | 2016-10-24 | 2017-02-22 | 华进半导体封装先导技术研发中心有限公司 | Stacked-chip micro-channel heat dissipation structure and preparation method |
| CN106601704A (en) * | 2016-11-17 | 2017-04-26 | 云南电网有限责任公司电力科学研究院 | Thyristor radiator |
| CN110246816A (en) * | 2019-06-12 | 2019-09-17 | 上海先方半导体有限公司 | A kind of three-dimensional stacked fluid channel radiator structure of wafer scale and its manufacturing method |
| CN110444518A (en) * | 2019-09-10 | 2019-11-12 | 甬矽电子(宁波)股份有限公司 | Semiconductor package and production method |
-
2019
- 2019-12-30 CN CN201911392937.7A patent/CN111128917A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956347A (en) * | 2014-03-24 | 2014-07-30 | 中山新诺科技股份有限公司 | 3D packaging chip |
| CN104124218A (en) * | 2014-08-04 | 2014-10-29 | 华进半导体封装先导技术研发中心有限公司 | Heat dissipation structure for 2.5D/3DTSV high-power chip package |
| CN104134637A (en) * | 2014-08-04 | 2014-11-05 | 华进半导体封装先导技术研发中心有限公司 | Radiating structure for high-power logic chip PoP |
| CN106449569A (en) * | 2016-10-24 | 2017-02-22 | 华进半导体封装先导技术研发中心有限公司 | Stacked-chip micro-channel heat dissipation structure and preparation method |
| CN106601704A (en) * | 2016-11-17 | 2017-04-26 | 云南电网有限责任公司电力科学研究院 | Thyristor radiator |
| CN110246816A (en) * | 2019-06-12 | 2019-09-17 | 上海先方半导体有限公司 | A kind of three-dimensional stacked fluid channel radiator structure of wafer scale and its manufacturing method |
| CN110444518A (en) * | 2019-09-10 | 2019-11-12 | 甬矽电子(宁波)股份有限公司 | Semiconductor package and production method |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584448A (en) * | 2020-05-19 | 2020-08-25 | 上海先方半导体有限公司 | Chip embedded micro-channel module packaging structure and manufacturing method |
| CN111584448B (en) * | 2020-05-19 | 2022-03-29 | 上海先方半导体有限公司 | Chip embedded micro-channel module packaging structure and manufacturing method |
| CN111698824A (en) * | 2020-05-22 | 2020-09-22 | 中国电子科技集团公司第二十九研究所 | Integrated interconnection structure of self-airtight packaging functional module and implementation method |
| CN111698824B (en) * | 2020-05-22 | 2022-03-08 | 中国电子科技集团公司第二十九研究所 | Integrated interconnection structure of self-airtight packaging functional module and implementation method |
| WO2022061767A1 (en) * | 2020-09-25 | 2022-03-31 | 华为技术有限公司 | Chip packaging structure, preparation method for chip packaging structure, and device interconnection system |
| CN116235298A (en) * | 2020-09-25 | 2023-06-06 | 华为技术有限公司 | Chip packaging structure, preparation method of chip packaging structure and equipment interconnection system |
| CN112490208A (en) * | 2020-12-31 | 2021-03-12 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging structure with inductor |
| CN115132709A (en) * | 2022-06-27 | 2022-09-30 | 深圳宏芯宇电子股份有限公司 | Chip stacking and packaging structure |
| US11876037B1 (en) | 2022-06-27 | 2024-01-16 | Hosin Global Electronics Co., Ltd | Chip stacking and packaging structure |
| CN116153884A (en) * | 2023-04-18 | 2023-05-23 | 上海韬润半导体有限公司 | Flip chip packaging structure and packaging method |
| CN116675175A (en) * | 2023-08-04 | 2023-09-01 | 青岛泰睿思微电子有限公司 | Multifunctional image light sense packaging equipment |
| CN116675175B (en) * | 2023-08-04 | 2023-12-08 | 青岛泰睿思微电子有限公司 | Multifunctional image light sense packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111128917A (en) | Chip packaging structure and manufacturing method thereof | |
| KR100586698B1 (en) | Semiconductor Module having semiconductor chip package which is vertically mounted on module board | |
| TWI469309B (en) | Integrated circuit package system | |
| US7196403B2 (en) | Semiconductor package with heat spreader | |
| US6414391B1 (en) | Module assembly for stacked BGA packages with a common bus bar in the assembly | |
| JP6033843B2 (en) | Multi-die face-down stacking for two or more dies | |
| US9728481B2 (en) | System with a high power chip and a low power chip having low interconnect parasitics | |
| US7906842B2 (en) | Wafer level system in package and fabrication method thereof | |
| US8916958B2 (en) | Semiconductor package with multiple chips and substrate in metal cap | |
| US7495327B2 (en) | Chip stacking structure | |
| US7892888B2 (en) | Method and apparatus for stacking electrical components using via to provide interconnection | |
| CN103378017A (en) | High density 3D package | |
| US20180374827A1 (en) | Semiconductor assembly with three dimensional integration and method of making the same | |
| CN103811436A (en) | Thermal performance of logic chip in a package-on-package structure | |
| US20080258288A1 (en) | Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same | |
| CN110634848A (en) | Multi-chip stacking packaging structure and manufacturing method thereof | |
| CN101882606B (en) | Heat-dissipation semiconductor encapsulation structure and manufacturing method thereof | |
| TWI397164B (en) | Chip package with connecting extension of tsv | |
| CN213782014U (en) | Three-dimensional interconnected system-in-package | |
| US20170133352A1 (en) | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same | |
| CN115527975A (en) | Chip packaging structure and chip packaging method | |
| CN114334851A (en) | Fan-out type packaging structure and preparation method thereof | |
| CN113517263A (en) | Stacking structure and stacking method | |
| CN114334857A (en) | Chip packaging structure and method | |
| CN113451258A (en) | Semiconductor packaging structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200508 |