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WO2020114193A1 - Structure de ligne de carte de circuit imprimé, ensemble carte de circuit imprimé et dispositif électronique - Google Patents

Structure de ligne de carte de circuit imprimé, ensemble carte de circuit imprimé et dispositif électronique Download PDF

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Publication number
WO2020114193A1
WO2020114193A1 PCT/CN2019/116594 CN2019116594W WO2020114193A1 WO 2020114193 A1 WO2020114193 A1 WO 2020114193A1 CN 2019116594 W CN2019116594 W CN 2019116594W WO 2020114193 A1 WO2020114193 A1 WO 2020114193A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
circuit
layer
layers
traces
Prior art date
Application number
PCT/CN2019/116594
Other languages
English (en)
Chinese (zh)
Inventor
张卫鹏
Original Assignee
维沃移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Publication of WO2020114193A1 publication Critical patent/WO2020114193A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB

Definitions

  • the present disclosure relates to the technical field of circuit boards, and in particular, to a circuit board circuit structure, circuit board assembly, and electronic equipment.
  • circuit board layout of the electronic equipment in the related art has greater restrictions, and as the space of the circuit board becomes more and more tight, the layout problem becomes more and more serious.
  • the embodiments of the present disclosure provide a circuit board circuit structure, a circuit board assembly, and an electronic device, to solve the problem that the circuit board layout of the electronic device in the related art is relatively restrictive.
  • an embodiment of the present disclosure provides a circuit board circuit structure applied to a circuit board provided with devices, the circuit board being a multi-layer circuit board with a number of layers greater than or equal to 2;
  • the circuit board circuit has a circuit segment passing through the orthographic projection area of the device
  • the line segment includes even-numbered layer traces, and the layer traces of the line segment are respectively disposed on different layers of the circuit board, and the layer traces of the line segment are sequentially connected by a connecting segment, and the line segment The current directions of adjacent two layers of traces are opposite.
  • an embodiment of the present disclosure provides a circuit board assembly, including a circuit board, a magnetic sensitive device provided on the circuit board, and a circuit board circuit, the circuit board circuit adopts the structure of the first aspect.
  • an embodiment of the present disclosure provides an electronic device, including the circuit board assembly in the second aspect.
  • the even-numbered layer traces are arranged under the device, so that the magnetic fields generated by the current changes of the layer traces can cancel each other, thereby reducing the magnetic field interference around the device. In this way, there is no need to passively select an area where the magnetic field interference is small to set up the device, and the circuit board traces need not avoid the device. It can be seen that the embodiments of the present disclosure can make the circuit board layout more flexible.
  • FIG. 2 is a second structural diagram of a circuit board assembly provided by an embodiment of the present disclosure.
  • various electronic components are implemented on the circuit board to achieve different functions.
  • the current level generally occurs.
  • the change of the working scene of the electronic device such as charging scene, call scene, video scene, etc.
  • the change of the current size is also different.
  • the principle of electromagnetic induction a changing electric current produces a changing electric field, and a changing electric field produces a changing magnetic field. Therefore, the device will generate magnetic field interference to the device, especially the magnetic sensitive device, and the magnetic field interference may change at any time.
  • the continuous expansion of the functions of electronic equipment there are more and more scenes with large loads, and the current changes are more frequent, which makes the device more susceptible to magnetic field interference.
  • the methods to avoid magnetic field interference mainly include the following: First, the device is placed in an area away from the magnetic field interference, but as the layout area of the circuit board becomes more and more tight, the layout space restrictions are more and more, It is also getting harder and harder to find a location away from magnetic interference. Second, when laying out the circuit board traces, avoid the surrounding and bottom areas of the device, which limits the flexibility of the circuit board traces to a certain extent. Third, the device is placed in the clearance area of the radio frequency antenna, which reduces the effective clearance area of the radio frequency antenna, thereby reducing the sensitivity of the radio frequency antenna. It can be seen that none of the above methods can effectively solve the above-mentioned problems caused by installing devices in the electronic equipment.
  • embodiments of the present disclosure provide a circuit board circuit structure to solve the above-mentioned problems.
  • an embodiment of the present disclosure provides a circuit board circuit structure, which is applied to a circuit board 2 provided with a device 1.
  • the circuit board 2 is a multilayer circuit board with a number of layers greater than or equal to 2; a circuit board
  • the line 3 has a line segment 31 passing through the orthographic projection area of the device 1; the line segment 31 includes even-numbered layer traces, the layer traces of the line segment 31 are respectively disposed on different layers of the circuit board 2, and the layer traces of the line segment 31 pass through
  • the connection sections 313 are connected in sequence, and the current directions of the two adjacent layers of the line section 31 are opposite.
  • the circuit board circuit 3 is a circuit of other devices (not shown) provided on the circuit board 2.
  • the above-mentioned device 1 may be a device that realizes its function by a magnetic field (may be referred to as a "magnetic sensitive device"), such as a magnetic sensor.
  • Magnetically sensitive devices commonly used in related technologies include compasses, Hall elements, and so on.
  • the circuit board circuit 3 described above includes a current input terminal 32 and a current output terminal 33 in addition to the circuit segment 31 passing through the front projection area of the device 1.
  • the orthographic projection area of the device 1 on the circuit board 2 is a sealed area, and the line segment 31 passing through the orthographic projection area of the device 1 includes the first layer trace 311 passing through the orthographic projection area, which is outside the orthographic projection area It is connected to the connection section 313 and connected to the second layer trace 312 through the connection section 313.
  • the second layer trace 312 also passes through the orthographic projection area and forms the current output terminal 33.
  • the line segment 31 passing through the front projection area of the device 1 further includes that the first layer trace 311 extends from the front projection area to the front projection area, and is connected to the second layer trace 312 through the connection section 313 in the front projection area.
  • the second layer trace 312 passes through the orthographic projection area and forms the current output terminal 33.
  • the line segment 31 passing through the front projection area of the device 1 further includes that the first layer trace 311 extends from the front projection area to the outside of the front projection area, and is connected to the second layer trace 312 through the connecting section 313 outside the front projection area.
  • the second layer trace 312 extends into the orthographic projection area and forms a current output terminal 33.
  • the number of wiring layers of the above-mentioned line segment 31 is at least 2 layers, and the maximum number of wiring layers can be reasonably set according to the number of layers of the circuit board 2, for example, if the number of layers of the circuit board 2 is 4, the number of the line segment 31 The maximum number of trace layers is 4, and so on.
  • the connection section 313 between the adjacent two layers of traces of the line section 31 can be realized by copper plating through vias.
  • FIG. 2 shows a specific implementation manner in which the number of wiring layers of the line segment 31 is two layers.
  • the line segment 31 includes the first layer trace 311 and the second layer trace 312.
  • the first layer traces 311 and the second layer traces 312 are located on different layers of the circuit board 2 respectively.
  • the first layer traces 311 and the second layer traces 312 are arranged substantially in parallel (may be arranged in parallel or non-parallel);
  • the line section 31 further includes a connection section 313 connecting adjacent two layers of traces.
  • the connection section 313 may be a portion where the via on the circuit board 2 is located.
  • the first layer trace 311 and the second layer trace 312 will form current paths of equal size and substantially opposite directions.
  • the two current paths in the area where the device is located will produce magnetic fields with substantially opposite directions and almost equal sizes (due to the layer spacing between the first layer trace 311 and the second layer trace 312, the two current paths are in The size of the magnetic field in the area where the device 1 is located cannot be completely equal), so that the magnetic fields generated by the two current paths can be almost completely cancelled out, thus minimizing the magnetic field interference of the circuit board circuit 3 on the device.
  • the number of wiring layers of the line segment 31 may be two layers, or even layers such as four layers or six layers.
  • the number of wiring layers of the line segment 31 is optionally two layers, the reason is that, because there is only a magnetic field difference caused by the spacing between the two layers of wiring, the magnetic field cancellation effect is the best; and, the wiring layer The smaller the number, the fewer the number of layers occupying the circuit board 2, which can simplify the wiring arrangement inside the circuit board 2.
  • the number of wiring layers of the line segment 31 also needs to be set reasonably according to various parameters of the device.
  • the circuit board routing does not need to avoid the device, and the circuit board layout is more flexible; the circuit board can be laid out
  • the number of devices can also be appropriately increased, which can increase the layout density of the circuit board; and, it does not need to occupy the clearance area of the RF antenna to set the device, ensuring the working performance of the RF antenna and improving the sensitivity of the RF antenna.
  • each layer of the line segment 31 is parallel.
  • two adjacent layers of traces will form current paths of equal size and completely opposite directions.
  • the two current paths will generate magnetic fields with completely opposite directions and almost equal sizes in the area where the device is located, so as to offset the magnetic fields generated by the adjacent two layers of traces to the greatest extent.
  • the traces of each layer of the line segment 31 are respectively disposed on successive layers of the circuit board 2.
  • FIGS. 1 to 2 show an embodiment in which the first layer traces 311 and the second layer traces 312 are respectively disposed on the second layer and the third layer of the circuit board 2.
  • the distance between the trace of the line segment 31 closest to the device 1 and the device 1 is at least one Layer circuit board.
  • the line segment 31 should avoid the circuit board layer where the device 1 is located as much as possible.
  • the trace of the line segment 31 closest to the device 1 may be separated from the device 1 by at least one layer of circuit board. That is to say, the device 1 is arranged on the first layer of the circuit board 2, and the line segment 31 can be arranged from the second layer of the circuit board 2 or a layer below the second layer.
  • the circuit segment 31 can also be placed at the device 1 avoiding the connection structure such as solder legs and pads Circuit board layer.
  • the distance between the trace of the line segment 31 closest to the device 1 and the device 1 At least two layers of circuit boards.
  • the traces of each layer of the line segment 31 can be arranged on the layers of the circuit board 2 away from the device 1 .
  • the wiring of the line segment 31 may be provided on the third and fourth layers of the circuit board 2.
  • each layer of the line segment 31 also needs to be reasonably set according to the overall layout requirements of the circuit board 2.
  • the layer spacing of the circuit board 2 where the line segments 31 are provided is less than or equal to the layer spacing of the circuit board 2 where the line segments 31 are not provided.
  • the spacing between the layers of the circuit board 2 can be set differently, and the line segment 31 can be disposed on a layer with a smaller layer spacing of the circuit board 2.
  • the lengths of the traces of each layer of the line segment 31 are equal, and the connecting segment 313 between the traces of two adjacent layers is perpendicular to the traces of each layer. In this way, the closer the magnitude of the magnetic field generated by the traces of each layer to the device 1 is, the less the interference of the magnetic field generated by the device 1 to the device 1 is.
  • the vertical distance between the two ends of the traces of each layer of the line segment 31 and the edge of the device 1 is equal, and the connection segment 313 between the traces of two adjacent traces is perpendicular to the traces of each layer.
  • the two ends of the traces of each layer are arranged symmetrically with respect to the center of the device 1, and the resulting interference to the magnetic field of the device 1 is smaller.
  • each connection segment 313 connected to both ends of each layer trace in the line segment 31 to the edge of the device 1 is also approximately equal, and the vertical distance between each connection segment 313 and the edge of the device 1 is the same as the current input terminal 32
  • the vertical distance from the (or current output terminal 33) to the edge of the device 1 is also approximately equal. In this way, the magnetic field interference to the device 1 generated in the above-mentioned places can be substantially completely cancelled, thereby further reducing the magnetic field interference of the entire circuit board circuit 3 to the device 1.
  • the current input terminal 32 of the circuit board circuit 3 is located in the area from the edge of the device 1 to the outside of the device 1;
  • the current output terminal 33 of the circuit board line 3 is located in the area from the edge of the device 1 to the outside of the device 1.
  • circuit board lines 3 of other devices can be introduced from the outside of the device 1 and drawn out from the outside of the device 1 so as to avoid affecting the arrangement of the device 1 on the circuit board 2.
  • connection segment 313 between the adjacent two layers of traces of the line segment 31 is located in the area from the edge of the device 1 to the outside of the device 1.
  • each connecting section 313 and the edge of the device 1 is approximately equal to the vertical distance between the current input terminal 32 (or current output terminal 33) and the edge of the device 1.
  • the current output terminal 33 of the circuit board line 3 is directly led out from the last layer of the line segment 31 as shown in FIG. 1; when there is a surplus number of layers of the circuit board 2, the current of the circuit board line 3 The output terminal 33 is led out from the circuit board layer located under the last layer of the line segment 31, as shown in FIG. 2.
  • An embodiment of the present disclosure also provides a circuit board assembly.
  • the circuit board assembly includes a circuit board 2 and a device 1 provided on the circuit board 2 and a circuit board circuit 3.
  • the circuit board circuit 3 adopts the above disclosure The circuit board circuit structure in the embodiment.
  • the device 1 is a magnetic sensitive device, including at least one of a compass and a Hall element.
  • circuit board assembly can refer to the above description, and can achieve the same technical effect. In order to avoid repetition, it will not be repeated here.
  • An embodiment of the present disclosure also provides an electronic device, including the circuit board assembly in the above disclosed embodiment.
  • the specific implementation of the circuit board assembly in the electronic device can refer to the above description, and can achieve the same technical effect. In order to avoid repetition, it will not be repeated here.
  • the electronic device may be a computer, a mobile phone, a tablet, a laptop, a laptop, a personal computer, a personal digital assistant (PDA), or a mobile Internet electronic Device (Mobile Internet Device, MID), wearable device (Wearable Device), e-reader, navigator, digital camera, etc.
  • PDA personal digital assistant

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention concerne une structure de ligne d'une carte de circuit imprimé, un ensemble carte de circuit imprimé et un dispositif électronique, la structure de ligne d'une carte de circuit imprimé étant appliquée à une carte de circuit imprimé (2) configurée avec un composant (1), et la carte de circuit imprimé (2) étant une carte de circuit imprimé multicouche dont le nombre de couches est égal ou supérieur à deux ; une ligne de la carte de circuit imprimé (2) comprend une section de ligne (31) qui passe à travers une zone de projection orthographique du composant (1) ; la section de ligne (31) comprend un nombre pair de couches de câblage, chaque couche de câblage de la section de ligne (31) est respectivement disposée sur une couche différente de la carte de circuit imprimé (2), chaque couche de câblage de la section de ligne (31) est connectée en séquence au moyen d'une section de connexion (313), et les directions des courants de deux couches adjacentes de câblage de la section de ligne (31) sont opposées.
PCT/CN2019/116594 2018-12-03 2019-11-08 Structure de ligne de carte de circuit imprimé, ensemble carte de circuit imprimé et dispositif électronique WO2020114193A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811466251.3 2018-12-03
CN201811466251.3A CN109379839A (zh) 2018-12-03 2018-12-03 一种电路板线路结构、电路板组件和电子设备

Publications (1)

Publication Number Publication Date
WO2020114193A1 true WO2020114193A1 (fr) 2020-06-11

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PCT/CN2019/116594 WO2020114193A1 (fr) 2018-12-03 2019-11-08 Structure de ligne de carte de circuit imprimé, ensemble carte de circuit imprimé et dispositif électronique

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WO (1) WO2020114193A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109379839A (zh) * 2018-12-03 2019-02-22 维沃移动通信有限公司 一种电路板线路结构、电路板组件和电子设备
EP4210446A4 (fr) * 2020-09-11 2024-07-31 Guangdong Oppo Mobile Telecommunications Corp Ltd Structure de circuit, batterie, dispositif électronique et procédé de fabrication de batterie
CN114173542A (zh) * 2020-09-11 2022-03-11 Oppo广东移动通信有限公司 电路结构、电池、电子设备及电池的制造方法
CN216565726U (zh) * 2021-12-29 2022-05-17 长春捷翼汽车零部件有限公司 一种低电磁干扰的pcb板、电源分配单元及车辆

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JPH05120928A (ja) * 1991-10-25 1993-05-18 Sumitomo Wiring Syst Ltd フラツト回路体
CN1129993A (zh) * 1993-08-31 1996-08-28 摩托罗拉公司 水平扭绞对型平面导线结构
US5835979A (en) * 1994-06-02 1998-11-10 Fujitsu Limited Wiring pattern preventing EMI radiation
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CN107535047A (zh) * 2015-05-14 2018-01-02 索尼公司 电路板、图像拍摄元件以及电子装置
CN109379839A (zh) * 2018-12-03 2019-02-22 维沃移动通信有限公司 一种电路板线路结构、电路板组件和电子设备

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US8913364B2 (en) * 2011-12-20 2014-12-16 Intel Corporation Decoupling arrangement

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120928A (ja) * 1991-10-25 1993-05-18 Sumitomo Wiring Syst Ltd フラツト回路体
CN1129993A (zh) * 1993-08-31 1996-08-28 摩托罗拉公司 水平扭绞对型平面导线结构
US5835979A (en) * 1994-06-02 1998-11-10 Fujitsu Limited Wiring pattern preventing EMI radiation
CN102014602A (zh) * 2010-12-17 2011-04-13 深圳宏伍智能光电有限公司 一种提高大功率器件及大功率器件模组电磁兼容性能的设计方法
CN107535047A (zh) * 2015-05-14 2018-01-02 索尼公司 电路板、图像拍摄元件以及电子装置
CN109379839A (zh) * 2018-12-03 2019-02-22 维沃移动通信有限公司 一种电路板线路结构、电路板组件和电子设备

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