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WO2018229978A1 - Carte de circuit imprimé - Google Patents

Carte de circuit imprimé Download PDF

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Publication number
WO2018229978A1
WO2018229978A1 PCT/JP2017/022361 JP2017022361W WO2018229978A1 WO 2018229978 A1 WO2018229978 A1 WO 2018229978A1 JP 2017022361 W JP2017022361 W JP 2017022361W WO 2018229978 A1 WO2018229978 A1 WO 2018229978A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring line
pattern layer
conductor pattern
wiring
conductor
Prior art date
Application number
PCT/JP2017/022361
Other languages
English (en)
Japanese (ja)
Inventor
藤之 中本
佐々木　雄一
尚人 岡
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2017/022361 priority Critical patent/WO2018229978A1/fr
Publication of WO2018229978A1 publication Critical patent/WO2018229978A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a printed wiring board having a noise filter.
  • Patent Document 1 Japanese Patent Laid-Open No. 2017-34115 discloses a printed wiring board having a wiring pattern that can suppress deterioration of noise removal performance caused by such parasitic inductance.
  • the printed wiring board disclosed in Patent Document 1 has a structure in which an upper wiring layer and a lower wiring layer are laminated via an insulating layer.
  • first and second wiring lines extending in parallel with each other and arranged to face each other are formed.
  • One end of the first wiring line is electrically connected to the bypass capacitor, and the other end of the first wiring line is in series with one end of the second wiring line through the lower wiring layer. It is connected.
  • These first and second wiring lines are arranged to face each other so as to form a mutual inductance by magnetic coupling.
  • the negative inductance appearing equivalently corresponding to the mutual inductance cancels out the parasitic inductance of the bypass capacitor and the connection wiring, so that the deterioration of the noise removal performance of the bypass capacitor can be suppressed.
  • Japanese Patent Laying-Open No. 2017-34115 (for example, FIGS. 2A and 2B and paragraphs 0020 to 0030)
  • an object of the present invention is to provide a printed wiring board that can ensure high noise removal performance even in the presence of magnetic flux generated from mounted components and wiring on the printed wiring board.
  • a printed wiring board includes a first conductor pattern layer, a second conductor pattern layer disposed away from the first conductor pattern layer in a thickness direction of the first conductor pattern layer, and the first conductor pattern layer.
  • a printed wiring board having a laminated structure including an insulating layer interposed between one conductor pattern layer and the second conductor pattern layer, and is formed as a part of the first conductor pattern layer and electrically
  • a main wiring having a connection end for connecting to the first wiring, and a first connection conductor that is electrically connected to the main wiring and extends in the thickness direction from the first conductor pattern layer to the second conductor pattern layer;
  • a first wiring line formed as a part of the second conductor pattern layer and having one end electrically connected to the main wiring via the first connection conductor; and the other end of the first wiring line;
  • the second conductor pad A second connection conductor extending in the thickness direction from the first layer to the first conductor pattern layer, and formed as another part of the first conductor pattern layer, and the second connection conductor via the
  • a negative inductance can be formed by forming a magnetic coupling in the thickness direction between the first wiring line and the second wiring line. Since the magnetic coupling in the thickness direction is not easily affected by magnetic flux generated from a mounted component or other wiring on the printed wiring board, a negative inductance sufficient to cancel the parasitic inductance can be formed. Therefore, high noise removal performance can be obtained even in the presence of magnetic flux generated from the mounted components on the printed wiring board and other wiring.
  • FIG. 1A to 1C are diagrams showing a schematic configuration of a printed wiring board according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic diagram illustrating a main part of a cross-sectional configuration of the printed wiring board according to the first embodiment.
  • 3A is a diagram illustrating an example of a mutual induction circuit including a pair of parasitic inductors
  • FIG. 3B is a diagram illustrating a T-type equivalent circuit corresponding to the mutual induction circuit of FIG. 3A.
  • FIG. 3 is a diagram schematically showing a main part of an equivalent circuit of the printed wiring board according to the first embodiment. It is the schematic which shows the principal part of the cross-sectional structure of the printed wiring board which is Embodiment 2 of the modification of Embodiment 1.
  • FIG. 3 is a schematic diagram illustrating a main part of a cross-sectional configuration of the printed wiring board according to the first embodiment.
  • 3A is a diagram illustrating an example of a mutual induction circuit including
  • FIG. 1A to 1C are diagrams showing a schematic configuration of a printed wiring board 1 according to Embodiment 1 of the present invention.
  • FIG. 1A is a diagram schematically showing a cross-sectional structure of the printed wiring board 1 in the YZ plane (a plane parallel to both the Y axis and the Z axis).
  • 1B and 1C are diagrams showing the planar configurations of the first conductor pattern layer PL1 and the second conductor pattern layer PL2 in the printed wiring board 1, respectively.
  • 1B and 1C show the planar configurations of the first conductor pattern layer PL1 and the second conductor pattern layer PL2 when viewed from the Z-axis positive direction side.
  • the printed wiring board 1 includes a first conductor pattern layer PL1 formed on both front surfaces in the thickness direction of the insulating layer IL0, and a second conductor pattern formed on the back surfaces of the both surfaces.
  • the insulating layer IL0 only needs to be made of an electrically insulating material such as a nonconductive resin.
  • the thickness of the insulating layer IL0 is not particularly limited as long as it is adjusted within a range of 0.05 mm to several mm, for example.
  • the front surface of the printed wiring board 1 is a mounting surface on which circuit elements such as an LSI (Large Scale Integrated Circuit), an IC (Integrated Circuit), a power supply circuit element, and a capacitor element can be mounted.
  • circuit elements such as an LSI (Large Scale Integrated Circuit), an IC (Integrated Circuit), a power supply circuit element, and a capacitor element can be mounted.
  • a circuit element 11, a connector circuit 12, and a capacitive element 13 are provided on the first conductor pattern layer PL1.
  • the connector circuit 12 is a circuit element that is electrically connected to the external power source 2 such as a DC-DC converter or an in-vehicle battery.
  • the capacitive element 13 is mounted as a bypass capacitor for removing electromagnetic noise in a high frequency band.
  • the first conductor pattern layer PL1 is electrically connected to the main wirings 20 and 22 that are electrically connected to the circuit element 11 and the connector circuit 12, respectively, and to the circuit element 11 and the connector circuit 12, respectively.
  • the wiring pattern includes connection wirings 28 and 29 to be connected and connection wirings 23 and 24 to be electrically connected to both electrode terminals of the capacitive element 13.
  • the wiring pattern of the first conductor pattern layer PL1 can be formed by patterning a conductive thin film such as a copper foil using a known selective etching technique.
  • the second conductor pattern layer PL2 is disposed at a position away from the first conductor pattern layer PL1 in the thickness direction (Z-axis negative direction) of the multilayer structure.
  • the second conductor pattern layer PL ⁇ b> 2 is a conductor composed of a connection wiring 21 formed in the wiring pattern region 30 and a ground conductor surface 31 formed in the entire region other than the wiring pattern region 30. Has a pattern.
  • the ground conductor surface 31 is connected to the ground potential.
  • the ground conductor surface 31 is formed in a region that is electrically insulated from the connection wiring 21 in the wiring pattern region 30.
  • the conductor pattern of the second conductor pattern layer PL2 can be formed by patterning a conductive thin film such as a copper foil using a known selective etching technique.
  • Via conductors Va, Vb, Vc, Vd, Ve are provided in the insulating layer IL0 interposed between the first conductor pattern layer PL1 and the second conductor pattern layer PL2.
  • These via conductors Va to Ve are connection conductors extending in the thickness direction (Z-axis direction) from the first conductor pattern layer PL1 to the second conductor pattern layer PL2 inside the insulating layer IL0.
  • the via conductors Va and Vb are connection conductors (first and second connection conductors) that conduct to the wiring pattern region 30 of the second conductor pattern layer PL2.
  • the end portions of the other via conductors Vc, Vd, and Ve all function as ground lines that are electrically connected to the ground conductor surface 31.
  • a step of filling the conductive paste instead of the step of filling the conductive paste, a step of forming a metal layer inside the interlayer connection hole by electroless plating may be employed.
  • the main wiring 20 (hereinafter also referred to as “first main wiring 20”) of the first conductor pattern layer PL1 is electrically connected between the power supply terminal of the circuit element 11 and the via conductor Va.
  • the power supply wiring pattern to be A connection end 20a forming one end of the first main wiring 20 is connected to the power supply terminal of the circuit element 11, and the other end 20b of the first main wiring 20 is connected to the via conductor Va.
  • the ground terminal of the circuit element 11 is electrically connected to the ground conductor surface 31 of the second conductor pattern layer PL2 via the connection wiring 28 and the via conductor Vd.
  • connection wiring 21 includes a wiring line 21i (hereinafter referred to as “first wiring line 21i”) extending from the via conductor Va in the negative Y-axis direction, and a via conductor from the left end portion of the first wiring line 21i.
  • the wiring line 21j extends to Vb.
  • the portion where the first wiring line 21i and the wiring line 21j intersect constitutes a bent portion that is bent at a right angle, but is not limited to the shape of the bent portion.
  • the bent portion may have a smooth shape (for example, an arc shape or an elliptic arc shape) or a polygonal shape instead of a shape that bends at 90 °.
  • the main wiring 22 (hereinafter also referred to as “second main wiring 22”) of the first conductor pattern layer PL1 is electrically connected to the plus terminal of the external power source 2 via the connector circuit 12. It is a power supply wiring pattern to be connected.
  • a connection end 22b forming one end of the second main wiring 22 is connected to the connector circuit 12, and the other end 22a of the second main wiring 22 is connected to the via conductor Vb.
  • the ground terminal of the connector circuit 12 is electrically connected to the negative terminal of the external power supply 2, and the connection wiring 29 connects the ground terminal to the via conductor Ve. Therefore, the ground terminal of the connector circuit 12 is electrically connected to the ground conductor surface 31 of the second conductor pattern layer PL2 via the connection wiring 29 and the via conductor Ve.
  • the second main wiring 22 is connected to an inverted L-shaped bent wiring line 22d having one end connected to the via conductor Vb and the other end of the bent wiring line 22d.
  • Linear wiring line 22i (hereinafter referred to as "second wiring line 22i").
  • the second wiring line 22i is arranged at a position facing and close to the first wiring line 21i of the second conductor pattern layer PL2 in the thickness direction (Z-axis direction). For this reason, the first wiring line 21i and the second wiring line 22i are disposed so as to face each other (that is, between the first conductor pattern layer PL1 and the second conductor pattern layer PL2).
  • the second wiring line 22i is connected in series with the first wiring line 21i on the back surface side via the bent wiring line 22d, the via conductor Vb, and the wiring line 21j. Therefore, the directions of the currents flowing in the first wiring line 21i and the second wiring line 22i are the same direction. Further, the direction of the magnetic flux generated due to the parasitic inductance of the first wiring line 21i and the second wiring line 22i is almost the same.
  • the second wiring line 22i extends in the Y-axis direction, it extends along the extending direction of the first wiring line 21i.
  • the extending direction of the second wiring line 22i is the same as the extending direction of the first wiring line 21i.
  • the first wiring line 21i and the second wiring line 22i are arranged so as to form an equivalent negative inductance by being magnetically coupled in the thickness direction.
  • the capacitive element 13 has a pair of electrode terminals.
  • One electrode terminal of the capacitive element 13 is electrically connected to the via conductor Vb and the other end 22a of the second main wiring 22 via the connection wiring (lead-out wiring) 23, and the other electrode terminal of the capacitive element 13 is connected to the via conductor Vb. It is electrically connected to the via conductor Vc through the connection wiring (drawing wiring) 24.
  • the via conductor Vc electrically connects the other electrode terminal of the capacitive element 13 to the ground conductor surface 31 of the second conductor pattern layer PL2.
  • Such a capacitive element 13 functions as a bypass capacitor that releases (bypasses) high-frequency electromagnetic noise propagating through the first conductor pattern layer PL1 to the ground line.
  • FIG. 2 is a schematic diagram showing a cross-section of the main part of the printed wiring board 1 according to the first embodiment.
  • FIG. 2 shows a part of the cross section of the printed wiring board 1 taken along the line II-II in FIGS. 1B and 1C.
  • the first wiring line 21 i and the second wiring line 22 i are disposed close to and opposed to each other in the thickness direction (Z-axis direction) between the layers.
  • the first wiring line 21i and the second wiring line 22i have a constant wiring thickness ⁇ Z (for example, several tens of ⁇ m) and a constant wiring width ⁇ X (for example, several hundreds of ⁇ m).
  • the first wiring line 21i and the second wiring line 22i are opposed to each other by the wiring width ⁇ X.
  • the first wiring line 21i and the second wiring line 22i are magnetically coupled in the thickness direction to cause mutual induction. At this time, a magnetic flux is generated between the first wiring line 21i and the second wiring line 22i.
  • the noise filter according to the present embodiment includes a first wiring line 21 i, a second wiring line 22 i, and a capacitive element 13.
  • M 0 ( ⁇ 0 / (2 ⁇ )) ⁇ R ⁇ (ln (2R / d) ⁇ 1) (1)
  • R is a common length (unit: m) of the two conductors
  • d is an interval (unit: m) between the two conductors
  • the approximate expression (1) is established when the length R is sufficiently larger than the interval d.
  • the mutual inductance magnitude M between the first wiring line 21i and the second wiring line 22i can be designed using the above equation (1). At this time, it is possible to design the magnitude M of the mutual inductance in consideration of the parasitic inductance of the connection wirings (lead wirings) 23 and 24 used for mounting the capacitive element 13.
  • the first wiring line 21i and the second wiring line 22i have a pair of parasitic inductors that are magnetically coupled to cause mutual induction.
  • L1 is the self-inductance of the parasitic inductor of the first wiring line 21i
  • L2 is the self-inductance of the parasitic inductor of the second wiring line 22i.
  • FIG. 3A is a diagram schematically showing a mutual induction circuit including the parasitic inductor 41 of the first wiring line 21i and the parasitic inductor 42 of the second wiring line 22i.
  • FIG. 3B is a diagram showing a T-type equivalent circuit corresponding to the mutual induction circuit of FIG. 3A.
  • the mutual induction circuit of FIG. 3A includes three inductors 51, 52, and 53 each having three inductances L1 + M, L2 + M, and ⁇ M, as shown in FIG. 3B. It can be considered as an equivalent circuit. This type of equivalent circuit is called a T-type equivalent circuit.
  • FIG. 4 is a diagram schematically showing a main part of an equivalent circuit of the printed wiring board 1 of the present embodiment.
  • the equivalent circuit shown in FIG. 4 includes a circuit element 11, the above-described T-type equivalent circuit (FIG. 3B), a capacitive element 13, a parasitic inductor 54 having a wiring inductance L4, and a connector circuit 12.
  • the equivalent inductance of the inductor 51 is L1 + M
  • the equivalent inductance of the inductor 52 is L2 + M.
  • the capacitive element 13 includes a capacitor component 13C having a capacitance C and a parasitic inductor component 13E having a residual inductance Lp that is an equivalent series inductance.
  • the parasitic inductor 54 is mainly formed by the via conductor Vc that connects between the capacitive element 13 and the ground conductor surface 31.
  • the display of other circuit elements of the printed wiring board 1 for example, the resistance component and the parasitic inductor component of the connection wiring 23 is omitted.
  • an inductor 53 having a negative inductance ⁇ M appears equivalently as shown in FIG. That is, the inductor 53 having an equivalent negative inductance ⁇ M is connected to the series connection point Np between the inductors 51 and 52. At this time, an inductor 53 having a negative inductance ⁇ M, a capacitor component 13C, a parasitic inductor component 13E having a residual inductance Lp, and a parasitic inductor 54 having a wiring inductance L4 between the series connection point Np and the ground point. Are connected in series. If the negative inductance ⁇ M is designed to cancel the residual inductance Lp and the wiring inductance L4, the impedance of the bypass circuit can be equivalent to the impedance of only the capacitor component 13C.
  • the bypass circuit according to the present embodiment includes the connection wiring 23, the capacitor element 13, the connection wiring 24, and the via conductor Vc.
  • the wiring inductance L4 of the via conductor Vc can be approximately calculated based on the dimensions (for example, length and via diameter) and the material of the via conductor Vc.
  • the residual inductance Lp can be calculated by measuring the characteristics of the capacitive element 13. Therefore, the impedance of the bypass circuit is reduced by designing the negative inductance ⁇ M so that the impedance cancels out with respect to the negative inductance ⁇ M, the wiring inductance L4 of the via conductor Vc, and the residual inductance Lp of the capacitive element 13.
  • the first wiring line 21i and the second wiring line 22i are opposed to each other in the thickness direction (vertical direction) of the laminated structure and in the same direction. It is arranged to extend.
  • the first wiring line 21i and the second wiring line 22i are connected in series via the wiring line 21j, the via conductor Vb, and the bent wiring line 22d. Accordingly, mutual induction can be caused by forming a magnetic coupling in the thickness direction (vertical direction) between the first wiring line 21i and the second wiring line 22i.
  • the negative inductance ⁇ M that appears equivalently corresponding to the magnetic coupling can cancel the parasitic inductance (residual inductance Lp and wiring inductance L4) of the bypass circuit.
  • the magnetic coupling in the thickness direction is not easily affected by magnetic flux generated from the mounted components (circuit element 11 and connector circuit 12) on the first conductor pattern layer PL1 and other wiring (for example, the first main wiring 20). Therefore, a negative inductance ⁇ M sufficient to cancel out parasitic inductances such as the residual inductance Lp and the wiring inductance L4 can be formed. Therefore, the printed wiring board 1 having high noise removal performance can be provided.
  • the first wiring line and the second wiring line are formed in the same layer, and therefore, the magnetic field in the lateral direction perpendicular to the thickness direction. A bond is formed.
  • the magnetic coupling in the lateral direction is susceptible to the magnetic flux generated by the mounting component and other wiring provided in the same layer, and thus forms a negative inductance sufficient to cancel the parasitic inductance. It can be difficult.
  • the inductive coupling when inductive coupling occurs between the mounted component and the first and second wiring lines, or between the other wiring and the first and second wiring lines, the inductive coupling causes the first
  • the lateral magnetic coupling between the first wiring line and the second wiring line is weakened, and a negative inductance sufficient for canceling the parasitic inductance may not be formed.
  • the magnetic coupling in the thickness direction is formed between the layers, so that a negative inductance ⁇ M having a sufficient size for canceling the parasitic inductance can be formed. . Therefore, it is possible to suppress the performance deterioration of the bypass circuit due to the magnetic flux generated from the mounted components on the printed wiring board 1 and other wiring. Further, even if the dimension of the wiring pattern on the printed wiring board 1 (for example, the wiring length) is small, the magnetic coupling having the strength necessary for canceling the parasitic inductance can be ensured. It is possible to increase the possible area (area that the mounting component can occupy).
  • FIG. 5 is a schematic view showing a cross-section of the main part of the printed wiring board according to the second embodiment of the present invention.
  • the structure of the printed wiring board according to the present embodiment is the same as that of the first embodiment except that the magnetic body 60 shown in FIG. 5 is interposed between the first wiring line 21i and the second wiring line 22i.
  • the structure of the printed wiring board 1 is the same.
  • the magnetic body 60 can confine at least a part of the magnetic flux generated between the first wiring line 21i and the second wiring line 22i.
  • the first wiring line 21i and the second wiring line 22i are arranged close to each other and opposed to each other in the thickness direction (Z-axis direction) between the layers.
  • the first wiring line 21i and the second wiring line 22i are magnetically coupled in the thickness direction to cause mutual induction.
  • a magnetic flux is generated between the first wiring line 21i and the second wiring line 22i.
  • a magnetic path through which a magnetic flux passes is formed between the first wiring line 21i and the second wiring line 22i.
  • the value of the coupling coefficient k between the parasitic inductors 41 and 42 of the first wiring line 21i and the second wiring line 22i is the maximum value “1”. Since the magnetic body 60 is arranged in the vicinity of the first wiring line 21i and the second wiring line 22i, the magnetic flux is concentrated inside the magnetic body 60, so that the amount of magnetic flux leaking to the external space of the printed wiring board. Can be reduced. As a result, the coupling coefficient k approaches the value “1”, and the magnitude M of the mutual inductance is increased by the above equation (2). Further, since ⁇ 0 in the above formula (1) is replaced with ⁇ 0 ⁇ ⁇ r ( ⁇ r : complex relative permeability of magnetic material), the magnitude M of mutual inductance is increased.
  • the self-inductances L1 and L2 can be set to small values in accordance with the increase in the coupling coefficient k. Thereby, the line length (wiring length) of the first wiring line 21i and the second wiring line 22i can be shortened. Therefore, the dimensions of the first wiring line 21i and the second wiring line 22i necessary for obtaining the negative inductance ⁇ M can be reduced.
  • Such a magnetic body 60 is preferably a ferrite magnetic body having a high magnetic permeability with respect to a high frequency signal of several MHz or more.
  • the magnetic body 60 may be formed by embedding a resin composition in which soft magnetic metal powder is dispersed in the insulating layer IL0.
  • the magnetic body 60 may be formed by laminating a plurality of ferrite plating films each having a thickness of about several ⁇ m inside the insulating layer IL0.
  • the mountable area of the printed wiring board 1 (the area that can be occupied by the mounted components) can be further increased.
  • the number of conductor pattern layers in the first and second embodiments is two, but is not limited to this.
  • the laminated structure of the first and second embodiments may be appropriately changed so as to constitute a multilayer printed wiring board having three or more conductive pattern layers.
  • a connector circuit 12 that is electrically connected to the external power supply 2 is provided.
  • a power circuit element may be mounted as an internal power source. Even in this case, it is possible to suppress the propagation of high-frequency electromagnetic noise to the mounted power supply circuit element.
  • circuit boards of various electronic devices can be preferably used.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne une carte de circuit imprimé (1) qui présente une structure en couches comprenant une première couche de motif conducteur (PL1), une seconde couche de motif conducteur (PL2), et une couche d'isolation (IL0) située entre la première couche de motif conducteur (PL1) et la seconde couche de motif conducteur (PL2). Une première ligne de câblage (21i) faisant partie intégrante de la seconde couche de motif conducteur (PL2) est formée, et une seconde ligne de câblage (22i) faisant partie intégrante de la première couche de motif conducteur (PL1) est formée. Un élément capacitif (13) est connecté électriquement à une extrémité de la seconde ligne de câblage (22i) ainsi qu'à un potentiel électrique de masse. La seconde ligne de câblage (22i) est connectée en série avec la première ligne de câblage (21i) par l'intermédiaire d'un conducteur de connexion (Vb) s'étendant de la première couche de motif conducteur (PL1) à la seconde couche de motif conducteur (PL2), dans le sens de l'épaisseur. La seconde ligne de câblage (22i) est disposée de manière à s'opposer à la première ligne de câblage (21i) dans le sens de l'épaisseur, et s'étend le long du sens d'extension de la première ligne de câblage (22i).
PCT/JP2017/022361 2017-06-16 2017-06-16 Carte de circuit imprimé WO2018229978A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/022361 WO2018229978A1 (fr) 2017-06-16 2017-06-16 Carte de circuit imprimé

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/022361 WO2018229978A1 (fr) 2017-06-16 2017-06-16 Carte de circuit imprimé

Publications (1)

Publication Number Publication Date
WO2018229978A1 true WO2018229978A1 (fr) 2018-12-20

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PCT/JP2017/022361 WO2018229978A1 (fr) 2017-06-16 2017-06-16 Carte de circuit imprimé

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WO (1) WO2018229978A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6725090B1 (ja) * 2019-10-25 2020-07-15 三菱電機株式会社 光半導体装置
WO2020235092A1 (fr) * 2019-05-23 2020-11-26 三菱電機株式会社 Circuit de filtre
US20230047936A1 (en) * 2020-06-10 2023-02-16 Mitsubishi Electric Corporation Filter circuit
CN116325390A (zh) * 2020-10-20 2023-06-23 三菱电机株式会社 光半导体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007060892A (ja) * 2005-07-25 2007-03-08 Tdk Corp サージ吸収回路
JP2013077663A (ja) * 2011-09-30 2013-04-25 Murata Mfg Co Ltd 回路モジュール
JP2016031965A (ja) * 2014-07-28 2016-03-07 三菱電機株式会社 プリント基板
JP2017034115A (ja) * 2015-08-03 2017-02-09 三菱電機株式会社 プリント基板
JP2017034501A (ja) * 2015-08-03 2017-02-09 三菱電機株式会社 プリント基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007060892A (ja) * 2005-07-25 2007-03-08 Tdk Corp サージ吸収回路
JP2013077663A (ja) * 2011-09-30 2013-04-25 Murata Mfg Co Ltd 回路モジュール
JP2016031965A (ja) * 2014-07-28 2016-03-07 三菱電機株式会社 プリント基板
JP2017034115A (ja) * 2015-08-03 2017-02-09 三菱電機株式会社 プリント基板
JP2017034501A (ja) * 2015-08-03 2017-02-09 三菱電機株式会社 プリント基板

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020235092A1 (fr) * 2019-05-23 2020-11-26 三菱電機株式会社 Circuit de filtre
JP6725090B1 (ja) * 2019-10-25 2020-07-15 三菱電機株式会社 光半導体装置
WO2021079510A1 (fr) * 2019-10-25 2021-04-29 三菱電機株式会社 Dispositif à semi-conducteur optique
CN114556724A (zh) * 2019-10-25 2022-05-27 三菱电机株式会社 光半导体装置
CN114556724B (zh) * 2019-10-25 2024-04-02 三菱电机株式会社 光半导体装置
US20230047936A1 (en) * 2020-06-10 2023-02-16 Mitsubishi Electric Corporation Filter circuit
CN116325390A (zh) * 2020-10-20 2023-06-23 三菱电机株式会社 光半导体装置

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