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WO2020001553A1 - 氮化镓器件和集成电路的栅极驱动电路及电压调节器 - Google Patents

氮化镓器件和集成电路的栅极驱动电路及电压调节器 Download PDF

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Publication number
WO2020001553A1
WO2020001553A1 PCT/CN2019/093350 CN2019093350W WO2020001553A1 WO 2020001553 A1 WO2020001553 A1 WO 2020001553A1 CN 2019093350 W CN2019093350 W CN 2019093350W WO 2020001553 A1 WO2020001553 A1 WO 2020001553A1
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Prior art keywords
ehemt
voltage
dhemt
hemt
gallium nitride
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PCT/CN2019/093350
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English (en)
French (fr)
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李湛明
傅玥
刘雁飞
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李湛明
傅玥
刘雁飞
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Priority claimed from US16/449,356 external-priority patent/US10686411B2/en
Application filed by 李湛明, 傅玥, 刘雁飞 filed Critical 李湛明
Priority to CN201980056656.6A priority Critical patent/CN112640124B/zh
Publication of WO2020001553A1 publication Critical patent/WO2020001553A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
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    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
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    • H03K17/06—Modifications for ensuring a fully conducting state
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    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to a gallium nitride-based power electronic device and an integrated circuit. More specifically, the present invention relates to a gallium nitride power device gate drive and voltage regulator and its implementation in a gallium nitride integrated circuit.
  • gallium nitride platforms include silicon-based gallium nitride, sapphire substrate gallium nitride, and gallium nitride on gallium nitride substrates. Regardless of the substrate material used, a common challenge is the mismatch of the gate drive voltage, which is much lower than the same type of silicon-based devices, which makes it possible to directly replace silicon-based MOSFETs or IGBTs in existing power power electronics systems. Become difficult. Lower gate drive voltage reduces the ability of GaN devices to resist drive voltage noise, thereby reducing system reliability.
  • a common solution to overcome this mismatch is to use a low-voltage MOSFET as the front end in a cascaded configuration.
  • this method has the problem of channel leakage current mismatch between two different transistors, which reduces the reliability and performance of such cascaded devices compared to high electron mobility transistor (HEMT) devices.
  • HEMT high electron mobility transistor
  • Another aspect of the present invention relates to a gallium nitride-based gate input integrated circuit (IC) that includes two to four enhanced high electron mobility tubes (EHEMT) and a series connected
  • the depletion type high electron mobility tube is composed of DHEMT (source-to-drain).
  • the connection is such that the gate of EHEMT is connected to the drain; the gate of DHEMT is connected to the source; the input of the gate input integrated circuit is DHEMT. Drain, whose output is the source of the DHEMT.
  • the output of the gate input integrated circuit can be used as a gate driver for at least one gallium nitride power transistor.
  • the DHEMT is integrally integrated with multiple EHEMTs having different channel lengths and widths, and the voltage rating of all components is lower than the power transistor.
  • the DHEMT and the integrated EHEMTs are implemented using the same technology with the same channel length, and the channel width of the DHEMT is 17% to 25% of the minimum EHEMT.
  • the EHEMTs are implemented using an arrangement that includes two metals: the gate metal 2 is parallel to the EHEMT gate strip; the gate metal 2 is located on the side next to the adjacent drain (gate strip); the short metal 2 panel Connected to the gate bar and the drain terminal.
  • the main power transistor and the gate input integrated circuit are arranged such that the main power transistor includes two power transistors connected in parallel, and the bars of the two power transistors are parallel; one of the power transistors is shorter than the other of the power transistors. One edge of the shorter power transistor is aligned with the edge of the longer power transistor, and the other edge of the shorter power transistor defines a rectangular wafer space on the mold; the source and drain arrangements of the two power transistors make the mold The rectangular wafer space is surrounded by the source of two power transistors; the gate input drives multiple transistors (DHEMT and EHEMTs) in series and are distributed in the rectangular wafer space.
  • DHEMT and EHEMTs multiple transistors
  • the DHEMT of the gate input integrated circuit is asymmetric and has a large drain to accommodate a lead pad or a ground grid array (LGA) or a ball grid array (BGA). Metal bumps.
  • LGA ground grid array
  • BGA ball grid array
  • auxiliary voltage regulator integrated circuit based on gallium nitride
  • the auxiliary voltage regulator integrated circuit comprising four to six EHEMTs connected in series with a DHEMT (source to drain),
  • One of the large EHEMTs is parallel to the DHEMT, the gate of a smaller EHEMT is connected to the drain electrode, the gate of the DHEMT is connected to the source electrode; the gate of the larger EHEMT is connected to the source of the DHEMT, and the gate of the larger EHEMT is The drain is connected to the drain of the DHEMT; the input of the integrated circuit is the drain of the DHEMT; the output of the integrated circuit is the source of the larger EHEMT.
  • the DHEMT is integrated with a plurality of EHEMTs having different channel lengths and widths, and the larger EHEMTs have the largest channel width, and the voltage rating of all integrated circuit components is lower than the main power transistor.
  • the DHEMT and the integrated EHEMTs use the same technology with the same channel length to implement the EHEMTs and DHEMT, and the DHEMT channel width is 3% to 5% of the minimum EHEMT.
  • the EHEMTs have the same size, and they are arranged as follows: all small-sized EHEMTs have grid bars parallel to all the tips, aligned to form a separate column (or row); each EHEMT has a relative to the phase
  • the adjacent EHEMT flips the source and drain (ie, alternate sides); and the source and drain of each EHEMT use two layers of metal to connect to the opposite electrode of its adjacent EHEMT.
  • the opposite electrode refers to the source of each EHEMT
  • the drains of adjacent EHEMTs are connected, and the drains are connected to the sources of adjacent EHEMTs.
  • one EHEMT is larger, and the gate bars are arranged perpendicular to the smaller EHEMTs; its smaller sides are the same as the array width of the smaller EHEMTs, so the entire integrated circuit is arranged to form a rectangular block.
  • the main power transistor and the rectangular block of the integrated circuit are arranged such that the main power transistor includes two power transistors connected in parallel; wherein the bars of the two power transistors are parallel; the bars of one power transistor are shorter than those of the other power transistor.
  • One edge of the shorter power transistor is aligned with the edge of the longer power transistor, while the other edge of the shorter power transistor defines a rectangular space on the wafer mold; where the source and drain of the two power transistors
  • the arrangement of the electrodes makes the rectangular space surrounded by the sources of the two power transistors; among them, four to six voltage rectangular blocks of EHEMT and DHEMT are placed on the outer edges of the rectangular space.
  • Fig. 1 is a schematic diagram of a gate driving circuit of a gallium nitride power transistor according to an embodiment.
  • FIG. 2 is a schematic diagram showing an equivalent circuit of the voltage stabilizing circuit in FIG. 1.
  • FIG. 3A is a schematic diagram illustrating how an increase in drain current causes a negative voltage feedback for stabilizing a gate voltage of a gallium nitride power transistor.
  • FIG. 3B shows the relationship between the electron velocity and the field of the channel of a D-mode high electron mobility transistor (DHEMT).
  • DHEMT D-mode high electron mobility transistor
  • Fig. 3c is a characteristic curve showing the leakage current-voltage of DHEMT M3 at zero gate voltage.
  • FIG. 4 shows a layout diagram of an E-mode HEMT using two metal layers (metal1 and metal2) in the prior art.
  • Fig. 5 is a D-mode HEMT layout using two metal layers (metal1 and metal2) with a source and a gate short according to an embodiment.
  • Fig. 6 is a layout of an E-mode HEMT with gate and drain shorts according to an embodiment.
  • Fig. 7 is a layout of a gate input integrated circuit module near a source side of a main gallium nitride power transistor according to an embodiment.
  • FIG. 8 is a detailed view of the layout of the gate input integrated circuit module near the source side of the main gallium nitride power transistor shown in FIG. 7, where two rectangular high voltage main power transistors accommodate the gate input integrated circuit in parallel.
  • Fig. 9 is a detailed view of a DHEMT layout of a gate input integrated circuit module near a source side of a main gallium nitride power transistor according to an embodiment.
  • Fig. 10 is a detailed view showing a layout of a gate input integrated circuit module near a source side of a main gallium nitride power transistor according to an embodiment, wherein a gate metal strip of the main transistor faces a horizontal direction.
  • FIG. 11 is a schematic diagram of a voltage transfer characteristic of a gate driving module obtained by simulating two cases.
  • FIG. 12 is a schematic diagram of a current-voltage characteristic of a gate driving module obtained by simulating two cases.
  • FIG. 14 is a schematic diagram showing the pulse output response of the main EHEMT with respect to the input driving pulses of the two gate driving module designs obtained through simulation.
  • FIG. 15 is a schematic diagram showing a pulse current response of two gate driving modules having different gate widths obtained through simulation.
  • Fig. 16 is a schematic diagram showing a gate driving circuit according to another embodiment.
  • Fig. 17 is a schematic diagram of an equivalent circuit of the voltage stabilization circuit according to the embodiment shown in Fig. 16.
  • Fig. 18 is a layout diagram of a gate-drain short-circuit EHEMT according to an embodiment.
  • FIG. 19 is a schematic diagram of regulator modules distributed in a rectangular block according to FIG. 16.
  • FIG. 20 shows a detailed view of the distribution of four EHEMTs in the layout embodiment according to FIG. 19.
  • FIG. 21 is a detailed view of the DHEMT distribution in the embodiment of the layout according to FIG. 19.
  • 22A and 22B are schematic diagrams of voltage transfer characteristics and current voltage characteristics of a voltage reference branch of a voltage regulator module obtained through simulation, respectively.
  • FIG. 23 is a schematic diagram showing how a regulator module can be used as an auxiliary power source for a gate driver according to an embodiment.
  • FIG. 24 is a schematic diagram showing the layout of the auxiliary power supply in FIG. 23 according to an embodiment for driving a single power EHEMT.
  • FIG. 25 is a schematic diagram illustrating the layout of the auxiliary power source in FIG. 23 according to an embodiment for driving two power EHEMTs in parallel.
  • FIG. 26 is a schematic diagram of an auxiliary power source layout in FIG. 23 according to another embodiment for driving two power electron beams in parallel.
  • 27A and 27B are graphs showing input voltage pulses and auxiliary voltage outputs, respectively, obtained from the simulation of the embodiment of FIG. 23 and the layout of FIG. 24 for the main power source EHEMT with a rated maximum current rating of 8A.
  • 28A and 28B are graphs showing a gate driving voltage and a gate current obtained from the simulation of the embodiment of FIG. 23 and the layout of FIG. 24, respectively, for a main power source EHEMT with a rated maximum current of 8A.
  • the gate drive voltage and channel leakage current between two different transistor technologies do not match, thereby reducing reliability and performance.
  • the gate drive voltage of silicon-based power electronics is typically between 10 and 15 volts.
  • the gate drive voltage of a GaN HEMT is much lower, ranging from 3 to 6 volts.
  • One aspect of the present invention relates to a voltage stabilization and / or regulation circuit implemented with GaN HEMT technology, which provides applications suitable for applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits Stable output voltage. Therefore, some embodiments may advantageously take advantage of the 2DEG characteristics of gallium nitride devices.
  • the embodiments of the present invention can be implemented by using the gallium nitride integrated circuit method technology, and the cost of the chip area is low.
  • some embodiments may be implemented in a 650V silicon-based gallium nitride process.
  • the E mode can be implemented using the p-gan layer, but the present invention is not limited to this, because the embodiments in the E mode can also be implemented using other technologies.
  • the gate driver embodiments can be designed according to the guidelines of the 100V rule, and virtually any technology in the 30-100V range is suitable.
  • this embodiment may use a bimetal layer process, of course, the present invention is not limited thereto.
  • the gate driver, the gate driving circuit, and the gate driving module are all the same object.
  • M4 is a main power transistor, and M1, M2, and M3 are gate driving modules of M4 (also referred to as “gate input module”).
  • M4 is a high voltage (HV) EHEMT (for example, 650V to 1200V)
  • M1 and M2 are two similar or identical low voltage (LV) EHEMTs (for example, 40V to 100V)
  • M3 is a low voltage DHEMT.
  • M3 can use the same channel / gate function as M1 and M2.
  • the input driving voltage Vgi of the gate driving module is 10V to 30V
  • the gate voltage Vg of M4 is 6V; however, other voltages are also feasible.
  • the topology of M1, M2, and M3 provides voltage downshift and overvoltage protection to provide M4 with a suitable gate drive voltage.
  • the equivalent circuit of M1, M2, and M3 in the embodiment of FIG. 1 is shown in FIG. 2.
  • DHEMT M3 can be regarded as a variable resistor R
  • two EHEMTs M1 and M2 can be regarded as a Zener diode D.
  • FIG. 1 An advantage of the embodiment of FIG. 1 can be explained by considering the electron velocity (proportional to the electron current in the DHEMT channel) plotted in FIG. 3B.
  • the electron saturation behavior exhibits a negative differential resistance (Turin, V.O., an improved model of high-field mobility of transferred electrons for GaN device S, Solid State Electronics 49: 1678–16822005). Due to the different channel scattering mechanism and the measurement from low frequency to DC, no negative resistance was obtained. Therefore, it is common practice to model the electronic velocity characteristics as a flat line (as shown in Figure 3B).
  • the flat line indicates that the resistance of the DHEMT is variable. At higher bias voltages, the resistance is higher, which reduces the voltage stress on the main EHEMT M4 gate.
  • EHEMT M1 and M2 are configured with a unique gate-to-drain short circuit connection.
  • This structure effectively establishes a negative voltage feedback loop as shown below: the increase in dVg (short circuit) at the drain / gate is amplified to the drain current + id Increase (see Figure 3A).
  • the increase in the drain current enhances the voltage drop across the load, thereby reducing dVg (see "-dVg1" in Figure 3A), which completes the negative feedback.
  • FIG. 4 shows the various layers of the manufacturing process, where Metal 1 and Metal 2 are the two top metal layers above the device for making electrodes, and the vias are between the metal 1 and metal 2 layers.
  • the opening of the insulating layer is filled with metal to connect Metal 1 and Metal 2.
  • Figures 5-10, 18-21, and 24-26 are the same, although the pad openings in Figures 8-10, 19, and 24-26 are the top protective coating openings through which electrode contact is made.
  • G, D, and S represent the gate, drain, and source, respectively.
  • the gate metal can be entered through two metal layers (metal 1 and metal 2, connected through a via).
  • the source and drain can only form channels through metal 2.
  • the bimetal layer technology DHEMT layout is shown in Figure 5, where the gate is shorted to the power supply to provide a stable bias for the conduction channel.
  • Device manufacturing is to achieve the natural D mode of HEMT.
  • gate driver module For power integrated circuit layout, how to place a gate driver module (gate driver module) relative to the main power transistor is very important. Several factors must be considered. First, the gate drive module must be close enough to the gate electrode of the main power transistor to reduce parasitic inductance. Secondly, in order to reduce the cost of wafer space, the gate drive module must occupy as small an area as possible. Third, the gate drive module must be shielded from the high-voltage drain to avoid electromagnetic interference.
  • this figure shows an embodiment of the layout of the power module integrated circuit.
  • the position of the gate drive module is shown in the upper left corner relative to the rest of the power module integrated circuit.
  • the main transistor is divided into two rectangular areas of parallel EHEMTs, thereby leaving a small rectangular area of the size required by the gate drive module.
  • Dashed lines A-B separate two parallel connected rectangular main transistors into M4. It is worth noting that the gate drive module integrated circuit is close to the source side of two main transistors in parallel.
  • FIG. 8 is a more detailed view of the layout of the gate driving module of the embodiment of FIG. 7.
  • the output of the gate drive module is connected to the top gate track on the metal layer (G-Metal1). Connected through a via and a drain metal pad of EHEMT M2, the latter is the output point of the gate drive module.
  • the Gi-pad is the input of the gate drive module. It is located on the Metal2 layer. As shown in Gi-metal2, the Gi-pad needs to be enlarged to facilitate device packaging.
  • the GI pad is connected to the drain of the DHEMT M3, but is electrically isolated from other devices.
  • DHEMT M3 uses a unique design, as shown in Figure 9, which is a more detailed view of the layout of Figure 8.
  • Figure 9 is a more detailed view of the layout of Figure 8.
  • the first part is to remove the upper part of the metal2 gate side bar (or the left side when the layout of the gate gate drive module series components is oriented horizontally) to make way for the drain pad.
  • the second is that the source and drain are implemented in an asymmetric manner, making the drain much larger than the source. In this way, the size of the drain pad can be large enough to facilitate lead bonding or metal collision.
  • the layout of the main transistor M4 is such that the gate strip is parallel to the longer direction of the device, and the source and drain are located at both ends of the strip.
  • the gate bars can be positioned in horizontal and longer directions, as shown in FIG. 10.
  • the main power transistor M4 uses two parallel rectangular transistors, separated by horizontal lines A-B, as shown in the power module layout embodiments in FIGS. 7-10.
  • the gate input module is located above the larger main transistor.
  • a 650V process may be used for the main transistor, and a 100V process may be used for low-voltage EHEMTs and DHEMT, although other processes may be used. It is important to design the ratio of the channel width of DHEMT to the channel width of EHEMT to ensure the correct Vg is achieved. For example, in two embodiments where the EHEMT is the same and the DHEMT uses the same high-voltage (LV) technology as the EHEMT, the channel width ratio EHEMT: DHEMT (microns) should be about 350 ⁇ : 75 ⁇ or about 4.7: 1.
  • Scaling by a constant factor in approximately the same order as the units that is, changing the scale, such as 2: 1, 3: 1, 8: 1, 9: 1, etc., where the first number is multiplied by a factor of 0.1 to 9, and the second number Always 1) It will not change the result, but it will affect the resistance of the gate input module and thus the intensity of the discharge / charge current.
  • Size 1 refers to the width of EHEMT: DHEMT 350 ⁇ : 75 ⁇ and size 2 is 700 ⁇ : 150 ⁇ .
  • the results of the gate voltage Vg and the bias voltage Vgi are shown in FIG. 11.
  • the voltage downshift results of the two sizes (size 1 and size 2) are the same.
  • the bias current Igi of the gate drive module is sensitive to the device channel width. For the above channel width, the bias current Igi is shown in FIG. 12. There is a trade-off between the discharge speed of the integrated circuit and the DC power loss: a smaller channel width can reduce the DC power loss, but it will slow down the discharge speed of the main transistor M4. It should be noted that the use of the gate drive module described here will cause the power module (ie, the gate drive module plus the power transistor M4 (eg, two master HEMTs in parallel)) to have a current of 50-100 Amplified bipolar junction transistor (BJT).
  • BJT Amplified bipolar junction transistor
  • Figure 13 shows the input / output impulse response of two channel-sized gate drive modules. DHEMT's low resistance results in clean on / off response without tailing. As expected, larger gate drive modules make switching faster.
  • Figure 14 also shows the relationship between the Vd impulse response of the two channel-sized power transistors and the input voltage of the gate driver module.
  • Figure 15 shows the dc bias current (and therefore power loss) of two channel-sized gate drive modules. It is clear that there is a trade-off between DC power loss and gate delay.
  • M60 is a low-voltage (LV) EHEMT (eg, 40V to 100V) with a larger channel, which provides the current required by the gate driver for the power HEMT.
  • M10 to M40 are smaller low-pressure solenoid valves with the same or similar channel size, and their connections short the gate to the drain.
  • M50 is a DHEMT whose connection shorts the gate to the source. The following will discuss in detail how M10 to M50 function to provide the reference voltage.
  • FIG. 17 The equivalent circuit of the embodiment of FIG. 16 is shown in FIG. 17, where DHEMT M50 can be regarded as a variable resistor R, and four EHEMTs M10 to M40 can be regarded as a Zener diode, which limits the reference voltage to about 7.5 V.
  • the embodiment of FIG. 16 also achieves the aforementioned advantages of the embodiment of FIG. 1 in terms of electronic speed characteristics (see FIG. 3B) and the variable resistance (ie, M50) of the DHEMT in the embodiment of FIG. 16.
  • the benefit of using DHEMT for M50 is also the low resistance at low field or voltage.
  • the high mobility (high initial slope of the upper insertion part in FIG. 3B) makes the DHEMT quickly enter a saturated state, and acts as a variable resistor in the saturated state.
  • the EHEMTs M10 to M40 of FIG. 16 are configured with a unique contact connection distribution having a gate-drain short circuit, which effectively establishes a negative voltage feedback loop as described above.
  • the limit of the number of low-voltage EHEMTs is set according to the reference voltage.
  • the reference voltage is about 7.5V.
  • Vt common threshold gate voltage
  • VT threshold voltage
  • connection mode of the supply current EHEMT m60 is negative feedback, which can be used to stabilize the auxiliary power supply voltage Vcc.
  • M60 negative feedback works as follows: Consider a power supply load between ground and M60 power. Increasing the power supply current in the M60 will increase the M60's power supply voltage, while Vgs will decrease. Decreasing the Vgs of M60 will increase the DC resistance of M60, which will cause the power supply voltage of M60 to increase in the reverse direction. This completes the negative feedback cycle. Obviously, the negative feedback effect is proportional to the transconductance of M60, and the transconductance is proportional to the channel width / area of M60. More stable VCC requires larger transistor size and higher wafer area cost.
  • stable voltage EHEMTs M10 to M40 can be implemented using a metal 2 connection from the drain to the top gate. It should be noted that the width ratio between the low-voltage DHEMT and the low-voltage EHEMT must be carefully set to achieve a stable voltage of 7.5V, as described below.
  • the layout of the regulator must be carefully planned. First, it should be small enough to reduce costs. Second, it should be placed on the edge of the entire module, not between the driver and the main power transistor. Third, the power socket Vcc should be located at the top in order to power the entire driving circuit, which may include an amplifier as shown in the embodiment of FIG. 23.
  • FIG. 19 shows one embodiment of a regulator layout in a rectangular block.
  • the EHEMTs M10 to M40 in the picture are on the lower end, while the larger M60 is on the upper end.
  • the power socket is the power source of the M60, located on the top of the mold.
  • the four EHEMTs M10 to M40 bars are horizontal or vertical to the larger M60 bars, as shown in FIG. 20.
  • the source and drain are alternately arranged from M10 to M40. It is convenient to connect the drain of one HEMT to the source of the next HEMT using a short Metal2 rectangle.
  • the DHEMT M50 is relatively small, as shown in the layout example of FIG. 19 and a more detailed view of FIG. 21.
  • the ratio of the channel widths is such that the width of the DHEMT is about 2-20% of the width of the EHEMTs (eg, M10 to M40). If the channel widths of EHEMTs are not equal but similar, the ratio should be based on the smallest EHEMT.
  • the DHEMT bar is perpendicular to the larger transistor M60 bar, as shown in the embodiment of FIG. 21.
  • FIG. 16 The embodiment of FIG. 16 was simulated using APSYS TM software, and its integrated circuit layout is shown in FIG. 19.
  • FIG. 22A shows an analog voltage transfer characteristic of a regulator integrated circuit
  • FIG. 22B shows a current-voltage characteristic of a regulator voltage reference branch. It can be clearly seen from FIG. 22A that the designed 7.5V is implemented in a wide voltage range above 8V, thereby verifying the design.
  • the DC current through the M10-M40 branch is small, so the DC loss is minimal.
  • the EHEMT channel width of each EHEMT is approximately 400 ⁇ m.
  • FIG. 23 is a schematic diagram showing how a regulator is used with amplifier A, such as a direct coupling field effect transistor logic (DCFL) and a buffer amplifier as an auxiliary power source for a gate driver of a main power transistor M70.
  • the regulator may be integrated with the main power transistor M70 in gallium nitride. It should be noted that turning Vcci down to the required 6V will inevitably lead to power loss, which is proportional to the input voltage Vcci and the current provided by the transistor M60. Therefore, the embodiment can use a lower system voltage, that is, a low-side voltage of 10-30V.
  • the design of the reference voltage branches M10 to M40 can be used to draw a low DC current.
  • FIG. 24 shows an example of a mold layout for the circuit of FIG. 23 including a regulator in the power supply integrated circuit described above and shown in FIG. 19.
  • the main power HEMT M70 bar is parallel to the longer direction of the regulator.
  • the length of the main power HEMT bar is designed to be approximately the same as the longer side of the regulator block.
  • the design height of the amplifier driver block is about the same as the regulator (as shown in Figure 24), it is sandwiched between the main power HEMT M70 and the regulator block.
  • Figures 25 and 26 show mold layouts for two embodiments, including regulators, as shown in Figure 19, but with a main power source HEMT with a larger rated current.
  • a main power source HEMT with a larger rated current.
  • the regulator block is rotated 90 degrees relative to the main power HEMT, with the grid fingers facing vertically.
  • the main power transistor is divided into two parallel EHEMT rectangular areas, leaving a rectangular area of the required size. Dashed lines A-B separate two rectangular main transistors connected in parallel. It is worth noting that the low-voltage block is located near the source of two main transistors in parallel.
  • the layout of the main transistor is such that the gate strip is parallel to the longer direction of the device, and the source and drain are located at both ends of the strip.
  • the gate bars are oriented horizontally and longer, as shown in FIG. 26.
  • the low-voltage block ie regulator and amplifier / driver
  • two parallel rectangular power transistors are separated by a horizontal line AB, and the low-voltage block is located in the larger Above the main transistor.
  • Fig. 23 The embodiment of Fig. 23 and the layout of Fig. 24 were simulated, based on a power HEMT rated at 8A.
  • Fig. 27A shows the simulated input voltage pulse
  • Fig. 27B shows the auxiliary power output Vcc of about 5.5V.
  • the external Vcci is set to 10V.
  • the channel width of the current supply transistor (M60) is set to 6000 ⁇ m. It is expected that using a larger M60 channel WI can achieve better voltage regulation, but at the cost of increasing the chip area.
  • Figures 28A and 28B show the simulated gate drive voltage and gate current of the main power supply EHEMT with a maximum rated current of 8A, respectively. These results, as well as the results shown in Figures 22A and 22B, confirm that the regulator achieves the goal of an auxiliary power source that can use a wide range of DC voltage inputs. Therefore, the embodiment provides a small stamper region voltage regulator suitable for supplying about 6V auxiliary power to a gallium nitride integrated circuit. The input voltage range is large enough to be compatible with all current power system auxiliary power supplies. These embodiments make it possible to implement gallium nitride power equipment in existing power systems.

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Abstract

本发明实施例提供一种氮化镓器件和集成电路的栅极驱动电路及电压调节器，采用氮化镓HEMT技术实现的电压稳定和调压电路能够提供稳定的输出电压，适用于氮化镓功率晶体管栅极驱动器和氮化镓集成电路的低压辅助电源等应用。栅极驱动器和电压调节器模块包括至少一个串联连接在一起的DHEMT和至少两个EHEMTs，以便至少一个DHEMT作为可变电阻工作，并且至少两个EHEMTs作为限制输出的齐纳二极管工作。栅极驱动器和电压调节器模块可以实现作为一个氮化镓集成电路，并且可以在单个芯片上与放大器和功率HEMT等其他组件整体集成，以提供氮化镓HEMT功率模块集成电路。

Description

氮化镓器件和集成电路的栅极驱动电路及电压调节器
相关申请
本申请要求于2018年6月27日提出的第62/690,378号美国专利申请以及于2018年7月6日提出的第62/694,663号美国专利申请的优先权，上述两个美国专利申请的公开内容以引用方式全文并入于此本申请中。
技术领域
本发明涉及氮化镓基电力电子器件及集成电路。更具体的说，本发明有关氮化镓功率器件栅极驱动及电压调节器及其在氮化镓集成电路中的实现。
背景技术
得益于优越的材料特性，例如高击穿电场，高电子饱和速率及在可用的二维电子气(2DEG)沟道中的高电子迁移率，宽禁带氮化镓基电力电子器件在下一代高效率功率器件中的作用越来越大。有了这项技术，在电力电子系统中可以实现高功率密度及高效率。
目前，可用的氮化镓平台包括硅基氮化镓、蓝宝石衬底的氮化镓和氮化镓衬底上的氮化镓。无论采用何种基片材料，一个共同常见的挑战是栅极驱动电压的失配，远低于同类型的硅基器件，这使得在现有的功率电力电子系统中直接替换硅基MOSFET或IGBTS变得困难。较低的栅极驱动电压使氮化镓器件抗驱动电压噪声的能力降低，从而降低了系统的可靠性。
克服这种失配的一个通用解决方案是在级联配置中使用低压MOSFET作为前端。然而，这种方法在两个不同的晶体管之间存在沟道漏电流失配的问题，与高电子迁移率晶体管(HEMT)器件相比，这会降低这种级联器件 的可靠性和性能。
发明内容
本发明的另一方面涉及一种基于氮化镓的栅极输入集成电路(IC)，该栅极输入集成电路包括由两到四个增强型高电子迁移率管(EHEMT)和一个串联连接的耗尽型高电子迁移率管DHEMT(源极到漏极)组成，其连接使得EHEMT的栅极连接到漏极；DHEMT的栅极连接到源极；该栅极输入集成电路的输入是DHEMT的漏极，其输出是DHEMT的源极。该栅极输入集成电路的输出可以用作至少一个氮化镓功率晶体管的栅极驱动器。
在一个实施例中，DHEMT与具有不同沟道长度和宽度的多个EHEMTs整体集成，并且所有组件的额定电压都低于功率晶体管。
在一个实施例中，DHEMT与所集成的EHEMTs采用相同沟道长度的相同技术实现，且DHEMT的沟道宽度为最小EHEMT的17％到25％。
在一个实施例中，EHEMTs采用包含两种金属的排列方式实现：栅极金属2平行于EHEMT栅极条；栅极金属2位于靠近的漏极(栅极条)旁边的侧面；短金属2面板连接到该栅极条和漏极端。
在一个实施例中，主功率晶体管和栅极输入集成电路的排列使得主功率晶体管包含两个并联的功率晶体管，两个功率晶体管的条平行；其中一个功率晶体管的条短于另一个功率晶体管的条；较短功率晶体管的一个边缘为与较长功率晶体管的边缘对齐，且较短功率晶体管的另一边缘在模具上定义矩形晶圆空间；两个功率晶体管的源极和漏极排列使得模具的矩形晶圆空间被两个功率晶体管的源极包围；栅极输入驱动多个串联的晶体管(DHEMT和EHEMTs)被分布在矩形晶圆空间内。
在一个实施例中，栅极输入集成电路的DHEMT不对称，且漏极较大以容纳引线焊盘或接地网阵列(a Land Grid Array，LGA)或球网格阵列(Ball Grid Array,BGA)金属凸起。
本发明的另一方面涉及一种基于氮化镓的辅助电压调节器集成电路(IC)， 该辅助电压调节器集成电路包括四到六个与一个DHEMT(源极到漏极)串联的EHEMTs，其中一个大尺寸EHEMT和DHEMT平行，一个较小的EHEMT的栅极连接到漏电极，DHEMT的栅极连接到源电极；较大的EHEMT的栅极连接到DHEMT的源极，较大的EHEMT的漏极连接到DHEMT的漏极；其中，集成电路的输入端是DHEMT的漏极；集成电路的输出端是较大的EHEMT的源极。
在一个实施例中，DHEMT与具有不同沟道长度和宽度的多个EHEMTs整体集成，且较大的EHEMTs的沟道宽度最大，并且所有集成电路元件的额定电压低于主功率晶体管。
在一个实施例中，DHEMT与所集成的EHEMTs采用相同沟道长度的相同技术将EHEMTs和DHEMT实现，且DHEMT沟道宽度为最小EHEMT的3％到5％。
在一个实施例中，EHEMTs具有相同尺寸，并且它们的排列如下：所有的小尺寸EHEMTs具有与所有条尖平行的栅条，对齐形成一个单独的列(或行)；每个EHEMT具有相对于相邻EHEMT翻转的源极和漏极(即交替侧)；并且每个EHEMT的源极和漏极使用两层金属连接到其相邻的EHEMT的相反电极，相反电极是指每个EHEMT的源极连接相邻的EHEMT的漏极，漏极连接相邻的EHEMT的源极。
在一个实施例中，一个EHEMT更大，并且采用栅极条垂直于较小的EHEMTs的方式排列；其较小的侧面与较小EHEMTs的阵列宽度相同，因此整个集成电路排列形成一个矩形块。
在一个实施例中，主功率晶体管和集成电路矩形块的排列使得主功率晶体管包含两个并联的功率晶体管；其中，两个功率晶体管的条平行；一个功率晶体管的条短于另一个功率晶体管的条；较短的功率晶体管的一个边缘与较长的功率晶体管的边缘对齐，而较短的功率晶体管的另一边缘在晶圆模具上限定矩形空间；其中，两个功率晶体管的源极和漏极排列使得矩形空间被两个功率晶体管的源极包围；其中，四到六个EHEMT和DHEMT的电压矩 形块放置在矩形空间的外缘。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1是根据一实施例示出的氮化镓功率晶体管的栅极驱动电路的示意图。
图2是示出的图1中稳压电路的等效电路的示意图。
图3A是说明漏极电流增加如何引起负电压反馈，该负电压反馈用于稳定氮化镓功率晶体管的栅极电压的示意图。
图3B示出了D模式高电子迁移率晶体管(DHEMT)沟道的电子速度与场的关系曲线。
图3c是显示在零栅极电压下DHEMT M3的漏电流-电压的特性曲线。
图4示出了现有技术中使用两个金属层(metal1和metal2)的E模式HEMT的布局图。
图5是根据一实施例示出的使用源极和栅极短路的两个金属层(metal1和metal2)的D模式HEMT布局。
图6是根据一实施例示出的具有栅极和漏极短路的E模式HEMT的布局。
图7是根据一实施例示出的靠近主氮化镓功率晶体管源侧的栅极输入集成电路模块的布局。
图8是图7所示的主氮化镓功率晶体管源侧附近的栅极输入集成电路模块布局的详细视图，其中两个矩形高压主功率晶体管以并联的方式来容纳栅极输入集成电路。
图9是根据一实施例示出的靠近主氮化镓功率晶体管源侧的栅极输入集 成电路模块的DHEMT布局的详细视图。
图10是根据一实施例示出的显示靠近主氮化镓功率晶体管源侧的栅极输入集成电路模块布局的详细视图，其中主晶体管的栅极金属条朝向水平方向。
图11是通过模拟两个案例获得的栅极驱动模块的电压传递特性的示意图。
图12是通过模拟两个案例获得的栅极驱动模块的电流-电压特性的示意图。
图13是通过模拟获得的显示两个具有不同DHEMT栅极宽度(尺寸1:DHEMT宽度＝75μm；尺寸2:DHEMT宽度＝150μm)的栅极驱动模块的脉冲电压响应的示意图。
图14是通过模拟获得的显示主EHEMT相对于两个栅极驱动模块设计的输入驱动脉冲的脉冲输出响应示意图。
图15是通过模拟获得的显示具有不同栅极宽度的两个栅极驱动模块的脉冲电流响应的示意图。
图16是根据另一个实施例示出的栅极驱动电路的示意图。
图17是根据图16实施例示出的电压稳定电路的等效电路的示意图。
图18是根据一实施例示出的栅极漏极短路EHEMT的布局图。
图19是根据图16所示的分布在矩形块中调节器模块的示意图。
图20示出了根据图19的布局实施例中的四个EHEMTs分布的详细视图。
图21是根据图19布局的实施例中DHEMT分布的详细视图。
图22A和22B分别是通过模拟获得的调压器模块电压参考支路的电压传递特性和电流电压特性的示意图。
图23是根据一实施例示出调节器模块如何用作栅极驱动器的辅助电源的示意图。
图24是根据用于驱动单电源EHEMT的实施例来展示图23中辅助电源布局的示意图。
图25是根据用于并行驱动两个功率EHEMTs的实施例来展示了图23中辅助电源布局的示意图。
图26是根据用于并行驱动两个电力电子束的另一实施例的图23中辅助电源布局的示意图。
图27A和27B是分别显示输入电压脉冲和辅助电压输出的曲线图，从图23的实施例的模拟和图24的布局中获得，用于额定最大电流额定值为8A的主电源EHEMT。
图28A和28B是分别从图23的实施例的模拟和图24的布局中获得的显示栅极驱动电压和门电流的曲线图，用于额定最大电流为8A的主电源EHEMT。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置例子。
详细描述了现有基于硅器件的氮化镓功率晶体管栅极驱动器的缺点，即两种不同的晶体管技术之间的栅极驱动电压和沟道漏电流不匹配，从而降低了可靠性和性能。例如，硅基电力电子器件的栅极驱动电压通常在10到15伏之间。相比之下，氮化镓HEMT的栅极驱动电压要低得多，从3到6伏不等。本发明的一个方面涉及以氮化镓HEMT技术实现的电压稳定和/或调节电路，该技术提供适用于诸如氮化镓功率晶体管栅极驱动器和用于氮化镓集成电路的低压辅助电源等应用的稳定输出电压。因此，一些实施例可以有利地利用氮化镓器件的2DEG特性。本发明实施例可以使用氮化镓集成电路方法技术实现，且晶片面积成本较低。作为示例，一些实施例可在650V硅基氮化镓工艺中实施。E模式可以使用p-gan层来实现，但是，本发明并不限 于此，因为E模式中的实施例也可以使用其他技术来实现。栅极驱动器实施例可根据100V规则的指南进行设计，事实上30-100V范围内的任何技术都是合适的。这里，本实施例可以使用双金属层工艺，当然本发明不限于此。
需要说明的是，本发明各实施例中栅极驱动器、栅极驱动电路和栅极驱动模块均为同一对象。
根据一个实施例的栅极驱动模块，如图1所示，其中M4是主功率晶体管，M1、M2和M3是M4的栅极驱动模块(也称为“栅极输入模块”)。M4是高压(High Voltage，HV)EHEMT(例如，650V至1200V)，M1和M2是两个相似或相同的低压(Low Voltage LV)EHEMT(例如，40V至100V)，M3是低压DHEMT。M3可以使用与M1和M2相同的沟道/闸门功能。在图1的实施例中，栅极驱动模块的输入驱动电压Vgi为10V到30V，M4的栅极电压Vg为6V；然而，使用其他电压也是可行的。
在图1的实施例中，M1、M2和M3的拓扑提供电压降档和过电压保护，以为M4提供合适栅极驱动电压。图1实施例中M1、M2和M3的等效电路如图2所示，其中，DHEMT M3可被视为可变电阻R，且两个EHEMTs M1和M2可被视为稳压齐纳二极管D，将输出电压限制在M4的栅极上，例如6V左右。
图1实施例的一个优点可以通过考虑图3B中绘制的电子速度(与DHEMT沟道中的电子电流成比例)来解释。理论上，电子饱和行为表现出负的微分电阻(Turin，V.O.，氮化镓器件S的一种改进的转移电子高场迁移率模型，《固态电子学》49:1678–16822005)。由于信道散射机制的不同以及低频到直流的测量，没有得到负电阻。因此，通常的做法是将电子速度特性建模为一条扁平线(如图3B所示)。扁平线表示DHEMT的电阻是可变的。在较高的偏压下，电阻更高，从而降低了主EHEMT M4栅极的电压应力。
EHEMT M1和M2以独特的栅漏短路连接方式配置，这种结构有效地建立了一个如下所示负电压反馈回路：漏极/栅极处的增加dVg(短路)被放大 为漏极电流+id的增加(见图3A)。漏极电流的增加增强了负载上的电压下降，从而降低了dVg(如图3A中的“-dVg1”)，这就完成了负反馈。
与图3A相关的分析中可以清楚地看出，当更多的低压EHEMTs串联使用时，+id是叠加的。理想的实施方式是尽可能多地使用低压EHEMTs来稳定电压。但是，低压EHEMTs的数量限制是根据主电源EHEMT的最大Vg设置的。对于基于p-gan制造的氮化镓技术，通常为6V。假设一个共同的阈值门电压(Vt)为1.5-2V，并且考虑到在适当的信号放大模式下，需要高于阈值电压约1V来偏压低压EHEMT，则只能使用两个低压EHEMT。但是，如果电压Vt降低到1V或以下，则可使用3至4个低压EHEMT。
现在描述如何使用氮化镓集成电路技术实现图1中显示的实施例，其中常见的双金属层技术EHEMT布局如图4所示。图4显示了制造工艺的各个层，其中金属1(Metal1)和金属2(Metal2)是装置上方的两个顶部金属层，用于制作电极，并且通孔是金属1和金属2层之间的绝缘层的开口，填充金属以连接金属1和金属2。图5-10、18-21和24-26也是一样的，尽管在图8-10、19和24-26焊盘开孔是顶部保护涂层的开孔，通过其进行电极接触。在这些图中，G、D和S分别表示栅极、漏极和源极。栅极金属可通过两个金属层(金属1和金属2，通过通孔连接)进入。源极和漏极只能通过金属2形成通道。
双金属层技术DHEMT布局如图5所示，其中栅极对电源短路，以便为传导沟道提供稳定的偏压。器件制造是为了获得HEMT的自然D模式。
参考图1，使用从漏极到栅极侧条的Metal2连接是实现电压稳定的EHEMTs M1和M2的最方便的途径，效果如图6所示。需要注意的是，必须小心设置低压DHEMT和低压EHEMT之间的宽度比例，以达到以下所述的6V稳定电压。
对于功率集成电路布局，如何放置相对于主功率晶体管的栅极驱动模块(Gate driver module)至关重要。必须考虑几个因素。首先，栅极驱动模块必须足够靠近主功率晶体管的栅电极，以减少寄生电感。其次，为了降低晶 圆空间成本，该栅极驱动模块必须尽可能地占用较小的面积。第三，栅极驱动模块必须与高压漏极屏蔽，以避免电磁干扰。
如图7所示，该图显示了功率模块集成电路布局的一个实施例，相对于功率模块集成电路的其余部分，栅极驱动模块的位置显示在左上角，后者是栅极条为垂直方向的主氮化镓晶体管M4。为了在矩形模具上为栅极驱动模块提供晶圆区域，将主晶体管分为两个平行EHEMTs的矩形区域，从而留出栅极驱动模块所需尺寸的小矩形区域。虚线A-B将两个平行连接的矩形主晶体管分隔为M4。值得注意的是，栅极驱动模块集成电路靠近两个并联的主晶体管的源极侧。
图8是图7实施例的栅极驱动模块布局的更详细的视图。栅极驱动模块的输出连接到金属层(G-Metal1)上顶部的栅极轨道。连接通过一个通孔和一个EHEMT M2的漏极金属垫，后者是栅极驱动模块的输出点。Gi-pad是栅极驱动模块的输入，位于Metal2层，如Gi-metal2所示，需要将Gi垫放大，以便于设备包装。GI垫与DHEMT M3的漏极相连，但与其他装置电气隔离。
为了线路连接的需求，GI接触垫必须足够大。因此，DHEMT M3采用了独特的设计，如图9所示，这是图8布局的更详细视图。为了使GI的金属垫尽可能大，采用了两种技术。第一部分是拆除metal2闸门侧杆的上部(或闸栅极驱动模块系列部件的布局朝向水平方向时的左侧)，以便为漏极垫让路。第二种是源极和漏极以不对称的方式实现，使得漏极比源极大得多。这样，漏极垫的尺寸可以足够大，以利于引线粘合或金属碰撞。
例如，对于650V应用中的地面网格阵列(LGA)或球网格阵列(BGA)，有必要在大于约2mm的距离处分离漏极板和源极板。因此，在一个实施例中，主晶体管M4的布局使得栅极条平行于器件的较长方向，而源极和漏极位于条的两端。在另一个实施例中，栅极条可以在水平和较长的方向上定位，如图10所示。
为了在模具上为栅极输入模块保留空间，在一个实施例中，主功率晶体管M4使用两个平行矩形晶体管，由水平线A-B分开，如图7-图10中的功 率模块布局实施例所示。在这种实施例中，栅极输入模块位于较大的主晶体管上方。
为实施如上所述的实施例，可对主晶体管使用650V工艺，而对于低压EHEMTs和DHEMT，可使用100V工艺，当然也可使用其他工艺。设计DHEMT的沟道宽度与EHEMT的沟道宽度之比非常重要，以确保实现正确的Vg。例如，在两个EHEMT相同且DHEMT采用与EHEMT相同的高压(LV)技术的实施例中，沟道宽度比EHEMT:DHEMT(微米)应为约350μ：75μ或约4.7:1。按与单位大致相同顺序的常数因子缩放(即改变比例，如2:1、3:1、8:1、9:1等，其中第一个数字乘以系数0.1到9，而第二个数字始终为1)不会改变结果，但会影响栅极输入模块的电阻，从而影响放电/充电电流的强度。
使用APSYS TM软件(Crosslight Software Inc.，温哥华，加拿大；www.crosslight.com)进行模拟，以确认基于图1电路的实施例的操作。在模拟中，考虑了两种尺寸。尺寸1是指EHEMT:DHEMT 350μ：75μ和尺寸2为700μ：150μ的宽度。栅极电压Vg与偏置电压Vgi的结果如图11所示，两种尺寸(尺寸1和尺寸2)的电压降档结果相同。
栅极驱动模块的偏置电流Igi对器件沟道宽度敏感。对于上述沟道宽度，偏置电流Igi如图12所示。集成电路的放电速度和直流功率损耗之间存在着交换：较小的沟道宽度可以降低直流功率损耗，但会减慢主晶体管M4的放电速度。需要注意的是，这里所述的栅极驱动模块的使用会使功率模块(即，栅极驱动模块加上功率晶体管M4(例如，两个并联的主HEMT))表现为具有50-100的电流放大的双极结晶体管(BJT)。
图13显示了两个沟道尺寸的栅极驱动模块的输入/输出脉冲响应。DHEMT的低电阻导致打开/关闭响应干净无拖尾。与预期的一样，更大尺寸的栅极驱动模块使开关速度更快。图14还显示了两个沟道尺寸的功率晶体管输出Vd脉冲响应与栅极驱动器模块输入电压的关系。
图15显示了两个沟道尺寸的栅极驱动模块的直流偏置电流(因此功率损 失)。很明显，在直流功率损耗和栅极延迟之间存在着一种交换。
图16的示意图中显示了另一个实施例，其中M60是具有较大沟道的低压(LV)EHEMT(例如，40V到100V)，它为功率HEMT提供栅极驱动器所需的电流。M10到M40是较小的低压电磁阀，具有相同或类似的沟道尺寸，其连接使栅极与漏极短路。M50是一个DHEMT，它的连接将栅极与源极短路。下面将详细讨论，M10到M50如何作用提供参考电压。
图16实施例的等效电路如图17所示，其中DHEMT M50可被视为可变电阻R，而四个EHEMTs M10至M40可被视为稳压齐纳二极管，将参考电压限制在约7.5V。
图16的实施例还实现了图1实施例在电子速度特性(参见图3B)和图16实施例中DHEMT的可变电阻(即M50)方面的上述优点。
将DHEMT用于M50的好处还在于低场或低电压下的低电阻。高迁移率(图3B中上部插入部分的高初始斜率)使DHEMT迅速进入饱和状态，在饱和状态下充当可变电阻。对于相同的电流，可以改变DHEMT上的电压降，以便DHEMT M50可以接收Vcci的任何多余电压，确保参考电压保持在7.5V，以便可以在要求的Vcc＝6V时钳紧提供给EHEMT源极的电流。
如图1的实施例所示，图16的EHEMTs M10至M40配置成具有栅极漏极短路的独特接触连接分布，有效地建立了如上所述的负电压反馈回路。
在图1的实施例中，当串联使用更多的低压EHEMTs时，+id是累加的。尽管出于电压稳定的目的，需要尽可能多地使用低压EHEMTs，但低压EHEMTs数量的限制根据参考电压设置，在本实施例中，参考电压约为7.5V。假设公共阈值门电压(Vt)约为1.5V，并且假设需要高于阈值电压(VT)约0.3-0.5V。在适当的信号放大模式下，只能使用四个低压EHEMTs。但是，如果电压VT降低到1V或以下，则可使用5至7个低压EHEMTs。
供电电流EHEMT m60的连接方式为负反馈，可用于稳定辅助电源电压Vcc。M60的负反馈工作如下：考虑一个接地和M60电源之间的电源负载。M60中电源电流的增加会增加M60的电源电压，而Vgs会降低。M60的Vgs 降低会增加M60的直流电阻，从而使M60的电源电压升高反向，这就完成了负反馈循环。很明显，负反馈效应与M60的跨导成正比，跨导与M60的沟道宽度/面积成正比。更稳定的VCC需要更大的晶体管尺寸和更高的晶片面积成本。
现在将描述使用氮化镓集成电路技术实现图16的实施例。如上文所述，图4的两个金属层技术EHEMT布局和图5的DHEMT布局(其中栅极对源极短路)可在本实施例中使用。
如图18所示，稳定电压的EHEMTs M10至M40可使用金属2连接从漏极到顶部栅极来实现。需要注意的是，必须仔细设置低压DHEMT和低压EHEMT之间的宽度比，以达到7.5V稳定电压，如下所述。
必须仔细规划调节器的布局。首先，它应该足够小以降低成本。其次，它应该放在整个模块的边缘，而不是在驱动器和主功率晶体管之间。第三，电源插座Vcc应位于顶部，以便为整个驱动电路供电，该驱动电路可包括如图23实施例所示的放大器。
图19显示了矩形块中调节器布局的一个实施例。图中的EHEMTs M10到M40位于下端，而较大的M60位于上端。电源插座是M60的电源，位于模具顶部。需要注意的是，为了使矩形块的X-尺寸恒定，四个EHEMTs M10到M40的条水平或垂直于较大的M60的条，如图20所示。源极和漏极从M10到M40交替排列，使用短的Metal2矩形将一个HEMT的漏极连接到下一个HEMT的源极是方便的。
与其他晶体管相比，DHEMT M50相对较小，如图19的布局实施例和图21的更详细视图所示。在一个实施例中，沟道宽度之比使得DHEMT之宽度约为EHEMTs(例如，M10到M40)宽度的2-20％。如果EHEMTs的沟道宽度不相等但相似，则该比率应以最小的EHEMT为基础。为了确保DHEMT的栅极可以用作整个调节器的公共连接器，而不占用模具上的很多区域，DHEMT条与较大晶体管M60条垂直，如图21的实施例所示。
使用APSYS TM软件对图16的实施例进行了模拟，其集成电路布局如图 19所示。图22A显示了调节器集成电路的模拟电压转移特性，图22B显示了调节器电压参考支路的电流-电压特性。从图22A可以清楚地看出，设计的7.5V是在8V以上的宽电压范围内实现的，从而验证了设计。作为参考电压源，通过M10-M40支路的直流电流较小，因此直流损耗最小。这为M10到M50的尺寸(沟道宽度)设定了上限。针对其中的一个100V低压实施例，每个EHEMT的EHEMT沟道宽度约为400μm。
图23是显示调节器如何与放大器A一起使用的示意图，例如直接耦合场效应管逻辑(DCFL)和缓冲放大器作为主功率晶体管M70的栅极驱动器的辅助电源。根据该实施例，调节器可与主功率晶体管M70整体集成在氮化镓中。需要注意的是，将Vcci调低到所需的6V不可避免地会导致功率损耗，这与输入电压Vcci和通过晶体管M60提供的电流成比例。因此，实施例可以使用较低的系统电压，即10-30V的低端电压另外，参考电压支路M10至M40的设计可用于绘制低直流电流。
图24显示了图23电路的模具布局的一个实施例，包括上述和图19所示的电源集成电路中的调节器。主电源HEMT M70条与调节器的较长方向平行，主电源HEMT条长度的设计为与调节器块的较长侧大致相同。放大器驱动块的设计高度与调节器大致相同(如图24所示)，它夹在主电源HEMT M70和调节器块之间。
图25和26显示了两个实施例的模具布局，包括调节器，如图19所示，但具有更大额定电流的主电源HEMT。如大功率HEMT，由于调节器的尺寸比主功率HEMT小得多，因此使用与图24相同的布置是不具有区域效率的。在图25的实施例中，调节器块相对于主电源HEMT旋转90度，其中栅极指垂直朝向。为了在模具上为调节器和放大器/驱动器块提供区域，主功率晶体管被分成两个平行的EHEMT矩形区域，留下一个所需尺寸的矩形区域。虚线A-B将两个平行连接的矩形主晶体管分开。值得注意的是，低压块位于两个并联的主晶体管的源端附近。
如上所述，对于650V应用中的LGA或BGA包装，必须将漏极垫和源 极垫分开2mm以上的距离。因此，在一个实施例中，主晶体管的布局使得栅极条平行于器件的较长方向，而源极和漏极位于条的两端。在另一个实施例中，栅极条朝向水平和较长的方向，如图26所示。在这种实施例中，对于大电流额定值的LGA设备，为了为低压块(即调节器和放大器/驱动器)留出空间，两个平行矩形功率晶体管由水平线A-B分开，低压块位于较大的主晶体管上方。
对图23的实施例和图24的布局进行了模拟，基于额定值为8A的功率HEMT。
图27A显示了模拟的输入电压脉冲，图27B显示了约5.5V的辅助电源输出Vcc。外部Vcci设置为10V。在本实施例中，电流供应晶体管(M60)的沟道宽度设置为6000μm。预计使用更大的M60沟道WI可以实现更好的电压调节，但是要以增加晶片面积为代价。
图28A和28B分别显示了额定最大电流为8A的主电源EHEMT的模拟栅极驱动电压和栅极电流。这些结果以及图22A和22B中所示的结果,确认调节器达到能够使用广泛的直流电压输入的辅助电源的目标。因此，所述实施例提供一种适于向氮化镓集成电路提供约6V辅助电源的小型压模区电压调节器。输入电压范围足够大，可与所有当前电力系统辅助电源兼容。这些实施例使得在现有的电力系统中实现氮化镓电力设备成为可能。
以上所述的实施例仅为了说明本发明的技术思想及特点，其目的在于使本领域的普通技术人员能够了解本发明的内容并据以实施，本专利的范围并不仅局限于上述具体实施例，即凡依本发明所揭示的精神所作的同等变化或修饰，仍涵盖在本发明的保护范围。

Claims (40)

  1. 一种氮化镓(GaN)功率高电子迁移率晶体管(HEMT)的栅极驱动电路，其特征在于，包括：
    一个接收输入电压的输入点，一个用来输出驱动功率HEMT电压的输出点；
    一个串联电路，包括至少一个氮化镓D模式HEMT(DHEMT)和至少第一和第二个氮化镓E模式HEMTs(EHEMTs)；
    其中：DHEMT的漏极连接到输入点，DHEMT的源极连接到第一EHEMT的漏极和输出点；
    DHEMT的栅极与DHEMT的源极相连；
    第一EHEMT的源极连接到第二EHEMT的漏极；
    第一EHEMT的栅极连接到第一EHEMT的漏极；
    第二EHEMT的源极连接到电路公共端；并且第二EHEMT的栅极连接到第二EHEMT的漏极；
    其中，栅极驱动电路是在氮化镓集成电路(IC)上实现的，或者使用分立的氮化镓器件实现。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，所述栅极驱动电路提供电压降档和过电压保护以驱动氮化镓功率HEMT。
  3. 根据权利要求1所述的栅极驱动电路，其特征在于，其中所述至少一个DHEMT作为可变电阻器工作，并且所述至少第一EHEMT和第二EHEMT作为齐纳二极管工作，所述齐纳二极管将输出电压限制在约6V。
  4. 根据权利要求1所述的栅极驱动电路，其特征在于，其中所述DHEMT、所述至少第一EHEMT和第二EHEMT是低压器件。
  5. 根据权利要求1所述的栅极驱动电路，其特征在于，其中所述DHEMT 至少与所述至少第一EHEMT和第二EHEMT具有不同的沟道长度和/或不同的沟道宽度。
  6. 根据权利要求1所述的栅极驱动电路，其特征在于，其中所述DHEMT至少与所述至少第一EHEMT和第二EHEMT具有相同的沟道长度。
  7. 根据描述权利要求1所述的栅极驱动电路，其特征在于，其中所述DHEMT的沟道宽度至少为所述第一EHEMT和第二EHEMT中最小的沟道宽度的17％到25％。
  8. 根据权利要求1所述的栅极驱动电路，其特征在于，其中至少所述第一EHEMT和第二EHEMT的沟道宽度相同，并且所述DHEMT:EHEMTs的沟道宽度之比约为1:4.7。
  9. 一种氮化镓(GaN)集成电路(IC)电源模块，其特征在于，包括：
    根据权利要求1所述的栅极驱动电路；和功率HEMT；
    其中，栅极驱动模块和功率HEMT整体集成在一个模具中。
  10. 关于权利要求9所述的氮化镓集成电路电源模块，其特征在于，其中：
    所述功率HEMT包括至少并联连接在一起的第一高压HEMT和第二高压HEMT；
    第一高压HEMT小于第二高压HEMT，以使模具的一个区域不被功率HEMT占据；并且
    栅极驱动模块设置在不被功率HEMT占用的模具区域。
  11. 一种用于实现氮化镓功率HEMT的栅极驱动电路的方法，其特征在于，包括：
    提供接收输入电压的输入点以及输出电压以驱动功率HEMT的输出点；
    将至少一个氮化镓DHEMT和至少第一氮化镓EHEMT和第二氮化镓 EHEMT串联在一起；其中：
    DHEMT的漏极连接到输入点，DHEMT的源极连接到第一EHEMT的漏极和输出点；
    DHEMT的栅极与DHEMT的源极相连；
    第一EHEMT的源极连接到第二EHEMT的漏极；
    第一EHEMT的栅极连接到第一EHEMT的漏极；
    第二EHEMT的源极连接到电路公共端；并且
    第二EHEMT的栅极连接到第二EHEMT的漏极；并且在氮化镓集成电路上实现栅极驱动电路。
  12. 根据权利要求11所述的方法，其特征在于，其中所述栅极驱动电路提供电压降档和过压保护以驱动所述氮化镓功率HEMT。
  13. 根据权利要求11所述的方法，其特征在于，包括：
    将所述DHEMT作为可变电阻器工作，以及将所述至少第一EHEMT和第二EHEMT作为齐纳二极管工作，所述齐纳二极管将输出电压限制在约6V。
  14. 如权利要求11所述的方法，其特征在于，其中该DHEMT及该至少第一EHEMT及第二EHEMTs是低压装置。
  15. 根据权利要求11所述的方法，其特征在于，其中所述DHEMT和所述至少第一EHEMT和第二EHEMT具有不同的沟道长度和/或不同的沟道宽度。
  16. 根据权利要求11所述的方法，其特征在于，其中所述DHEMT和所述至少第一EHEMT和第二EHEMT具有相同的沟道长度。
  17. 根据权利要求11所述的方法，其特征在于，其中所述DHEMT的沟道宽度为所述至少第一EHEMT和第二EHEMT中最小的沟道宽度的17％到25％。
  18. 根据权利要求11所述的方法，其特征在于，其中所述至少第一EHEMT和第二EHEMT的沟道宽度相同，并且所述DHEMT:EHEMTs的沟道宽度比约为1:4.7。
  19. 根据权利要求11所述的方法，其特征在于，包括将栅极驱动器与功率HEMT在单个氮化镓模具中整体集成。
  20. 根据权利要求19所述的方法，其特征在于，其中：
    所述功率HEMT使用至少第一高压HEMT和第二高压HEMT并联连接在一起实现；
    其中，第一高压HEMT小于第二高压HEMT以使模具的一个区域不被功率HEMT占据；并且栅极驱动模块设置在不被功率HEMT占用的模具区域。
  21. 一种用于氮化镓(GaN)集成电路(IC)的电压调节器电路，其特征在于，包括：
    接收输入电压的输入点以及用于输出驱动氮化镓集成电路电压的输出点；
    一种串联电路，包括至少一个具有栅极到源极连接的氮化镓D模式HEMT(DHEMT)和至少第一到第四氮化镓E模式HEMT(EHEMT)，每个HEMT具有漏极到栅极连接；
    一个输出EHEMT具有连接到输入点的漏极和连接到输出点的源极；
    其中：
    DHEMT的漏极连接到输入点，DHEMT的源极连接到第一个EHEMT的漏极和输出EHEMT的栅极；
    第一EHEMT的源极连接到第二EHEMT的漏极，
    第二EHEMT的源极连接到第三EHEMT的漏极，
    第三EHEMT的源极连接到第四EHEMT的漏极，
    第四EHEMT的源极连接到电路公共端；
    其中，电压调节器电路在氮化镓集成电路上实现或使用分立的氮化镓器件实现。
  22. 根据权利要求21所述的电压调节器电路，其特征在于，其中所述电压调节器电路提供参考电压输出。
  23. 根据权利要求21所述的电压调节器电路，其特征在于，其中所述电压调节器电路用于驱动低压氮化镓电路。
  24. 根据解释项21所述的电压调节器电路，其特征在于，其中所述至少一个DHEMT作为可变电阻器工作，并且所述至少第一EHEMT到第四个EHEMT作为齐纳二极管工作，所述齐纳二极管将输出电压限制在约6V。
  25. 根据权利要求21所述的电压调节器电路，其特征在于，其中所述DHEMT和所述至少第一EHEMT到第四EHEMT是低压装置。
  26. 如权利要求21所述的电压调节器电路，其特征在于，其中DHEMT及至少第一EHEMT至第四EHEMT具有不同沟道长度和/或不同沟道宽度。
  27. 根据权利要求21所述的电压调节器电路，其中所述DHEMT的沟道宽度约为所述至少第一EHEMT到第四个EHEMT中最小的沟道宽度的3.5％。
  28. 根据权利要求21所述的电压调节器电路，其特征在于，其中所述至少第一EHEMT到第四EHEMT的沟道宽度相同。
  29. 一种氮化镓(GaN)集成电路(IC)电源模块，其特征在于，包括：
    如权利要求1中的电压调节器电路；
    一个放大器；和一个功率HEMT；
    其中电压调节器电路、放大器和功率HEMT整体集成在一个模具中。
  30. 根据权利要求29所述的氮化镓集成电路电源模块，其特征在于，其中：
    所述功率HEMT包括至少第一高压HEMT和第二高压HEMT并联连接在一起；
    第一高压HEMT小于第二高压HEMT才使模具的一个区域不被功率HEMT占据；并且
    电压调节器电路和放大器设置在不被功率HEMT占用的模具区域。
  31. 一种用于实现氮化镓集成电路电压调节器电路的方法，其特征在于，包括：
    提供接收输入电压的输入点以及输出氮化镓集成电路驱动电压的输出点；
    将至少一个氮化镓D-模式HEMT(DHEMT)与栅极到源极连接串联，其中至少一个氮化镓E-模式HEMT(EHEMT)与漏极到栅极连接串联；
    将输出EHEMT的漏极连接到输入点，将输出HEMT的源极连接到输出点；
    其中：
    DHEMT的漏极连接到输入点，DHEMT的源极连接到第一个EHEMT的漏极和输出EHEMT的栅极；
    第一EHEMT的源极连接到第二EHEMT的漏极，
    第二EHEMT的源极连接到第三EHEMT的漏极，
    第三EHEMT的源极连接到第四EHEMT的漏极，
    第四EHEMT的源极连接到电路公共端；
    其中，电压调节器电路是在氮化镓集成电路上实现的，或者是使用分立的氮化镓器件实现的。
  32. 根据权利要求31所述的方法，其特征在于，其中所述电压调节器电路提供参考电压输出。
  33. 根据权利要求31所述的方法，其特征在于，其中所述电压调节器电路用于驱动低压氮化镓电路。
  34. 根据权利要求31所述的方法，其特征在于，其中所述至少一个DHEMT作为可变电阻器工作，并且所述至少第一EHEMT到第四个EHEMT作为齐纳二极管工作，所述齐纳二极管将输出电压限制在约6V。
  35. 根据权利要求31所述的方法，其特征在于，其中该DHEMT及至少第一EHEMT至第四EHEMT是低压装置。
  36. 根据权利要求31所述的方法，其特征在于，其中DHEMT及至少第一EHEMT至第四EHEMT具有不同沟道长度和/或不同沟道宽度。
  37. 根据权利要求31所述的方法，其特征在于，其中所述DHEMT的沟道宽度约为所述至少第一EHEMT到第四个EHEMT中最小的沟道宽度的3.5％。
  38. 根据权利要求31所述的方法，其特征在于，其中所述至少第一EHEMT到第四EHEMT的沟道宽度相同。
  39. 根据权利要求31所述的方法，其特征在于，包括将电压调节器电路与放大器和功率HEMT整体集成；
    其中电压调节器电路、放大器和功率HEMT整体集成在一个模具中。
  40. 根据权利要求39所述的方法，其特征在于，其包括：
    实现至少第一EHEMT和第二高压HEMT并联在一起的功率HEMT；
    其中，第一高压HEMT小于第二高压HEMT，因此模具的一个区域不被功率HEMT占据；并且电压调节器电路和放大器设置在不被功率HEMT占用的模具区域。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012151466A2 (en) * 2011-05-05 2012-11-08 Arctic Sand Technologies, Inc. Dc-dc converter with modular stages
GB2564482B (en) 2017-07-14 2021-02-10 Cambridge Entpr Ltd A power semiconductor device with a double gate structure
US11336279B2 (en) 2017-07-14 2022-05-17 Cambridge Enterprise Limited Power semiconductor device with a series connection of two devices
US11257811B2 (en) 2017-07-14 2022-02-22 Cambridge Enterprise Limited Power semiconductor device with an auxiliary gate structure
US11955478B2 (en) * 2019-05-07 2024-04-09 Cambridge Gan Devices Limited Power semiconductor device with an auxiliary gate structure
US10720913B1 (en) * 2019-05-28 2020-07-21 Infineon Technologies Austria Ag Integrated failsafe pulldown circuit for GaN switch
US10958268B1 (en) 2019-09-04 2021-03-23 Infineon Technologies Austria Ag Transformer-based driver for power switches
US10979032B1 (en) 2020-01-08 2021-04-13 Infineon Technologies Austria Ag Time-programmable failsafe pulldown circuit for GaN switch
US11502651B2 (en) * 2020-03-18 2022-11-15 Smarter Microelectronics (Guang Zhou) Co., Ltd. Overvoltage protection and gain bootstrap circuit of power amplifier
FR3134261A1 (fr) * 2022-03-31 2023-10-06 Wise-Integration Circuit integre comportant un circuit d’adaptation de la tension fournie a la grille d’un transistor de puissance
TWI848435B (zh) * 2022-11-11 2024-07-11 康舒科技股份有限公司 空乏式氮化鎵電晶體同步整流器及具有同步整流器的電源轉換器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681663A (zh) * 2012-09-20 2014-03-26 富士通株式会社 电源电路和电源装置
US9160326B2 (en) * 2012-07-10 2015-10-13 The Hong Kong University Of Science And Technology Gate protected semiconductor devices
CN106464242A (zh) * 2014-05-28 2017-02-22 美国联合碳化硅公司 共源共栅切换电路
CN107924938A (zh) * 2015-06-16 2018-04-17 泰戈尔技术股份有限公司 高性能射频开关

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767946A (en) * 1987-01-12 1988-08-30 Tektronix, Inc. High-speed supply independent level shifter
US6313705B1 (en) * 1999-12-20 2001-11-06 Rf Micro Devices, Inc. Bias network for high efficiency RF linear power amplifier
JP4519659B2 (ja) * 2005-01-06 2010-08-04 ルネサスエレクトロニクス株式会社 バイアス回路
JP2009290490A (ja) * 2008-05-28 2009-12-10 Micronics Japan Co Ltd 増幅回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9160326B2 (en) * 2012-07-10 2015-10-13 The Hong Kong University Of Science And Technology Gate protected semiconductor devices
CN103681663A (zh) * 2012-09-20 2014-03-26 富士通株式会社 电源电路和电源装置
CN106464242A (zh) * 2014-05-28 2017-02-22 美国联合碳化硅公司 共源共栅切换电路
CN107924938A (zh) * 2015-06-16 2018-04-17 泰戈尔技术股份有限公司 高性能射频开关

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