[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2020097987A1 - 显示控制装置以及显示设备 - Google Patents

显示控制装置以及显示设备 Download PDF

Info

Publication number
WO2020097987A1
WO2020097987A1 PCT/CN2018/118006 CN2018118006W WO2020097987A1 WO 2020097987 A1 WO2020097987 A1 WO 2020097987A1 CN 2018118006 W CN2018118006 W CN 2018118006W WO 2020097987 A1 WO2020097987 A1 WO 2020097987A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
data
circuit
display control
frame start
Prior art date
Application number
PCT/CN2018/118006
Other languages
English (en)
French (fr)
Inventor
王明良
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/043,530 priority Critical patent/US11423859B2/en
Publication of WO2020097987A1 publication Critical patent/WO2020097987A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present application relates to the field of display technology, in particular to a display control device and a display device.
  • liquid crystal display devices With the development of display technology, various display devices have enriched people's production and life. Among them, the liquid crystal display technology has been very mature, and is constantly updated and improved. Liquid crystal display devices occupy an absolute market position and are widely used in monitors, computers, televisions, and mobile phone screens.
  • the driving of the display device adopts the AC driving method, that is, the voltage of the first polarity (such as positive polarity) is used to drive in the previous frame, and the second polarity (such as Negative polarity) voltage drive.
  • the first polarity such as positive polarity
  • the second polarity such as Negative polarity
  • a display control device and a display device that improve the display of darker sub-pixels in the first row.
  • a display control device including:
  • the data driver includes a data output circuit configured to output a data signal
  • the timing controller is configured to output a data control signal that controls the signal input of the data driver.
  • the data control signal includes a frame start signal and a normal signal.
  • the frame start signal is located at the beginning of a frame
  • the conventional signal is located after the frame start signal in the same frame;
  • a control circuit that is electrically connected to the timing controller and the data output circuit, and is configured to perform signal input to the data output circuit according to the data control signal; when the data control signal is the frame start signal, The control circuit performs a first current input to the data output circuit according to the data control signal; when the data control signal is the regular signal, the control circuit outputs the data according to the data control signal The circuit performs a second current input, and the first current is greater than the second current.
  • a display control device including:
  • Scan driver set to output scan signal
  • the data driver includes a data output circuit configured to output a data signal
  • the timing controller is configured to output a data control signal that is an input signal of the scan driver and controls the signal input of the data driver;
  • the data control signal includes a frame start signal and a conventional signal, the The frame start signal is located at the beginning of a frame, the regular signal is located after the frame start signal in the same frame, and the level of the frame start signal is higher than the level of the regular signal;
  • the control circuit includes an N-type field effect transistor, a first current source, a P-type field effect transistor, and a second current source;
  • the gate of the N-type field effect transistor is electrically connected to the timing controller and receives the data control signal
  • the source of the N-type field effect transistor is electrically connected to the first current source
  • the N-type field effect is electrically connected to the data output circuit
  • the gate of the P-type field effect transistor is electrically connected to the timing controller and receives the data control signal, the source of the P-type field effect transistor is electrically connected to the second current source, and the P-type field effect The drain of the transistor is electrically connected to the data output circuit;
  • the current output by the first current source is greater than the current output by the second current source.
  • a display device includes a display control device and a display panel
  • the display control device includes:
  • the data driver includes a data output circuit configured to output a data signal
  • the timing controller is configured to output a data control signal that controls the signal input of the data driver.
  • the data control signal includes a frame start signal and a normal signal.
  • the frame start signal is located at the beginning of a frame
  • the conventional signal is located after the frame start signal in the same frame;
  • a control circuit that is electrically connected to the timing controller and the data output circuit, and is configured to perform signal input to the data output circuit according to the data control signal; when the data control signal is the frame start signal, The control circuit performs a first current input to the data output circuit according to the data control signal; when the data control signal is the regular signal, the control circuit outputs the data according to the data control signal The circuit performs a second current input, and the first current is greater than the second current;
  • the display panel includes multiple rows of sub-pixels and multiple data lines, and the data lines are electrically connected to the data output circuit and the sub-pixels.
  • FIG. 1 is a schematic diagram of a display device in an embodiment of this application.
  • FIG. 2 is a partial schematic diagram of a display device in an embodiment of this application.
  • 3 is a partial timing diagram of data signals of an exemplary display device
  • FIG. 4 is a timing diagram of data control signals within a frame in an embodiment of the present application.
  • FIG. 5 is a partial timing diagram of data signals in an embodiment of the present application.
  • the display control device provided by the present application may be, but not limited to, applied to a liquid crystal display device (for example, an LCD computer, an LCD TV, an LCD mobile phone screen, etc.).
  • a liquid crystal display device for example, an LCD computer, an LCD TV, an LCD mobile phone screen, etc.
  • a display device including a display panel 100 and a display control device 200.
  • the display panel 100 includes a plurality of rows of sub-pixels 110 and a plurality of data lines 120.
  • the data lines 120 are electrically connected to the display control device and the sub-pixels 110, and then charge each row of sub-pixels 110.
  • the display panel 100 may include a plurality of sub-pixels 110 of different colors, such as a red sub-pixel 110R, a green sub-pixel 110G, a blue sub-pixel 110B, and the like.
  • a plurality of sub-pixels 110 of different colors may form a display circuit.
  • the sub-pixels 110 of various colors in a display circuit cooperate so that the display circuit can display any desired color.
  • all the sub-pixels 110 of the display panel are sequentially arranged in multiple rows, and the number of sub-pixels 110 in each row is multiple. When the display panel is operating, each row of sub-pixels 110 is turned on row by row.
  • the sub-pixel 110 may include a pixel electrode, a common electrode, and liquid crystal molecules therebetween.
  • the data lines 120 charge the pixel electrodes of each sub-pixel 110 while the sub-pixels 110 of each row are turned on, so that the liquid crystal molecules are deflected to transmit light transparently.
  • the display control device 200 is connected to the data line 120 to provide data signals for charging the data line 120.
  • the display control device 200 specifically includes a data driver 210 and a timing controller 220.
  • the data driver 210 includes a data output circuit 211.
  • the data output circuit 211 is configured to output data signals for the data line 120.
  • the data signal is in the form of alternating current. That is, when the display device is operating, the data output circuit 211 has the opposite polarity of the data signal output to the same data line 120 in the previous frame and the next frame. There will be an idle time between the previous frame and the next frame. During this idle time, the data output circuit 211 does not output the data signal, and the driving trace of the display device (the trace connecting the data output circuit 211 and the data line 120) will maintain the level of the last driving voltage of the previous frame a.
  • the voltage on the driving trace is switched from the level a.
  • the level of the target charging voltage to be switched is the level b having the polarity opposite to the level a.
  • the voltage of level a and the voltage of level b are very different due to the opposite polarities, so that the actual charging voltage level of the first row of sub-pixels 110 that are initially charged is likely to be lower than the target charging voltage level b.
  • the data output circuit 211 charges the sub-pixels 110 in other rows in the same frame, so the polarity of the data signal does not change, so the actual charging voltage level of other traveling can easily reach the target charging voltage . Therefore, the sub-pixels 110 in the first row are darker than those in the other rows.
  • the timing controller 220 may output a data control signal.
  • the data control signal controls the signal input of the data driver 210. That is, the input signal of the data driver 100 is determined by the data control signal.
  • the data control signal includes a frame start signal V S1 .
  • the frame start signal V S1 is located at the beginning of a frame.
  • the data control signal also includes a normal signal V S2 .
  • FIG. 4 is a timing diagram of data control signals within a complete frame.
  • the frame start signal V S1 is located at the beginning of a frame and has a duration of t1.
  • the normal signal V S2 is located after the frame start signal in the same frame and has a duration of t2.
  • the display control device in the embodiment of the present application further includes a control circuit 230.
  • the control circuit 230 is electrically connected to the timing controller 220, and further performs signal input to the data output circuit 211 according to the data control signal.
  • the control circuit 230 is electrically connected to the data output circuit 211, and then performs signal input to the data driver 210, and then outputs a data signal positively related to the input signal received through the data output circuit 211.
  • the control circuit 230 When the data control signal is the frame start signal V S1 , the control circuit 230 performs the first current input to the data output circuit 211 according to the data control signal. When the data control signal is the normal signal V S2 , the control circuit performs a second current input to the data output circuit 211 according to the data control signal.
  • the second current input is the same current input as the exemplary display device. The first current is greater than the second current.
  • the control circuit 230 Since the input signal received by the data output circuit 211 is positively correlated with its output signal, when the data control signal is the frame start signal V S1 , the control circuit 230 performs a large first current input to the data output circuit 211, As a result, the output current of the data output circuit 211 also becomes larger. At the same time, the greater the current output by the data output circuit 211, the faster the charge transfer speed and the faster the switching speed of the output data signal. Therefore, referring to FIG. 5, the first row of sub-pixels 110 that are charged at the beginning of the next frame can easily reach the original target charging voltage level within the same time due to the faster voltage switching speed Achieved a predetermined charging target, thereby improving the phenomenon that the first row of sub-pixels 110 is displayed dark.
  • the control circuit 230 When the data control signal is the normal signal V S2 , the control circuit 230 performs a small second current input to the data output circuit 211.
  • the second current input is the same current input as the exemplary display device, so it can meet the charging requirements of the other rows of sub-pixels 110 other than the first row of sub-pixels 110.
  • the application of the larger first current input and the smaller second current input in conjunction with this application improves the case where the first line of the exemplary display device is insufficiently charged and dark, and reduces the current in time when other lines are charged, Thereby saving energy consumption.
  • the control circuit 230 includes a first circuit 231 and a second circuit 232 connected in parallel.
  • the separate arrangement of the first circuit 231 and the second circuit 232 in the control circuit 230 facilitates different signal input to the data output circuit 211 according to different data control signals (frame start signal V S1 and normal signal V S2 ).
  • the first circuit 231 performs a first current input to the data output circuit 211 according to the data control signal, and the second circuit 232 is turned off.
  • the data control signal is the normal signal V S2
  • the second circuit 232 performs a second current input to the data output circuit 211 according to the data control signal, and the first circuit 231 is turned off.
  • the first circuit 231 is provided to include a first switching device 2311 and a first current source 2312 that are electrically connected to each other.
  • the second circuit 232 includes a second switching device 2321 and a second current source 2322 that are electrically connected to each other.
  • first switching device 2311 is electrically connected to the timing controller 220 and the data output circuit 211.
  • second switching device 2321 is also electrically connected to the timing controller 220 and the data output circuit 211.
  • the first current source 2312 is configured to output a first current
  • the second current source 2322 is configured to output a second current.
  • the first switching device 2311 When the data control signal is the frame start signal V S1 , the first switching device 2311 is turned on, the second switching device 2321 is turned off, and the first current source 2312 performs a first current input to the data output circuit 211.
  • the data control signal is the normal signal V S2
  • the second switching device 2321 is turned on, the first switching device 2311 is turned off, and the second current source 2322 performs a second current input to the data output circuit 211.
  • Both the first switching device 2311 and the second switching device 2321 need to be electrically connected to the three parts. Therefore, it can be provided that both are three-terminal switching devices (such as transistors or switching transistors, etc.). In order to facilitate circuit design, the two can be set to the same type of switching device (the same transistor or the same switching transistor). Of course, the two can also be different types of switching devices.
  • the two may be field effect transistors of two different conductivity types.
  • the first switching device 2311 may be a first type (for example, N-type or P-type) field effect transistor.
  • the second switching device 2321 may be a second type (for example, P-type or N-type) field effect transistor.
  • the present application is not limited to this, and the first switching device 2311 and the second switching device 2321 may also be switching transistors and the like.
  • the gates of the field effect transistors of the first type and the field effect transistors of the second type are electrically connected to the timing controller 220 and receive data control signals.
  • the source of the first type field effect transistor is electrically connected to the first current source 2312, and the source of the second type field effect transistor is electrically connected to the second current source 2322.
  • the drain of the first type field effect transistor and the drain of the second type field effect transistor are electrically connected to the data output circuit 211.
  • Both the first current source 2312 and the second current source 2322 are constant current sources. Therefore, the control circuit can provide a stable current to the data output circuit 211 of the data driver 210, and further stabilize the data signal output by the data output circuit 211.
  • the duration t1 of the frame start signal V S1 is less than the duration t2 of the conventional signal V S2 . Since the frame start signal V S1 determines whether the compensation circuit 232 outputs a compensation signal, the output duration of the required compensation signal is usually close to the duration of one line of scanning signal, which is much shorter than the duration of one frame. Therefore, the setting of t1 less than t2 relatively meets the needs in this regard.
  • the level of the normal signal V S2 is set to be lower than the level of the frame start signal V S1 , which in turn enables the display control device to save more energy when it is working.
  • this application does not limit the duration of the frame start signal V S1 , which may be equal to the charging duration of the first row of sub-pixels 110, may also be less than the charging duration of the first row of sub-pixels 110, or may be greater than the first row The duration of the sub-pixel 110.
  • the duration of the frame start signal V S1 may be equal to the charging duration of the first row of sub-pixels 110, may also be less than the charging duration of the first row of sub-pixels 110, or may be greater than the first row The duration of the sub-pixel 110.
  • the display control device 200 further includes a scan driver 240 configured to output scan signals.
  • the data control signals (frame start signal V S1 and normal signal V S2 ) are the input signals of the scan driver 240.
  • the level of the input signal received by the scan driver 240 at the beginning of a frame is compared with that received at a later time in the same frame
  • the level of the input signal of is high, which satisfies the condition setting of the frame start signal V S1 and the normal signal V S2 described above.
  • the data control signals (frame start signal V S1 and normal signal V S2 ) can be set as the input signal of the scan driver 240, thereby making the input signal of the scan driver 240 of the display control device multi-functional, simplifying the display control device 200
  • the output circuit structure reduces the energy consumption of the display control device.
  • the data control signals may not be input signals of the scan driver 240 but are designed separately, and the present application does not limit this.
  • t1 is the scanning duration of the first row of sub-pixels within one frame
  • t2 is the sum of the scanning duration of the second row of sub-pixels and the sub-pixels of all rows after the second row.
  • t1 is the scan duration of the first row of sub-pixels in one frame, that is, the duration t1 of the high-level frame start signal V S1 is equal to the duration of the scan driver's row of scan signals, that is, equal to the first row of sub-pixels 110 Charging time. Therefore, it can be ensured that the first row of sub-pixels 110 can have a sufficiently fast voltage switching speed during the entire scanning period of the row, and sufficient charging can be achieved. At the same time, high-level signals are not wasted on the sub-pixels 110 of the second row and the second row that have already been fully charged, thereby saving energy consumption.
  • the data output circuit 211 includes an operational amplifier and a data output terminal, the control circuit is electrically connected to the operational amplifier circuit, and the operational amplifier circuit is located between the control circuit and the data output terminal. Therefore, the data output circuit 211 can effectively amplify the input signal received by the operational amplifier to form an amplified data signal for output.
  • control circuit 230 is located in the data driver 210, thereby facilitating signal input to the data output circuit 211 of the data driver 210.
  • the position of the control circuit 230 is not limited thereto, and it may also be located in other positions, for example, in the timing controller or in the scan driver 240 and so on.
  • the display control device 200 includes a scan driver 240, a data driver 210, and a timing controller 220.
  • the scan driver 240 is configured to output scan signals.
  • the data driver 210 includes a data output circuit 211.
  • the data output circuit 211 is configured to output data signals.
  • the timing controller 220 is configured to output data control signals.
  • the data control signal is an input signal of the scan driver 240 and controls the signal input of the data driver 210, thereby achieving multi-functionalization of the data control signal.
  • the data control signal includes a frame start signal V S1 and a normal signal V S2 .
  • the frame start signal V S1 is located at the beginning of a frame, and the normal signal V S2 is located after the frame start signal in the same frame.
  • the level of the frame start signal V S1 is higher than the level of the normal signal V S2 .
  • the display control device also includes a control circuit 230.
  • the control circuit 230 may be located in the data driver 210, and of course, it may be located at another location.
  • the control circuit 230 includes an N-type field effect transistor, a first current source 2312, a P-type field effect transistor, and a second current source 2322.
  • the data control signal is the high-level frame start signal V S1
  • the N-type field effect transistor is turned on, and the P-type field effect transistor is turned off.
  • the data control signal is a normal V S2 with a low level
  • the N-type field effect transistor is turned off and the P-type field effect transistor is turned on.
  • the gate of the N-type field effect transistor is electrically connected to the timing controller 220 and receives a data control signal; the source of the N-type field effect transistor is electrically connected to the first current source 2312; and the drain of the N-type field effect transistor is an electrical data output circuit 211. Therefore, when the data control signal is a high-level frame start signal V S1 , the N-type field effect transistor performs a large current input for the data output circuit 211, thereby speeding up the switching speed of the voltage output by the data output circuit 211, thereby The sub-pixels 110 in the first row are fully charged, and the display phenomenon of the sub-pixels 110 in the first row is improved.
  • the gate of the P-type field effect transistor is electrically connected to the timing controller 220 and receives the data control signal; the source of the P-type field effect transistor is electrically connected to the second current source 2322, and the current output by the first current source 2312 is greater than the second current source 2322 Output current; P-type field effect transistor drain electrical data output circuit 211. Therefore, when the data control signal is the low-level normal signal V S2 , the P-type field effect transistor performs a small current input for the data output circuit 211, thereby saving energy consumption.
  • the control circuit performs signal input to the data driver according to the data control signal.
  • the data control signal is a frame start signal
  • the control circuit makes a large current input to the data output circuit, thereby making the output current of the data output circuit large.
  • the higher the output current the faster the output voltage switching speed. Therefore, when the sub-pixels in the first row are charged, the voltage switching speed is accelerated, and it is easy to reach the original level of the target charging voltage in the same time, which achieves the predetermined charging target and further improves
  • the first row of sub-pixels shows a dark phenomenon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

显示控制装置（200）包括数据驱动器（210）、时序控制器（220）以及控制电路（230）。数据驱动器（210）包括数据输出电路（211），数据输出电路（211）设置为输出数据信号。时序控制器（220）设置为输出数据控制信号，数据控制信号控制数据驱动器（210）的信号输入，数据控制信号包括帧起始信号V S1与常规信号V S2。控制电路（230）电连接时序控制器（220）与数据输出电路（211），设置为根据数据控制信号对数据输出电路（211）进行信号输入。

Description

显示控制装置以及显示设备
本申请要求于2018年11月12日提交中国专利局、申请号为201811338831.4、发明名称为“显示控制装置以及显示设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种显示控制装置以及显示设备。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然的构成现有技术。
随着显示技术的发展，各种显示设备丰富了人们的生产生活。其中，液晶显示技术已经非常成熟，且还在不断的更新改进。液晶显示设备占据绝对的市场地位，广泛应用于显示器、电脑、电视和手机屏等领域。
相关技术中，显示设备驱动为了防止液晶极化，采用了交流驱动的方式，即上一帧采用第一极性(如正极性)的电压驱动，下一帧就会采用第二极性(如负极性)的电压驱动。此时，下一帧的第一行子像素往往会因充电不足，而导致显示偏暗。
申请内容
根据本申请的各种实施例，提供一种改善第一行子像素显示偏暗的显示控制装置以及显示设备。
一种显示控制装置，包括：
数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
时序控制器，设置为输出数据控制信号，所述数据控制信号控制所述数据驱动器的信号输入，所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后；
控制电路，电连接所述时序控制器与所述数据输出电路，设置为根据所述数据控制信号对所述数据输出电路进行信号输入；当所述数据控制信号为所述帧起始信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第一电流输入；当所述数据控制信号为所述常规信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第二电流输入，所述第一电流大于所述第二电流。
一种显示控制装置，包括：
扫描驱动器，设置为输出扫描信号；
数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
时序控制器，设置为输出数据控制信号，所述数据控制信号为所 述扫描驱动器的输入信号并控制所述数据驱动器的信号输入；所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后，所述帧起始信号的电平高于所述常规信号的电平；
控制电路，包括N型场效应晶体管、第一电流源、P型场效应晶体管以及第二电流源；
所述N型场效应晶体管的栅极电连接所述时序控制器并接受所述数据控制信号，所述N型场效应晶体管的源极电连接所述第一电流源，所述N型场效应晶体管的漏极电所述数据输出电路，
所述P型场效应晶体管的栅极电连接所述时序控制器并接受所述数据控制信号，所述P型场效应晶体管的源极电连接所述第二电流源，所述P型场效应晶体管的漏极电所述数据输出电路；
所述第一电流源输出的电流大于所述第二电流源输出的电流。
一种显示设备，包括显示控制装置以及显示面板，
显示控制装置包括：
数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
时序控制器，设置为输出数据控制信号，所述数据控制信号控制所述数据驱动器的信号输入，所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后；
控制电路，电连接所述时序控制器与所述数据输出电路，设置为 根据所述数据控制信号对所述数据输出电路进行信号输入；当所述数据控制信号为所述帧起始信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第一电流输入；当所述数据控制信号为所述常规信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第二电流输入，所述第一电流大于所述第二电流；
显示面板包括多行子像素以及多条数据线，所述数据线电连接所述数据输出电路与所述子像素。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1为本申请的一个实施例中显示设备的示意图；
图2为本申请的一个实施例中显示设备的局部示意图；
图3为示例性显示设备的数据信号的局部时序图；
图4为本申请的一个实施例中的一个帧内的数据控制信号的时序图；
图5为本申请的一个实施例中数据信号的局部时序图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述 的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请提供的显示控制装置，可以但不限于应用于液晶显示设备(例如，液晶电脑、液晶电视、液晶手机屏等等)之中。
参考图1以及图2，在一个实施例中，提供了一种显示设备，包括显示面板100、显示控制装置200。显示面板100包括多行子像素110以及多条数据线120，数据线120电连接显示控制装置与子像素110，进而为各行子像素110进行充电。
具体地，参考图2，显示面板100可以包括多个不同颜色的子像素110，例如红色子像素110R、绿色子像素110G、蓝色子像素110B等。多种不同颜色的子像素110可以形成一个显示电路。一个显示电路内的各种颜色的子像素110配合，使得显示电路可以显示任意所需颜色。同时，显示面板的所有子像素110有序地排列成多行，每行子像素110的数量为多个。显示面板工作时，各行子像素110逐行打开。子像素110可以包括像素电极、公共电极以及二者之间的液晶分子。数据线120在各行子像素110打开的同时为各子像素110的像素电极进行充电，使得液晶分子偏转进而透光显示。
显示控制装置200连接数据线120，进而为数据线120充电提供而数据信号。参考图1，显示控制装置200具体包括数据驱动器210以及时序控制器220。
数据驱动器210包括数据输出电路211。数据输出电路211设置为为数据线120输出数据信号。为了防止液晶极化，数据信号为交流电的形式。即显示设备工作时，数据输出电路211在上一帧与下一帧 对同一数据线120输出的数据信号的极性相反。上一帧与下一帧之间会有一段空闲时间。这段空闲时间内，数据输出电路211不进行数据信号的输出，显示设备的驱动走线(连接数据输出电路211与数据线120的走线)上会维持上一帧最后一个驱动电压的准位a。
如图3所示，示例性显示设备中，数据输出电路211在下一帧对相同的数据线120输出数据信号的时候，驱动走线上的电压从准位a开始切换。假设切换的目标充电电压的准位为与准位a极性相反的准位b。准位a的电压和准位b的电压由于极性相反而差距很大，所以会造成最开始进行充电的第一行子像素110的实际充电电压的准位容易低于目标充电电压的准位b。第一行过后，数据输出电路211对同一帧内的其他行子像素110进行充电时，由于数据信号的极性不变，因此，其他行进的实际充电电压的准位可以容易地达到目标充电电压。因此就会造成第一行子像素110相对其他行子像素110偏暗。
本申请实施例中，时序控制器220可以输出数据控制信号。数据控制信号控制数据驱动器210的信号输入。即，数据驱动器100的输入信号由数据控制信号决定。数据控制信号包括帧起始信号V S1。帧起始信号V S1位于一帧的开始。当时序控制器200发出帧起始信号V S1时，表示新的一帧的开始。数据控制信号还包括常规信号V S2。参考图4，图4为一个完整帧内的数据控制信号时序图。帧起始信号V S1位于一帧的开始，时长为t1。常规信号V S2位于同一帧内的帧起始信号之后，时长为t2。
同时，参考图1，本申请实施例中的显示控制装置还包括控制电 路230。控制电路230电连接时序控制器220，进而根据数据控制信号对数据输出电路211进行信号输入。同时控制电路230电连接数据输出电路211，进而对数据驱动器210进行信号输入，然后通过数据输出电路211再输出与其接受到的输入信号正相关的数据信号。
当数据控制信号为帧起始信号V S1时，控制电路230根据数据控制信号对数据输出电路211进行第一电流输入。当数据控制信号为常规信号V S2时，控制电路根据数据控制信号对数据输出电路211进行第二电流输入。第二电流输入为与示例性显示设备相同的电流输入第一电流大于第二电流。
由于数据输出电路211接受到的输入信号与其输出的信号正相关，因此，当数据控制信号为帧起始信号V S1，控制电路230对数据输出电路211进行较大的第一电流输入时，会使得数据输出电路211的输出电流也变大。而在同一时间内，数据输出电路211输出的电流越大，电荷传输速度就越快，其输出的数据信号的切换速度就越快。因此，参考图5，在下一帧的开始阶段进行充电的第一行子像素110，由于电压的切换速度加快，在同样的时间内便容易更快地到达原本的目标充电电压的准位的位置，实现了既定的充电目标，进而改善第一行子像素110显示偏暗的现象。
当数据控制信号为常规信号V S2时，控制电路230对数据输出电路211进行较小的第二电流输入。第二电流输入为与示例性显示设备相同的电流输入，因此其可以满足第一行子像素110以外的其他行子像素110的充电需求。本申请较大的第一电流输入与较小的第二电流 输入配合使用，即改善了示例性显示设备的第一行充电不足而偏暗的情况，又在其他行充电时及时减小电流，从而节省能耗。
参考图1，在一个实施例中，控制电路230包括并联的第一电路231与第二电路232。控制电路230中第一电路231与第二电路232的分开设置，便于根据不同的数据控制信号(帧起始信号V S1与常规信号V S2)对数据输出电路211进行不同的信号输入。
具体地，当数据控制信号为帧起始信号V S1时，第一电路231根据数据控制信号对数据输出电路211进行第一电流输入，第二电路232关闭。当数据控制信号为常规信号V S2时，第二电路232根据数据控制信号对数据输出电路211进行第二电流输入，第一电路231关闭。
在一个实施例中，为了便于实现上述第一电路231与第二电路232的功能，设置第一电路231包括相互电连接的第一开关器件2311以及第一电流源2312。第二电路232包括相互电连接的第二开关器件2321以及第二电流源2322。
并且，第一开关器件2311电连接时序控制器220与数据输出电路211。同时，第二开关器件2321也电连接时序控制器220与数据输出电路211。第一电流源2312设置为输出第一电流，第二电流源2322设置为输出第二电流。
当数据控制信号为帧起始信号V S1时，第一开关器件2311打开，第二开关器件2321关闭，第一电流源2312对数据输出电路211进行第一电流输入。当数据控制信号为常规信号V S2时，第二开关器件2321 打开，第一开关器件2311关闭，第二电流源2322对数据输出电路211进行第二电流输入。
第一开关器件2311以及第二开关器件2321均需与三部分电连接，因此，可以设置二者均为三端开关器件(例如晶体管或开关三极管等)。为了便于电路设计，可以设置二者为相同种类的开关器件(同为晶体管或同为开关三极管等)。当然，二者也可为不同种类的开关器件。
具体地，二者可以分别为两种不同导电类型的场效应晶体管。第一开关器件2311可以为第一类型(例如N型或P型)场效应晶体管。第二开关器件2321可以为第二类型(例如P型或N型)场效应晶体管。当然本申请不以此为限，第一开关器件2311以及第二开关器件2321还可以为开关三极管等。
第一类型场效应晶体管的栅极以及第二类型场效应晶体管的栅极电连接时序控制器220并接受数据控制信号。第一类型场效应晶体管的源极电连接第一电流源2312，第二类型场效应晶体管源极电连接第二电流源2322。第一类型场效应晶体管的漏极以及第二类型场效应晶体管的漏极电连接数据输出电路211。
第一电流源2312与第二电流源2322均为恒流源，因此，使得控制电路可以为数据驱动器210的数据输出电路211提供稳定的电流，进一步使得数据输出电路211输出的数据信号稳定。
在一个实施例中，参考图4，帧起始信号V S1的时长t1小于常规信号V S2的时长t2。由于帧起始信号V S1决定补偿电路232是否输出 补偿信号，而所需补偿信号的输出时长通常与一行扫描信号的时长相接近，其远小于一帧时长。因此t1小于t2的设置相对更满足在此方面的需求。
此时，设置常规信号V S2的电平低于帧起始信号V S1的电平，进而使得显示控制装置在进行工作时，更加节省能耗。
当然，本申请对帧起始信号V S1的时长并不做限制，其可以等于第一行子像素110的充电时长，也可以小于第一行子像素110的充电时长，也可以大于第一行子像素110的时长。可以设置帧起始信号V S1的时长小于所述常规信号V S2的时长，也可以设置帧起始信号V S1的时长大于所述常规信号V S2的时长。常规信号V S2的电平也可以高于帧起始信号V S1的电平。
在一个实施例中，显示控制装置200还包括设置为输出扫描信号的扫描驱动器240。数据控制信号(帧起始信号V S1以及常规信号V S2)为扫描驱动器240的输入信号，扫描驱动器240在一帧的开始时接收到的输入信号的电平，相较同一帧后续时候接收到的输入信号的电平高，满足上述帧起始信号V S1以及常规信号V S2的条件设置。因此，可以设置数据控制信号(帧起始信号V S1以及常规信号V S2)为扫描驱动器240的输入信号，进而使得显示控制装置的扫描驱动器240的输入信号多功能化，简化显示控制装置200的输出电路结构，降低显示控制装置的能耗。
当然，本申请实施例中，数据控制信号(帧起始信号V S1以及常规信号V S2)也可不为扫描驱动器240的输入信号，而另行设计，本 申请对此并无限制。
在一个实施例中，继续参考图4，t1为第一行子像素在一帧内的扫描时长，t2为第二行子像素以及第二行以后的所有行的子像素的扫描时长之和。t1为第一行子像素在一帧内的扫描时长，即将高电平的帧起始信号V S1的时长t1与扫描驱动器的一行扫描信号的时长相等，亦即等于第一行子像素110的充电时长。因此，可以保证第一行子像素110在该行整个扫描期间均能够具有足够快的电压切换速度，而实现充足的充电。同时，又不在原有已经具有充足充电的的第二行以及第二行以后的子像素110上浪费高电平信号，从而节省能耗。
在一个实施例中，数据输出电路211包括运算放大器与数据输出端，控制电路电连接运算放大器电路，运算放大器电路位于控制电路与数据输出端之间。因此，数据输出电路211可以通过运算放大器将其接收到的输入信号有效放大，形成放大后的数据信号进行输出。
在一个实施例中，控制电路230位于数据驱动器210内，进而便于对数据驱动器210的数据输出电路211进行信号输入。当然，本申请实施例中，控制电路230的位置并不以此为限制，其也可位于其他位置，例如位于时序控制器内或位于扫描驱动器240内等等。
在一个实施例中，如图1所示，显示控制装置200包括扫描驱动器240、数据驱动器210、时序控制器220。扫描驱动器240设置为输出扫描信号。数据驱动器210包括数据输出电路211。数据输出电路211设置为输出数据信号。时序控制器220设置为输出数据控制信号。数据控制信号为扫描驱动器240的输入信号并控制数据驱动器 210的信号输入，进而实现数据控制信号的多功能化。数据控制信号包括帧起始信号V S1与常规信号V S2。帧起始信号V S1位于一帧的开始，常规信号V S2位于同一帧内的帧起始信号之后。帧起始信号V S1的电平高于常规信号V S2的电平。
显示控制装置还包括控制电路230。控制电路230可以数据驱动器210内，当然，也可位于其他位置。控制电路230包括N型场效应晶体管、第一电流源2312、P型场效应晶体管以及第二电流源2322。当数据控制信号为高电平的帧起始信号V S1时，N型场效应晶体管打开，P型场效应晶体管关闭。而当数据控制信号为低电平的常规V S2时，N型场效应晶体管关闭，P型场效应晶体管打开。
N型场效应晶体管的栅极电连接时序控制器220并接受数据控制信号；N型场效应晶体管的源极电连接第一电流源2312；N型场效应晶体管的漏极电数据输出电路211。因此，当数据控制信号为高电平的帧起始信号V S1时，N型场效应晶体管为数据输出电路211进行较大的电流输入，进而加快数据输出电路211输出的电压的切换速度，从而使得第一行子像素110充电充分，而改善第一行子像素110显示偏暗现象。
P型场效应晶体管的栅极电连接时序控制器220并接受数据控制信号；P型场效应晶体管的源极电连接第二电流源2322，第一电流源2312输出的电流大于第二电流源2322输出的电流；P型场效应晶体管的漏极电数据输出电路211。因此，当数据控制信号为低电平的常规信号V S2时，P型场效应晶体管为数据输出电路211进行较小的电 流输入，从而节省能耗。
综上所述，本申请提供的显示控制装置，控制电路根据数据控制信号对数据驱动器的进行信号输入。当数据控制信号为帧起始信号时，控制电路对数据输出电路进行较大的电流输入，进而使得数据输出电路的输出电流电流变大。而输出电流越大，输出电压的切换速度就越快。因此，在第一行子像素进行充电时，由于电压的切换速度加快，在同样的时间内便容易更快地到达原本的目标充电电压的准位的位置，实现了既定的充电目标，进而改善第一行子像素显示偏暗的现象。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种显示控制装置，包括：
    数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
    时序控制器，设置为输出数据控制信号，所述数据控制信号控制所述数据驱动器的信号输入，所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后；
    控制电路，电连接所述时序控制器与所述数据输出电路，设置为根据所述数据控制信号对所述数据输出电路进行信号输入；当所述数据控制信号为所述帧起始信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第一电流输入；当所述数据控制信号为所述常规信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第二电流输入，所述第一电流大于所述第二电流。
  2. 根据权利要求1所述的显示控制装置，其中，
    所述控制电路包括包括并联的第一电路与第二电路；
    当所述数据控制信号为所述帧起始信号时，所述第一电路根据所述数据控制信号对所述数据输出电路进行第一电流输入，所述第二电路关闭；
    当所述数据控制信号为所述常规信号时，所述第二电路根据所述数据控制信号对所述数据输出电路进行第二电流输入，所述第一电路关闭。
  3. 根据权利要求2所述的显示控制装置，其中，
    所述第一电路包括相互电连接的第一开关器件以及第一电流源，所述第二电路包括相互电连接的第二开关器件以及第二电流源；
    所述第一开关器件电连接所述时序控制器与所述数据输出电路；并且，所述第二开关器件电连接所述时序控制器与所述数据输出电路；
    所述第一电流源设置为输出所述第一电流，所述第二电流源设置为输出所述第二电流；
    当所述数据控制信号为所述帧起始信号时，所述第一开关器件打开，所述第二开关器件关闭，所述第一电流源对所述数据输出电路进行第一电流输入；当所述数据控制信号为所述常规信号时，所述第二开关器件打开，所述第一开关器件关闭，所述第二电流源对所述数据输出电路进行第二电流输入。
  4. 根据权利要求3所述的显示控制装置，其中，所述第一开关器件以及所述第二开关器件均为三端开关器件。
  5. 根据权利要求3所述的显示控制装置，其中，所述第一开关器件以及所述第二开关器件为相同种类的开关器件。
  6. 根据权利要求5所述的显示控制装置，其中，所述第一开关器件以及所述第二开关器件分别为两种不同导电类型的场效应晶体管。
  7. 根据权利要求6所述的显示控制装置，其中，所述第一开关器件为N型场效应晶体管，所述第二开关器件为P型场效应晶体管。
  8. 根据权利要求6所述的显示控制装置，其中，所述第一开关器 件为P型场效应晶体管，所述第二开关器件为N型场效应晶体管。
  9. 根据权利要求1所述的显示控制装置，其中，所述帧起始信号的时长小于所述常规信号的时长。
  10. 根据权利要求9所述的显示控制装置，其中，所述常规信号的电平低于所述帧起始信号的电平。
  11. 根据权利要求10所述的显示控制装置，其中，所述显示控制装置还包括设置为输出扫描信号的扫描驱动器，所述数据控制信号为所述扫描驱动器的输入信号。
  12. 根据权利要求11所述的显示控制装置，其中，所述帧起始信号的时长与所述扫描驱动器的一行扫描信号的时长相等。
  13. 根据权利要求1所述的显示控制装置，其中，所述常规信号的电平高于所述帧起始信号的电平。
  14. 根据权利要求1所述的显示控制装置，其中，所述帧起始信号的时长大于所述常规信号的时长。
  15. 根据权利要求1所述的显示控制装置，其中，所述数据输出电路包括运算放大器与数据输出端，所述控制电路电连接所述运算放大器，所述运算放大器位于所述控制电路与所述数据输出端之间。
  16. 根据权利要求1所述的显示控制装置，其中，所述控制电路位于所述数据驱动器内。
  17. 根据权利要求1所述的显示控制装置，其中，所述控制电路位于所述时序控制器内。
  18. 根据权利要求1所述的显示控制装置，其中，所述显示控制 装置还包括设置为输出扫描信号的扫描驱动器，所述控制电路位于所述扫描驱动器内。
  19. 一种显示控制装置，包括：
    扫描驱动器，设置为输出扫描信号；
    数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
    时序控制器，设置为输出数据控制信号，所述数据控制信号为所述扫描驱动器的输入信号并控制所述数据驱动器的信号输入；所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后，所述帧起始信号的电平高于所述常规信号的电平；
    控制电路，包括N型场效应晶体管、第一电流源、P型场效应晶体管以及第二电流源；
    所述N型场效应晶体管的栅极电连接所述时序控制器并接受所述数据控制信号，所述N型场效应晶体管的源极电连接所述第一电流源，所述N型场效应晶体管的漏极电所述数据输出电路，
    所述P型场效应晶体管的栅极电连接所述时序控制器并接受所述数据控制信号，所述P型场效应晶体管的源极电连接所述第二电流源，所述P型场效应晶体管的漏极电所述数据输出电路；
    所述第一电流源输出的电流大于所述第二电流源输出的电流。
  20. 一种显示设备，包括显示控制装置以及显示面板，
    显示控制装置包括：
    数据驱动器，包括数据输出电路，所述数据输出电路设置为输出数据信号；
    时序控制器，设置为输出数据控制信号，所述数据控制信号控制所述数据驱动器的信号输入，所述数据控制信号包括帧起始信号与常规信号，所述帧起始信号位于一帧的开始，所述常规信号位于同一帧内的所述帧起始信号之后；
    控制电路，电连接所述时序控制器与所述数据输出电路，设置为根据所述数据控制信号对所述数据输出电路进行信号输入；当所述数据控制信号为所述帧起始信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第一电流输入；当所述数据控制信号为所述常规信号时，所述控制电路根据所述数据控制信号对所述数据输出电路进行第二电流输入，所述第一电流大于所述第二电流；
    显示面板包括多行子像素以及多条数据线，所述数据线电连接所述数据输出电路与所述子像素。
PCT/CN2018/118006 2018-11-12 2018-11-28 显示控制装置以及显示设备 WO2020097987A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/043,530 US11423859B2 (en) 2018-11-12 2018-11-28 Display control apparatus and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811338831.4 2018-11-12
CN201811338831.4A CN109243397B (zh) 2018-11-12 2018-11-12 显示控制装置以及显示设备

Publications (1)

Publication Number Publication Date
WO2020097987A1 true WO2020097987A1 (zh) 2020-05-22

Family

ID=65078203

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/118006 WO2020097987A1 (zh) 2018-11-12 2018-11-28 显示控制装置以及显示设备

Country Status (3)

Country Link
US (1) US11423859B2 (zh)
CN (1) CN109243397B (zh)
WO (1) WO2020097987A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285517A (zh) * 2018-11-12 2019-01-29 惠科股份有限公司 显示控制装置以及显示面板
CN109697949A (zh) 2019-01-29 2019-04-30 合肥京东方显示技术有限公司 显示装置及其显示控制方法和显示控制装置
CN117116196B (zh) * 2023-09-07 2024-07-19 重庆惠科金渝光电科技有限公司 显示补偿方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103854620A (zh) * 2012-12-04 2014-06-11 乐金显示有限公司 液晶显示装置及其驱动方法
CN107978263A (zh) * 2016-10-25 2018-05-01 三星显示有限公司 显示装置及其驱动方法
CN108305590A (zh) * 2017-01-12 2018-07-20 三星显示有限公司 液晶显示设备
CN108694909A (zh) * 2017-04-11 2018-10-23 三星显示有限公司 有机发光显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW552573B (en) 2001-08-21 2003-09-11 Samsung Electronics Co Ltd Liquid crystal display and driving method thereof
KR100502912B1 (ko) * 2003-04-01 2005-07-21 삼성에스디아이 주식회사 발광 표시 장치 및 그 표시 패널과 구동 방법
TWI278815B (en) * 2003-08-20 2007-04-11 Hannstar Display Corp Liquid crystal display panel
JP3888350B2 (ja) * 2003-12-10 2007-02-28 セイコーエプソン株式会社 演算増幅器及びこれを用いた駆動回路
TWI227801B (en) * 2004-02-17 2005-02-11 Vastview Tech Inc Method and device of a liquid crystal display overdrive
JP2006072211A (ja) * 2004-09-06 2006-03-16 Casio Comput Co Ltd 液晶表示装置及び液晶表示装置の駆動方法
JP2007072162A (ja) * 2005-09-07 2007-03-22 Mitsubishi Electric Corp 表示装置
KR101287477B1 (ko) * 2007-05-01 2013-07-19 엘지디스플레이 주식회사 액정표시장치
JP4890614B2 (ja) 2007-06-12 2012-03-07 シャープ株式会社 液晶表示装置、液晶表示装置の駆動方法、およびテレビジョン受像機
US8344722B2 (en) * 2010-05-17 2013-01-01 Crest Semiconductors, Inc. Electric current measurement
CN102024438B (zh) * 2010-12-24 2012-10-17 北京京东方光电科技有限公司 液晶显示器源极驱动装置和驱动方法
CN104503632B (zh) * 2015-01-26 2018-01-26 京东方科技集团股份有限公司 缓冲单元、触控驱动电路、显示装置及其驱动方法
CN104952407B (zh) * 2015-06-25 2018-01-12 南京中电熊猫液晶显示科技有限公司 一种液晶面板的源极驱动器及其驱动方法
US10726769B2 (en) * 2015-08-20 2020-07-28 Mitsubishi Electric Corporation LED display device and drive device
CN105761690B (zh) 2016-05-04 2018-08-14 深圳市华星光电技术有限公司 显示面板的驱动方法及包括其的显示装置
CN107742502B (zh) * 2017-11-30 2019-10-15 武汉天马微电子有限公司 一种显示面板、显示方法及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103854620A (zh) * 2012-12-04 2014-06-11 乐金显示有限公司 液晶显示装置及其驱动方法
CN107978263A (zh) * 2016-10-25 2018-05-01 三星显示有限公司 显示装置及其驱动方法
CN108305590A (zh) * 2017-01-12 2018-07-20 三星显示有限公司 液晶显示设备
CN108694909A (zh) * 2017-04-11 2018-10-23 三星显示有限公司 有机发光显示装置

Also Published As

Publication number Publication date
CN109243397A (zh) 2019-01-18
US20210110784A1 (en) 2021-04-15
CN109243397B (zh) 2021-03-19
US11423859B2 (en) 2022-08-23

Similar Documents

Publication Publication Date Title
US10134772B2 (en) Array substrate, display panel and display apparatus
US9105247B2 (en) Display device, display device driving method and source driving circuit
CN110060650B (zh) 多路复用型液晶显示驱动电路
CN103198804B (zh) 一种液晶显示装置及其驱动方法
CN108231031B (zh) 显示面板及其驱动方法、显示装置
US8928703B2 (en) Pixel structure
US11380714B2 (en) Array substrate, display panel and display device
US20160247426A1 (en) Display panel, pixel structure and driving method thereof
WO2020097987A1 (zh) 显示控制装置以及显示设备
CN108333841B (zh) 显示面板、显示装置及其驱动方法
JP2003228336A (ja) 平面表示装置
WO2020113594A1 (zh) 驱动装置以及显示设备
WO2021023201A1 (zh) 像素阵列、阵列基板及显示装置
US10535321B2 (en) Display panel, display device and driving method of display panel
WO2021184912A1 (zh) 数据驱动器及其控制方法、显示装置
US20200160768A1 (en) Source driving circuit and display panel
WO2020097986A1 (zh) 显示控制装置以及显示设备
WO2016061916A1 (zh) 液晶显示面板及其驱动结构和驱动方法
US20200152150A1 (en) Drive circuit of display panel and methods thereof and display device
CN106328064B (zh) 一种扫描驱动电路
CN106205526B (zh) 液晶显示面板驱动方法、驱动装置及液晶显示装置
US11276363B2 (en) Display driving control circuit, display panel and driving control method
CN214226480U (zh) 一种提高显示屏驱动电流的电路
CN112419992B (zh) 显示面板及其驱动方法、显示装置
WO2018171061A1 (zh) 驱动电路及液晶显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18940317

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 01.09.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18940317

Country of ref document: EP

Kind code of ref document: A1