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WO2018063748A1 - Anneau de protection de composant électronique - Google Patents

Anneau de protection de composant électronique Download PDF

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Publication number
WO2018063748A1
WO2018063748A1 PCT/US2017/049996 US2017049996W WO2018063748A1 WO 2018063748 A1 WO2018063748 A1 WO 2018063748A1 US 2017049996 W US2017049996 W US 2017049996W WO 2018063748 A1 WO2018063748 A1 WO 2018063748A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
barrier
electronic component
semiconductor material
guard ring
Prior art date
Application number
PCT/US2017/049996
Other languages
English (en)
Inventor
Hongbin Zhu
Minsoo Lee
Gordon A. Haller
Philip J. Ireland
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201780053824.7A priority Critical patent/CN109791915B/zh
Publication of WO2018063748A1 publication Critical patent/WO2018063748A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Definitions

  • Embodiments described herein relate generally to protection of electronic components, and more particularly to guard rings formed in semiconductor material about electronic components.
  • guard ring also known as a “seal ring,” typically formed of a metal band, is often located around the periphery of each chip as part of the fabrication of the IC dice prior to dice singulation via laser dicing, sawing, or combinations of these.
  • guard rings can provide structural reinforcement and stop undesirable cracks, moisture and mobile ionic contaminants from entering active circuitry regions of the chips and affecting operational reliability.
  • FIG. 1 illustrates a schematic representation of an electronic component in accordance with an example
  • FIG. 2 illustrates a detailed view of a guard ring of the electronic component of FIG. 1 ;
  • FIG. 3 illustrates a detailed view of a guard ring of an electronic
  • FIG. 4 illustrates a detailed view of a guard ring of an electronic
  • FIG. 5 illustrates a detailed view of a guard ring of an electronic
  • FIG. 6 illustrates a schematic representation of an electronic component in accordance with an example
  • FIG. 7 illustrates a side cross-sectional view of a trench for making a guard ring of the electronic component of FIG. 6;
  • FIG. 8 illustrates a detailed view of a trench for making a guard ring of an electronic component in accordance with an example
  • FIG. 9 illustrates a side view of trenches for making a guard ring of an electronic component in accordance with an example
  • FIG. 10 is a schematic illustration of a side view of an electronic device in accordance with an example.
  • FIG. 1 1 is a schematic illustration of an exemplary computing system.
  • Coupled is defined as directly or indirectly connected in an electrical or nonelectrical manner. Objects described herein as being “adjacent to” each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used.
  • comparative terms such as “increased,” “decreased,” “better,” “worse,” “higher,” “lower,” “enhanced,” “maximized,” and “minimized,” and the like refer to a property of a device, component, or activity that is measurably different from other comparable devices, components, or activities, or from different iterations or embodiments of the same device, properties in the known state of the art.
  • a data region that has an "increased" risk of corruption can refer to a region of a memory device, which is more likely to have write errors to it than other regions in the same memory device. A number of factors can cause such increased risk, including location, fabrication process, number of program pulses applied to the region, etc.
  • the term “substantially” refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result.
  • an object that is “substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed.
  • the exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained.
  • the use of “substantially” is equally applicable when used in a negative connotation to refer to the complete or near complete lack of an action, characteristic, property, state, structure, item, or result.
  • compositions that is "substantially free of” particles would either completely lack particles, or so nearly completely lack particles that the effect would be the same as if it completely lacked particles.
  • a composition that is "substantially free of” an ingredient or element may still actually contain such item as long as there is no measurable effect thereof.
  • Some electronic components include materials and structures (e.g., layers of conductive material) that can build up electrical charges and arc during formation of a trench for the construction of a guard ring. Such arcing can be detrimental to electronic components.
  • an electronic component guard ring in which the guard ring structure is such that build-up of electrical charges and arcing is minimized during construction while still providing the desired functions of a guard ring.
  • electrical charge is dissipated through connecting bridges of material to minimize arcing potential.
  • an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component.
  • the guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier.
  • Associated systems and methods are also disclosed.
  • the electronic component 100 can include a semiconductor material 102 and a guard ring 101 .
  • electronic circuitry 103 will be associated with the semiconductor material 102.
  • the semiconductor material 102 can be configured as a substrate.
  • the guard ring 101 can be incorporated for a variety of purposes, such as to provide mechanical benefits to the electronic component 100 and/or to provide a contamination barrier to protect the circuitry 103.
  • the guard ring 101 can be configured to prevent crack propagation (e.g., from die-sawing stress) and/or prevent contaminants from entering the electronic circuits 103 of the electronic component 100 (e.g., moisture, ion diffusion, etc.).
  • FIG. 2 illustrates a detail view of a portion 104 of the electronic component 100 of FIG. 1.
  • the guard ring 101 can include a barrier formed in the semiconductor material 102, which can be disposed about or encompassing a perimeter of the electronic component 100, as illustrated.
  • the guard ring 101 can include multiple barriers 1 10a, 1 10b.
  • the barriers 1 10a, 1 10b can be spaced from one another by any suitable distance 120 to form multiple rows of barriers.
  • the barriers 1 10a, 1 10b can be made of any suitable material, such as tungsten, aluminum, copper, silicon, titanium, titanium nitride, ruthenium, cobalt, tantalum, tantalum nitride, etc.
  • the barrier can have barrier portions oriented end to end.
  • the barrier 1 10a can have barrier portions 1 1 1 a, 1 12a oriented end to end
  • the barrier 1 10b can have barrier portions 1 1 1 1 b, 1 12b oriented end to end.
  • the guard ring 101 can also include an opening in the barrier between the barrier portions.
  • the barrier portions 1 1 1 a, 1 12a can be separated from one another by a gap 121 a to form an opening 122a between the barrier portions 1 1 1 a, 1 12a.
  • the barrier portions 1 1 1 1 b, 1 12b can be separated from one another by a gap 121 b to form an opening 122b between the barrier portions 1 1 1 b, 1 12b.
  • the opening 122a can extend between an outer side 123a and an inner side 124a (e.g., opposite sides) of the barrier 1 10a, such that a portion of the semiconductor material 102 extends between the outer and inner sides 123a, 124a of the barrier 1 10a.
  • the opening 122b can extend between an outer side 123b and an inner side 124b (e.g., opposite sides) of the barrier 1 10b, such that a portion of the semiconductor material 102 extends between the outer and inner sides 123b, 124b of the barrier 1 10b.
  • the guard ring 101 can still provide mechanical benefits and serve as a contamination barrier.
  • the openings 122a, 122b can be staggered or laterally offset from one another to prevent crack propagation and provide a tortuous or long path for contaminants to pass through the barriers 1 10a, 1 10b.
  • the barriers 1 10a, 1 10b can include any suitable number of barrier portions with openings in the barriers between adjacent barrier portions.
  • each of the barriers 1 10a, 1 10b can include three or more barrier portions disposed about the perimeter of the semiconductor material 102.
  • Each of the barriers 1 10a, 1 10b includes four such barrier portions as shown in FIG. 1 .
  • FIG. 3 illustrates a detail view of a portion of an electronic component guard ring 201 in accordance with an example of the present disclosure.
  • the guard ring 201 includes multiple barriers 210a, 210b spaced from one another.
  • the barrier 210a includes barrier portions 21 1 a, 21 1 b oriented end to end and separated by a gap to form an opening 222a in the barrier 210a.
  • the barrier 210b is continuous and devoid of an opening.
  • the barrier 210b does not include individual and distinct barrier portions but is, instead, one solid, continuous structure.
  • the solid, continuous barrier 210b can be an innermost barrier in a multiple barrier arrangement or configuration or the outer most barrier.
  • a guard ring in accordance with the present technology can include any suitable number of barriers or rows of barriers, such as three or more barriers. Two examples of multiple barrier configurations are illustrated in FIGS. 4 and 5.
  • FIG. 4 illustrates a detail view of a portion of an electronic component guard ring 301 in accordance with another example of the present disclosure.
  • the guard ring 301 includes four barriers 310a-d, with each barrier having multiple barrier portions oriented end to end and separated by gaps that form openings through the barriers.
  • FIG. 5 illustrates a detail view of a portion of an electronic component guard ring 401 in accordance with another example of the present disclosure.
  • the guard ring 401 includes four barriers 410a-d, with three of the barriers 410a-c having multiple barrier portions oriented end to end and separated by gaps that form openings through the barriers.
  • the barrier 41 Od is continuous and devoid of an opening.
  • the solid, continuous barrier 41 Ob can be an innermost barrier in a multiple barrier arrangement or configuration.
  • a multiple barrier arrangement or configuration can include only a single (i.e., no more than one) solid, continuous barrier and any suitable number of barriers with openings (e.g., three or more barriers with openings).
  • a guard ring as disclosed herein will be introduced in the context of a typical guard ring in a semiconductor material, a top view of which is shown in FIG. 6.
  • a typical guard ring is represented as only a single, continuous barrier.
  • Such a barrier is formed in a trench 530 in a semiconductor material 502, which is illustrated in cross section in FIG. 7.
  • the semiconductor material 502 includes a conductive material 540 and a dielectric material 541 , which can be arranged in alternating conductive and dielectric layers, such as in a NAND flash memory component (e.g., conductive layers forming word lines in a 3D NAND device).
  • Conductive layers can include any suitable conductive material, such as polycrystalline silicon, which can be conductively doped (e.g., to an N+ type conductivity).
  • Dielectric layers can include any suitable dielectric material, such as an oxide (e.g., silicon oxide), an oxynitride (e.g., silicon oxynitride), etc.
  • the trench 530 can be formed by any suitable process or technique, such as a dry etch process.
  • the trench 530 can effectively separate two portions of the semiconductor material 502 (e.g., an inner portion 542 and an outer portion 543), with portions of the conductive layers 540 in the outer portion 543 of the semiconductor material 502 that can become isolated (e.g., suspended by dielectric) by the formation of the trench 530.
  • a dry etch process to form the trench 530 can include plasma, which involves electrons that can charge the conductive layers 540.
  • the process to form the trench 530 can effectively form a capacitor with differential charge densities (e.g., charge per area) in the conductive layers 540 of the inner and outer portions 542, 543 of the semiconductor material 502. Utilizing a deep, long dry etch process to form the trench 530 can cause greater charge to build up in the conductive layers 540. As a result of the differential charge densities of the different portions of
  • Such charge build-up in the conductive layers 540 can be mitigated by leaving a "jumper” or bridge 544 of semiconductor material between or connecting the inner and outer portions 542, 543 of the semiconductor material 502, as illustrated in FIG. 8.
  • the trench 530 can be "broken" by the bridge 544, which can connect the relatively small portions of the conductive layers 540 in the outer portion 543 of the semiconductor material 502 to the relatively large portions of the conductive layers 540 in the inner portion 542 of the semiconductor material 502.
  • Such localized connections or bridges of semiconductor material can allow the charge to spread into a greater area, thus reducing the capacitive effect (i.e., reduce the charge per area) and the voltage across the trench 530, which can therefore reduce the likelihood of arcing.
  • the bridge 544 can be of any suitable dimension to facilitate the dissipation of electron charge from the outer portion 543 of the semiconductor material into the inner portion 542. Forming the trench 530 such that the semiconductor material 502 is continuous via the bridge 544 (i.e., continuous conductive layers 540) results in an opening or gap in a barrier subsequently formed in the trench. Thus, the bridge 544 can define the opening or gap in a barrier of a guard ring.
  • a method for minimizing arcing when making an electronic component can include forming a trench portion 531 of the trench 530 in the semiconductor material 502, and forming a trench portion 532 of the trench 530 in the semiconductor material 502.
  • the trench portion 531 and the trench portion 532 can be oriented end to end and separated from one another by a gap (i.e., the bridge 544) such that a portion of the semiconductor material 502 extends between a side 533 and a side 534 (e.g., opposite sides) of the trench 530.
  • a trench can include at least three trench portions separated by gaps or bridges.
  • a trench can include four or more breaks (i.e., bridges) in about 30 mm of linear distance in order to ensure adequate charge dissipation.
  • the result of such measures to minimize arcing can provide an electronic component precursor that can include the semiconductor material 502, and the trench 530 having the trench portions 531 , 532 formed in the
  • a method for making an electronic component guard ring can include disposing a barrier material in the trench 530 to form a barrier portion in the trench portion 531 and a barrier portion in the trench portion 532 to block ion diffusion and crack propagation in the electronic component.
  • the gap i.e., the bridge 544) can form an opening in the barrier between the barrier portions.
  • the barrier material can be disposed in the trench by any suitable process or technique, such as a deposition process.
  • a single barrier configuration with a gap or opening formed by the bridge 544 may effectively dissipate built-up electrical charge in the conductive layers 540, such a configuration may be inadequate for providing the desired functions of a guard ring, such as preventing crack propagation and providing a contamination barrier.
  • multiple barrier configurations can be utilized, such as those illustrated in FIGS. 1 -5.
  • FIG. 9 illustrates a cross-section of a semiconductor material 602 and trenches 630a, 630b in a two-barrier configuration as in FIGS. 1 -3.
  • the formation of trenches to create multiple barriers or rows of barriers can potentially isolate multiple portions of conductive layers 640.
  • the trenches 630a, 630b can isolate outer portions 643, 644 from one another and the larger inner semiconductor material portion 642.
  • trenches that form multiple barriers can have bridges to connect semiconductor material portions that would otherwise be isolated.
  • the result is the formation of openings in barriers (e.g., openings 122a, 122b in barriers 1 10a, 1 10b of FIG. 2).
  • one or more trenches can be continuous with no bridge interrupting the trench (i.e., devoid of a gap or bridge interrupting the trench).
  • the trench formed to create the barrier 210b of FIG. 3 is continuous with no interruptions.
  • Such a trench and barrier configuration can be utilized when built-up charge can be adequately dissipated by bridges or connections through one or more other trenches, such as a bridge forming the opening 222a in the barrier 210a.
  • a continuous barrier can provide enhanced protection capabilities over a divided or discontinuous barrier.
  • the greater the number of semiconductor material portions interconnected by bridges the greater the ability to dissipate built-up charge due to the increased area of interconnected
  • a continuous, unbroken trench may be an innermost or outermost trench separating or isolating an inner semiconductor material portion from multiple outer semiconductor material portions.
  • the outer semiconductor material portions can be connected to one another via a bridge in one or more outer trenches to accommodate the charge build-up in the combined areas of the outer semiconductor material portions, as in FIGS. 3 and 5.
  • a continuous, unbroken trench may be located anywhere (e.g., in a middle region) among multiple rows of trenches separating or isolating semiconductor material portions from one another, provided that connected semiconductor portions can accommodate the charge build-up in the combined areas of the grouped semiconductor material portions.
  • some embodiments can include multiple continuous, unbroken trenches (e.g., an innermost trench, a middle trench, and/or an outermost trench in any combination) among rows of trenches in multiple semiconductor material portions.
  • FIG. 10 is a schematic representation of an electronic device 705 in accordance with an example of the present disclosure.
  • the electronic device can include a device substrate 750 and an electronic component 700 as disclosed herein operably coupled to the device substrate 750.
  • the electronic component can comprise a memory component, such as a solid state computer memory component (e.g., a NAND flash device).
  • the device 705 can include any suitable electronic component 751 , such as a CPU, a GPU, a memory controller, a video decoder, an audio decoder, a video encoder, a camera processor, system memory, and/or a modem.
  • FIG. 1 1 illustrates an example computing system 806.
  • the computing system 806 can include an electronic component 800 as disclosed herein, coupled to a motherboard 860.
  • the computing system 806 can also include a processor 861 , a memory device 862, a radio 863, a heat sink 864, a port 865, a slot, or any other suitable device or component, which can be operably coupled to the motherboard 860.
  • the computing system 806 can comprise any type of computing system, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable device, a server, etc.
  • Other embodiments need not include all of the features specified in FIG. 1 1 , and may include alternative features not specified in FIG. 1 1 .
  • an electronic component guard ring comprising a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component, and an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier.
  • the first barrier portion and the second barrier portion are separated from one another by a gap to form the opening.
  • the barrier comprises at least three barrier portions and the opening comprises a plurality of openings in the barrier between adjacent barrier portions.
  • the barrier comprises a plurality of barriers spaced from one another on at least one of the first side and the second side.
  • the plurality of barriers comprises at least three barriers.
  • an electronic component guard ring comprises a second barrier spaced from the first barrier on the first side or the second side, wherein the second barrier is continuous and devoid of an opening.
  • the first barrier comprises a plurality of barriers spaced from one another on at least one of the first side and the second side.
  • the second barrier is an innermost barrier.
  • the barrier is disposed about a perimeter of the electronic component.
  • the barrier comprises tungsten.
  • an electronic component precursor comprising a semiconductor material forming a portion of an electronic
  • first and second trench portions are oriented end to end and separated from one another by a gap such that a portion of the semiconductor material extends between a first side and a second side of the trench.
  • the trench comprises at least three trench portions separated by gaps between adjacent trench portions.
  • the trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • the plurality of trenches comprises at least three trenches.
  • an electronic component precursor comprises a second trench spaced from the first trench on the first side or the second side, wherein the second trench is continuous and devoid of a gap.
  • the first trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • the second trench is an innermost trench.
  • the trench is disposed about a perimeter of the electronic component.
  • the semiconductor material comprises polycrystalline silicon.
  • the semiconductor material comprises a plurality of polycrystalline silicon layers.
  • an electronic component precursor comprises a plurality of oxide layers alternatingly arranged with the plurality of polycrystalline silicon layers.
  • an electronic component comprising a semiconductor material, a barrier formed in the semiconductor material, the barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in the electronic component, and an opening in the barrier between the first and second barrier portions such that a portion of the semiconductor material extends between a first side and a second side of the barrier.
  • the first barrier portion and the second barrier portion are separated from one another by a gap to form the opening.
  • the barrier comprises at least three barrier portions and the opening comprises a plurality of openings in the barrier between adjacent barrier portions.
  • the barrier comprises a plurality of barriers spaced from one another on at least one of the first side and the second side.
  • the plurality of barriers comprises at least three barriers.
  • an electronic component comprises a second barrier spaced from the first barrier on the first side or the second side, wherein the second barrier is continuous and devoid of an opening.
  • the first barrier comprises a plurality of barriers spaced from one another on at least one of the first side and the second side.
  • the second barrier is an innermost barrier.
  • the barrier is disposed about a perimeter of the electronic component.
  • the barrier comprises tungsten.
  • the semiconductor material comprises polycrystalline silicon.
  • the semiconductor material comprises a plurality of polycrystalline silicon layers.
  • an electronic component comprises a plurality of oxide layers alternatingly arranged with the plurality of polycrystalline silicon layers.
  • an electronic device comprising a semiconductor material, an electronic component operably coupled to the semiconductor material, the electronic component comprises a semiconductor material, a barrier formed in the semiconductor material, the barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in the electronic component, and an opening in the barrier between the first and second barrier portions such that a portion of the semiconductor material extends between a first side and a second side of the barrier.
  • the electronic component comprises a memory component.
  • an electronic device comprises a CPU, a GPU, a memory controller, a video decoder, an audio decoder, a video encoder, a camera processor, system memory, a modem, or a combination thereof.
  • a computing system comprising a motherboard, and an electronic device component operably coupled to the motherboard, the electronic component comprises a semiconductor material, a barrier formed in the semiconductor material, the barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in the electronic component, and an opening in the barrier between the first and second barrier portions such that a portion of the
  • semiconductor material extends between a first side and a second side of the barrier.
  • the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a wearable device, a server, an integrated automotive computing system (automated driver assistance system) or a combination thereof.
  • the computing system further comprises a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof operably coupled to the motherboard.
  • a method for making an electronic component guard ring comprising forming a trench in a semiconductor material of an electronic component, the trench having a first trench portion and a second trench portion oriented end to end and separated from one another by a gap such that a portion of the semiconductor material extends between a first side and a second side of the trench, and disposing a barrier material in the trench to form a first barrier portion and a second barrier portion in the first trench portion and the second trench portion, respectively, to block ion diffusion and crack propagation in the electronic component, wherein the gap forms an opening in the barrier between the first and second barrier portions.
  • forming a trench comprises a dry etching process.
  • disposing a barrier material in the trench comprises a deposition process.
  • forming the trench comprises forming at least three trench portions with gaps in the trench between adjacent trench portions.
  • the trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • a method for making an electronic component guard ring comprises a second trench spaced from the first trench on the first side or the second side, wherein the second trench is continuous and devoid of a gap.
  • the first trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • the plurality of trenches comprises at least three trenches.
  • the second trench is an innermost trench.
  • the trench is disposed about a perimeter of the electronic component.
  • the barrier material comprises tungsten.
  • the semiconductor material comprises polycrystalline silicon.
  • the semiconductor material comprises a plurality of polycrystalline silicon layers.
  • the plurality of polycrystalline silicon layers are alternatingly arranged with a plurality of oxide layers.
  • a method for minimizing arcing when making an electronic component comprising forming a first trench portion of a trench in a semiconductor material of an electronic component, and forming a second trench portion of the trench in the semiconductor material, wherein the first trench portion and the second trench portion are oriented end to end and separated from one another by a gap such that a portion of the semiconductor material extends between a first side and a second side of the trench.
  • forming the first and second trench portions comprises a dry etching process.
  • a method for minimizing arcing when making an electronic component comprises forming at least three trench portions of the trench with gaps in the trench between adjacent trench portions.
  • the trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • the plurality of trenches comprises at least three trenches.
  • a method for minimizing arcing when making an electronic component comprises a second trench spaced from the first trench on the first side or the second side, wherein the second trench is continuous and devoid of a gap.
  • the first trench comprises a plurality of trenches spaced from one another on at least one of the first side and the second side.
  • the second trench is an innermost trench.
  • the trench is disposed about a perimeter of the electronic component.
  • the semiconductor material comprises polycrystalline silicon.
  • the semiconductor material comprises a plurality of polycrystalline silicon layers.
  • the plurality of polycrystalline silicon layers are
  • Circuitry used in electronic components or devices (e.g. a die) of an electronic device can include hardware, firmware, program code, executable code, computer instructions, and/or software.
  • Electronic components and devices can include a non-transitory computer readable storage medium which can be a computer readable storage medium that does not include signal.
  • the computing devices recited herein may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
  • Volatile and non-volatile memory and/or storage elements may be a RAM, EPROM, flash drive, optical drive, magnetic hard drive, solid state drive, or other medium for storing electronic data.
  • Node and wireless devices may also include a
  • transceiver module a counter module, a processing module, and/or a clock module or timer module.
  • One or more programs that may implement or utilize any techniques described herein may use an application programming interface (API), reusable controls, and the like. Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.
  • API application programming interface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une technologie d'anneau de protection. Dans un exemple, un anneau de protection de composant électronique peut comprendre une barrière ayant une première partie barrière et une seconde partie barrière orientée bout à bout pour bloquer la diffusion d'ions et la propagation de fissures dans un composant électronique. L'anneau de protection peut également comprendre une ouverture dans la barrière entre les première et seconde parties barrières s'étendant entre un premier côté et un second côté de la barrière. L'invention concerne également des systèmes et des procédés associés.
PCT/US2017/049996 2016-10-01 2017-09-04 Anneau de protection de composant électronique WO2018063748A1 (fr)

Priority Applications (1)

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CN201780053824.7A CN109791915B (zh) 2016-10-01 2017-09-04 电子部件保护环

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US15/283,327 US10504859B2 (en) 2016-10-01 2016-10-01 Electronic component guard ring
US15/283,327 2016-10-01

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WO2018063748A1 true WO2018063748A1 (fr) 2018-04-05

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TWI845672B (zh) * 2020-05-08 2024-06-21 聯華電子股份有限公司 封裝環結構
KR20220028539A (ko) * 2020-08-28 2022-03-08 에스케이하이닉스 주식회사 반도체 장치

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US11018097B2 (en) 2021-05-25
US20180096955A1 (en) 2018-04-05
CN109791915A (zh) 2019-05-21
CN109791915B (zh) 2024-04-30
US10504859B2 (en) 2019-12-10

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