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WO2015178296A1 - 電力用半導体装置 - Google Patents

電力用半導体装置 Download PDF

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Publication number
WO2015178296A1
WO2015178296A1 PCT/JP2015/063993 JP2015063993W WO2015178296A1 WO 2015178296 A1 WO2015178296 A1 WO 2015178296A1 JP 2015063993 W JP2015063993 W JP 2015063993W WO 2015178296 A1 WO2015178296 A1 WO 2015178296A1
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WO
WIPO (PCT)
Prior art keywords
power semiconductor
lead terminal
semiconductor device
ceramic substrate
semiconductor element
Prior art date
Application number
PCT/JP2015/063993
Other languages
English (en)
French (fr)
Inventor
藤野　純司
三紀夫 石原
雅芳 新飼
啓行 原田
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US15/124,489 priority Critical patent/US10658284B2/en
Priority to JP2016521067A priority patent/JP6316412B2/ja
Priority to CN201580013957.2A priority patent/CN106104779B/zh
Priority to DE112015002348.8T priority patent/DE112015002348T5/de
Publication of WO2015178296A1 publication Critical patent/WO2015178296A1/ja

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Definitions

  • the present invention relates to a power semiconductor device, and more particularly to a configuration using a lead terminal for electrical connection with a main electrode of a power semiconductor element.
  • Power semiconductor devices are spreading in all kinds of products from industrial equipment to home appliances and information terminals, and power semiconductor devices mounted on home appliances have high productivity and high reliability that can be used in various types as well as being smaller and lighter. Desired.
  • the package form be applicable to a silicon carbide (SiC) semiconductor that is likely to become the mainstream in the future because of its high operating temperature and excellent efficiency.
  • a ceramic substrate with excellent thermal conductivity is often used as an insulating substrate in order to handle a high voltage and a large current and generate a large amount of heat and efficiently exhaust heat. Further, with the increase in the density of the power semiconductor element described above, a technique of directly soldering the copper electrode plate to the main electrode of the power semiconductor element is being used in order to form a circuit with a high current density.
  • the sealing body is configured so that materials with different physical properties are properly used depending on the region, such as sealing the periphery of the joint between the copper electrode plate and the semiconductor element with a flexible urethane resin and then sealing the whole with an epoxy resin. Attempts have been made to reduce stress and the like (for example, see Patent Document 1).
  • JP 2006-351737 paragraphs 0020 to 0027, FIG. 1
  • the present invention has been made to solve the above-described problems, and an object thereof is to obtain a highly reliable power semiconductor device corresponding to a large current.
  • the power semiconductor device of the present invention includes a circuit board, a power semiconductor element having an electrode formed on one surface and the other surface bonded to the circuit substrate, one end side bonded to the electrode, and the other end electrically connected to the outside.
  • An inclined surface is formed so as to move away from the circuit board toward the portion.
  • the power semiconductor device of the present invention since the inclined surface away from the circuit board is formed at the end portion of the lead terminal, the stress concentration on the boundary portion with the end portion is suppressed, and the reliability corresponding to the large current is achieved. A high power semiconductor device can be obtained.
  • 2A and 2B are a plan view and a cross-sectional view for explaining the configuration of the power semiconductor device according to the first embodiment of the present invention. It is sectional drawing for every process for demonstrating the manufacturing method of the semiconductor device for electric power concerning Embodiment 1 of this invention. It is a fragmentary sectional view showing the displacement of the portion near the end of each lead terminal of a conventional example and an example for explaining the operation effect in the power semiconductor device according to the first exemplary embodiment of the present invention. It is a fragmentary sectional view of the end of a lead terminal for explaining the composition of the power semiconductor device concerning the modification of Embodiment 1 of the present invention. It is sectional drawing for demonstrating the structure of the semiconductor device for electric power concerning the modification of Embodiment 1 of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device for electric power concerning Embodiment 2 of this invention.
  • FIG. FIGS. 1 to 3 are diagrams for explaining the configuration of the power semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.
  • FIG. 1 (a) shows the sealing resin from the power semiconductor device.
  • FIG. 1B is a cross-sectional view corresponding to the line AA in FIG. 1A.
  • FIG. 2 is a cross-sectional view for each step corresponding to FIG. 1B for explaining the method of manufacturing the power semiconductor device, and
  • FIG. It is a fragmentary sectional view which shows the displacement with respect to the power semiconductor element of the edge part of a lead terminal at the time.
  • FIG. 4 is a partial cross-sectional view of the end portion of the lead terminal for explaining a configuration in which the shape of the end portion of the lead terminal is changed as a first modification.
  • FIG. 5 is a cross-sectional view for explaining a configuration in which the form of the sealing body is changed as a second modified example, and corresponds to the AA line in FIG.
  • the feature of the power semiconductor device according to the first embodiment is the shape of the end of the lead terminal joined to the main electrode of the element.
  • a power semiconductor element 3 (simply referred to as “element”) is formed by solder 4 on a conductive layer 2a of a ceramic substrate 2 as a circuit board. Yes) is die-bonded (joined).
  • the ceramic substrate 2 has copper conductive layers 2a and 2b each having a thickness of 0.4 mm formed on both sides of a ceramic base 2i made of aluminum nitride (AlN) having a size of 40 mm ⁇ 25 mm ⁇ thickness 0.635 mm.
  • the power semiconductor element 3 is an element using SiC which is a wide band gap semiconductor material.
  • an IGBT (Insulated Gate Bipolar Transistor) 3S having a rectangular plate shape with a thickness of 0.25 mm and a 15 mm square is used.
  • a diode 3R having a rectangular plate shape with a thickness of 0.25 mm and 15 mm ⁇ 15 mm was used.
  • one end of the lead terminal 62 which is a feature of the present invention, is joined to the main electrodes (3a, 3e) on the front side including the emitter electrode 3e of the IGBT 3S.
  • a lead terminal 61 made of a copper plate having a width of 8 mm and a thickness of 0.7 mm is joined by solder 4 to the conductive layer 2a including the collector electrode 3c of the IGBT 3S to which the electrodes on the back side of each element are joined. .
  • the ceramic substrate 2 uses a silicone adhesive 9 so as to fill a gap between the ceramic substrate 2i portion inside a case 8 made of PPS (Poly Phenylene Sulfide) resin of 48 mm ⁇ 28 mm ⁇ height 12 mm. The positioning is fixed.
  • the lead terminal 61, the lead terminal 62, and the signal terminal 52 are each formed by insert molding in the case 8, and the width exposed from the upper part of the case 8 of the lead terminal 61 and the lead terminal 62 (upper left side in the figure).
  • the 10 mm terminal portions 61j and 62j are screw terminals.
  • one end (width: 1.5 mm) of the signal terminal 52 is electrically connected inside the case 8 by a gate electrode 3g which is a control electrode of the IGBT 3S and a bonding wire 51 (aluminum: ⁇ 0.15 mm). From the upper part (upper right side in the figure), the other end of the pin shape is exposed.
  • the lead terminal 61 and the lead terminal 62 form a main current circuit 6 including the power semiconductor element 3 and an external circuit.
  • the gate electrode 3g (1 mm ⁇ 2 mm) of the IGBT 3S has an external signal circuit 5 formed by a signal terminal 52 and a bonding wire 51.
  • the inside of the case 8 is filled with resin (sealing body 7) by direct potting, and is heat-cured and insulated and sealed.
  • the linear expansion coefficient of the sealing body 7 is adjusted so as to be an intermediate value between the linear expansion coefficient of the lead terminal 62 and the linear expansion coefficient of the ceramic substrate 2.
  • the lead terminal 62 which is a feature of the power semiconductor device 1 according to the first embodiment, has an inclined surface 62t that moves away from the ceramic substrate 2 and the power semiconductor element 3 as it proceeds to the end 62e in the longitudinal direction. Is provided.
  • the inclined surface 62t has a bent portion 62b (a portion 2b in front of the end portion 62e (on the opposite side of the terminal portion 62j) from the joined portion with respect to the flat portion 62f joined to the power semiconductor element 3 of the lead terminal 62. It is formed by providing a flip-up angle of 45 degrees).
  • the end portion 62e of the portion sealed by the sealing body 7 inside the case 8 is directed toward the end portion 62e. It inclines so that it may leave
  • the case 8 in which the lead terminal 61, the lead terminal 62, and the signal terminal 52 are integrated is formed by a mold insert.
  • the power semiconductor elements 3 are joined to the predetermined positions on the circuit surface (conductive layer 2 a side) of the ceramic substrate 2 by the solder 4.
  • the ceramic substrate 2 on which the power semiconductor element 3 is mounted is inserted from the lower side (lower side in the drawing) of the case 8 described above.
  • the inserted ceramic substrate 2 is fixed to the case 8 using an adhesive 9.
  • the gap between the ceramic base 2 i and the case 8 is filled with the adhesive 9, so that the case 8 and the ceramic substrate 2 form a container with the ceramic substrate 2 as a bottom and an open top.
  • the lead terminal 61 is opposed to the conductive layer 2a with an interval of 2 mm, and the lead terminal 62 (flat portion 62f) is predetermined with respect to the main electrodes 3a and 3e of the power semiconductor element 3. Opposite with a gap. And between each, the solder material which is not shown in figure is installed.
  • each of the lead terminal 61 and the conductive layer 2a, the lead terminal 62, and the power semiconductor element 3 The main electrodes 3a and 3e are joined by solder 4. Further, the end of the signal terminal 52 exposed in the case 8 is electrically connected to the control electrode of the IGBT 3S such as a temperature sensor electrode including the gate electrode 3g by the bonding wire 51.
  • the ceramic substrate 2 has copper conductor layers 2a and 2b formed on both sides of an AlN ceramic substrate 2i, and the linear expansion coefficient of the entire substrate is about 10 ppm / K, whereas a copper lead terminal
  • the linear expansion coefficient of 62 is 16 ppm / K.
  • an inclined surface 62t is formed by the bent portion 62b, so that the lead terminal 62 and the element (in the first embodiment, IGBT 3S) The gap becomes wider toward the end 62e. Therefore, the resin thickness of the sealing body 7 interposed between the lead terminal 62 and the element gradually increases toward the end 62e.
  • the present inventors have carried out a number of heat cycle tests on various samples of power semiconductor devices using combinations of ceramic substrates and lead electrodes.
  • the results were analyzed, it was found that in many samples, the end portion of the lead terminal to be joined to the main electrode in the sealed body was the starting point of destruction.
  • the lead terminal that electrically connects the external circuit and the main electrode of the power semiconductor element basically extends so as to run longitudinally in the circuit surface. It was found that the stress due to strain was concentrated and became the starting point of fracture.
  • the inclined surface 62t is formed at the end 62e, the distance from the element gradually increases toward the end 62e. That is, as it goes to the end 62e, the thickness of the sealing body 7 interposed between objects having different linear expansion coefficients increases, and the bending strength also increases. On the other hand, when the process proceeds further than the end 62e, the lead terminal 62 is interrupted, and the thickness of the sealing body 7 becomes the thickness.
  • the thickness of the sealing body does not change toward the end portion and is constant, but in this case as well, if the process proceeds further than the end portion 62e, the sealing body It becomes the thickness of the body 7 body.
  • the thickness of the sealing body 7 changes in a step shape at the portion where the terminal is interrupted.
  • the portion where the thickness changes along the longitudinal direction is only one point of the end portion 62e.
  • the thickness (and bending strength) also changes in the portion sandwiched between the lead terminals 62, and the portion where the thickness changes has a length including the end portion 62e ( It is dispersed on the inclined surface 62t). Therefore, it is possible to alleviate the concentration of stress applied to the sealing body 7 at the boundary portion with the end portion 62e, thereby extending the life.
  • FIG. 3 four partial sectional views of the vicinity of the end portion of the lead terminal are arranged vertically and horizontally, and a conventional example is shown on the left side and an embodiment of the present invention is shown on the right side.
  • the upper part shows the state at normal temperature, that is, the state at the stop
  • the lower part shows the state at the high temperature, that is, the state at the start.
  • broken lines passing through the upper and lower stages respectively indicate the position Pe of the end 62e of the conventional lead terminal 62C at normal temperature and the position Pe of the end 62e of the lead terminal 62 according to the embodiment.
  • the first intersection point from the broken line position Pe toward the power semiconductor element 3 is a position Pp on the main surface 3p of the element, which is directly below the end portion at normal temperature.
  • the thermal stress is based on the position Pe (on the end in the figure) of the lead terminal 62 (or 62C) facing the element at normal temperature and the position Pp on the main surface 3p of the element immediately below at a high temperature. It is considered to be proportional to the magnitude of the angle Ae between the line connecting the position Pe and the position Pp and the line perpendicular to the main surface 3p. Therefore, as the inclined surface 62t is formed as in the embodiment, the angle Ae is reduced by increasing the distance toward the end 62e, and the distortion is reduced. That is, the stress applied to the boundary portion with the end portion 62e of the sealing body 7 is smaller than that in the related art.
  • the bent portion 62b that bends the plate material is provided as a method of forming the inclined surface 62t that increases the distance from the element toward the end portion 62e, but is not limited thereto.
  • the inclined surface 62t may be formed by changing the thickness of the end 62e portion like a corner cut. Also in this case, the concentration of stress and starting point generation can be relaxed and the life can be extended.
  • the direct potting resin for forming the sealing body 7 can have the same effect even if it is of a type that is poured and cured at room temperature.
  • the diode 3R and the IGBT 3S have a one-to-one module configuration of “1 in 1”, but even two pairs of “2 in 1” and six pairs of “6 in 1” serve as lead terminals. The same effect can be obtained by arranging the signal terminal on the metal plate.
  • IGBT3S Metal Oxide Semiconductor Field Effect Transistor
  • SBD Schottky Barrier Diode
  • the number of elements is not limited to two, and may be more or one.
  • the same effect can be obtained by using a copper wire, an aluminum-coated copper wire, or a gold wire. Further, the same effect can be obtained by using a ribbon bond or a bus bar that ultrasonically bonds a metal plate.
  • the sealing body 7M may be formed by transfer molding using a mold (not shown) without using a case (transfer mold package).
  • the circuit board (ceramic substrate 2) and the electrodes (for example, 3a and 3e) are formed on one surface, and the other surface is formed on the circuit board.
  • the power semiconductor element 3 is sealed together with the joined power semiconductor element 3, one end side joined to the electrode and the other end side electrically connected to the outside, and the part joined to the electrode of the lead terminal 62.
  • An end face 62t on one end side of the lead terminal 62 (strictly speaking, an inclined surface 62t that moves away from the circuit board as the face facing the circuit board moves toward the end 62e). Is formed.
  • a portion where the thickness (and bending strength) of the portion sandwiched between the lead terminals 62 of the sealing body 7 changes is dispersed in a range (inclined surface 62t) having a length including the end portion 62e. Therefore, the concentration of stress applied to the sealing body 7 on the boundary portion with the end 62e is alleviated.
  • the angle Ae is reduced by increasing the interval, the strain is reduced, and the stress applied to the boundary portion with the end 62e of the sealing body 7 is smaller than that in the related art. As a result, even when the lead terminal 62 corresponding to a large current is used, the life can be extended.
  • the bent portion 62b is provided in the vicinity of the end portion 62e, the inclined surface 62t can be easily formed.
  • the inclined surface 62t can be easily formed even if, for example, a corner cut portion is provided so that the thickness decreases toward the end portion 62e.
  • FIG. 6 is a cross-sectional view corresponding to the line AA of FIG. 1A used in the first embodiment for explaining the configuration of the power semiconductor device according to the second embodiment of the present invention. is there.
  • the configuration other than the lead terminal is the same as that described in the first embodiment including the modification, the description thereof is omitted.
  • the same components as those described in the first embodiment are denoted by the same reference numerals, and a detailed description of overlapping portions is omitted.
  • the power semiconductor element 3 is die-bonded (joined) to the conductive layer 2 a of the ceramic substrate 2, which is a circuit board, by solder 4. .
  • the ceramic substrate 2 was formed by forming 0.4 mm thick copper conductive layers 2 a and 2 b on both sides of a 40 mm ⁇ 25 mm ⁇ 0.635 mm thick aluminum nitride ceramic substrate 2 i.
  • the power semiconductor element 3 is an element using SiC which is a wide band gap semiconductor material.
  • an IGBT (Insulated Gate Bipolar Transistor) 3S having a rectangular plate shape with a thickness of 0.25 mm and a 15 mm square is used.
  • a diode 3R having a rectangular plate shape with a thickness of 0.25 mm and 15 mm ⁇ 15 mm was used.
  • one end of the lead terminal 62 which is a feature of the present invention, is joined to the main electrodes (3a, 3e) on the front side including the emitter electrode 3e of the IGBT 3S.
  • a lead terminal 61 made of a copper plate having a width of 8 mm and a thickness of 0.7 mm is joined by solder 4 to the conductive layer 2a including the collector electrode 3c of the IGBT 3S to which the electrodes on the back side of each element are joined. .
  • the ceramic substrate 2 uses a silicone adhesive 9 so as to fill a gap between the ceramic substrate 2i portion inside a case 8 made of PPS (Poly Phenylene Sulfide) resin of 48 mm ⁇ 28 mm ⁇ height 12 mm. The positioning is fixed.
  • the lead terminal 61, the lead terminal 62, and the signal terminal 52 are each formed by insert molding in the case 8, and the width exposed from the upper part of the case 8 of the lead terminal 61 and the lead terminal 62 (upper left side in the figure).
  • the 10 mm terminal portions 61j and 62j are screw terminals.
  • one end (width: 1.5 mm) of the signal terminal 52 is electrically connected inside the case 8 by a gate electrode 3g which is a control electrode of the IGBT 3S and a bonding wire 51 (aluminum: ⁇ 0.15 mm). From the upper part (upper right side in the figure), the other end of the pin shape is exposed.
  • the lead terminal 61 and the lead terminal 62 form a main current circuit 6 including the power semiconductor element 3 and an external circuit.
  • the gate electrode 3g of the IGBT 3S has a signal circuit 5 connected to the outside by a signal terminal 52 and a bonding wire 51.
  • the inside of the case 8 is filled with resin (sealing body 7) by direct potting, heat cured, and insulated and sealed as described in the first embodiment.
  • the linear expansion coefficient of the sealing body 7 is adjusted so as to be an intermediate value between the linear expansion coefficient of the lead terminal 62 and the linear expansion coefficient of the ceramic substrate 2.
  • the lead terminal 62 of the power semiconductor device 1 according to the second embodiment protrudes downward over the region including the joint portion with the element so that both end portions in the longitudinal direction are farther from the ceramic substrate 2 than the center portion. (Curved portion 62c is formed). Since the curved portion 62c is formed, the vicinity of the end portion 62e is separated from the ceramic substrate 2 and the power semiconductor element 3 toward the end portion 62e. That is, of the facing surface of the lead terminal 62 to the power semiconductor element 3 or the ceramic substrate 2, the end portion 62e of the portion sealed by the sealing body 7 inside the case 8 is directed toward the end portion 62e. An inclined surface 62t that is inclined away from the power semiconductor element 3 or the ceramic substrate 2 is formed.
  • the occurrence of the breakdown starting point is alleviated from concentrating on the boundary portion with the end 62e, and as a result, the life until the breakdown is extended is extended. Can do.
  • the configuration in which the bent portion 62b described in the first embodiment is provided, the configuration in which the thickness is changed, and the configuration in which the bending is performed over the region including the joint portion with the element described in the second embodiment are appropriately combined. It is possible.
  • the sealing body 7 is formed by potting resin in the case 8 is shown, but the present invention is not limited to this.
  • the sealing body may be formed by transfer molding using a mold (not shown) without using a case.
  • the lead terminal 62 is opposed to the ceramic substrate 2 including the portion joined to the power semiconductor element 3 (the electrode thereof). Even if the portion (curved portion 62c) is configured to be curved, the inclined surface 62t can be easily formed.
  • the power semiconductor element 3 has been described using an example of SiC, which is a wide band gap semiconductor material.
  • SiC gallium nitride
  • GaN gallium nitride
  • the present invention can also be applied to a general element using silicon.
  • GaN gallium nitride
  • GaN gallium nitride
  • the inclined surface 62t on the lead terminal 62 so as to be away from the power semiconductor element 3 or the ceramic substrate 2 toward the end 62e, the occurrence of the starting point of destruction is prevented from occurring at the end. As a result, it is possible to relieve the concentration at the boundary with 62e, and as a result, it is possible to further increase the life until the destruction. That is, by using the configuration of the lead terminal 62 according to each embodiment of the present invention, it is possible to obtain a high-performance power semiconductor device 1 that takes advantage of the characteristics of a wide band gap semiconductor.

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Abstract

セラミック基板２と、一面に電極（例えば、３ａ、３ｅ）が形成され、他面がセラミック基板２に接合された電力用半導体素子３と、一端側が電極に接合され、他端側が外部と電気接続されるリード端子６２と、リード端子６２の電極に接合された部分とともに電力用半導体素子３を封止する封止体７と、を備え、リード端子６２の一端側の端部６２ｅに、端部６２ｅに向かうにつれセラミック基板２から遠ざかる傾斜面６２ｔが形成されている。

Description

電力用半導体装置
　本発明は、電力用半導体装置に関し、とくに電力用半導体素子の主電極との電気接続にリード端子を用いた構成に関する。
　産業機器から家電・情報端末まであらゆる製品に電力用半導体装置が普及しつつあり、家電に搭載される電力用半導体装置については、小型軽量化とともに多品種に対応できる高い生産性と高い信頼性が求められる。また、動作温度が高く、効率に優れている点で、今後の主流となる可能性の高い炭化ケイ素（ＳｉＣ）半導体に適用できるパッケージ形態であることも同時に求められている。
　電力用半導体装置では、高電圧・大電流を扱うため、発熱量が大きく、効率的に排熱するために、熱伝導率に優れたセラミック基板を絶縁基板として用いる場合が多い。さらに上述した電力用半導体素子の高密度化に伴い、高い電流密度の回路を形成するために、銅電極板を電力用半導体素子の主電極に直接はんだ付けする手法が用いられつつある。
　しかしながら、セラミック基板（α：６～７ｐｐｍ／Ｋ）のような無機物と銅電極板（α：１６ｐｐｍ／Ｋ）のような金属の組合せでは、従来の樹脂ベースの基板を用いた場合の組合せと比べて線膨張係数（α）の差が大きくなる。そのため、温度変化に伴う伸縮の差が大きく、それに伴う熱応力によって、亀裂等のダメージが発生しやすくなり、長期信頼性が損なわれる恐れがあった。そこで、銅電極板と半導体素子の接合部周辺を柔軟なウレタン樹脂で封止したうえで、全体をエポキシ樹脂で封止するなど、領域によって物性の異なる材料を使い分けるように封止体を構成し、応力を低減する方法等が試みられている（例えば、特許文献１参照）。
特開２００６－３５１７３７号公報（段落００２０～００２７、図１）
　しかしながら、封止体の物性の調整には限界があり、物性の調整のみで応力を緩和することは困難である。また、特許文献のように領域によって物性が異なる封止体を用いると、物性が変化する部分に応力が集中して亀裂等の発生を誘引し、却って信頼性が低下するおそれがあった。
　本発明は、上記のような課題を解決するためになされたもので、大電流に対応した、信頼性の高い電力用半導体装置を得ることを目的としている。
　本発明の電力用半導体装置は、回路基板と、一面に電極が形成され、他面が前記回路基板に接合された電力用半導体素子と、一端側が前記電極に接合され、他端側が外部と電気接続されるリード端子と、前記リード端子の前記電極に接合された部分とともに前記電力用半導体素子を封止する封止体と、を備え、前記リード端子の前記一端側の端部に、前記端部に向かうにつれ前記回路基板から遠ざかる傾斜面が形成されていることを特徴とする。
　本発明の電力用半導体装置によれば、リード端子の端部に回路基板から遠ざかる傾斜面を形成したので、端部との境界部分への応力集中を抑制し、大電流に対応した、信頼性の高い電力用半導体装置を得ることができる。
本発明の実施の形態１にかかる電力用半導体装置の構成を説明するための平面図と断面図である。 本発明の実施の形態１にかかる電力用半導体装置の製造方法を説明するための工程ごとの断面図である。 本発明の実施の形態１にかかる電力用半導体装置における作用効果を説明するための、従来例と実施例のそれぞれのリード端子の端部近傍部分の変位を示す部分断面図である。 本発明の実施の形態１の変形例にかかる電力用半導体装置の構成を説明するための、リード端子の端部の部分断面図である。 本発明の実施の形態１の変形例にかかる電力用半導体装置の構成を説明するための断面図である。 本発明の実施の形態２にかかる電力用半導体装置の構成を説明するための断面図である。
実施の形態１．
　図１～図３は、本発明の実施の形態１にかかる電力用半導体装置の構成、およびその製造方法について説明するための図であり、図１（ａ）は電力用半導体装置から封止樹脂を除いた状態の平面図、図１（ｂ）は図１（ａ）のＡ－Ａ線に対応する断面図である。そして、図２は電力用半導体装置の製造方法を説明するための、図１（ｂ）に対応する工程ごとの断面図、図３は従来例と実施例において、それぞれ常温から高温に温度変化した際の、リード端子の端部の電力用半導体素子に対する変位を示す部分断面図である。
　また、図４は第一変形例として、リード端子の端部の形状を変化させた構成を説明するためのリード端子の端部の部分断面図である。さらに、図５は第二変形例として、封止体の形態を変化させた構成を説明するための断面図であり、図１（ａ）のＡ－Ａ線に対応する。
　本実施の形態１にかかる電力用半導体装置の特徴は、素子の主電極に接合されるリード端子の端部の形状にあるが、はじめに、電力用半導体装置の基本構成について説明する。本実施の形態１にかかる電力用半導体装置１は、図１に示すように、回路基板であるセラミック基板２の導電層２ａに、はんだ４によって電力用半導体素子３（単に「素子」と称する場合あり）がダイボンド（接合）されている。
　セラミック基板２は、４０ｍｍ×２５ｍｍ×厚さ０．６３５ｍｍの窒化アルミニウム（ＡｌＮ）製のセラミック基材２ｉの両面に、厚さ０．４ｍｍの銅の導電層２ａ、２ｂを形成されている。電力用半導体素子３は、ワイドバンドギャップ半導体材料であるＳｉＣを用いた素子で、スイッチング素子としては、厚さ０．２５ｍｍ、１５ｍｍ角の矩形板状をなすＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）３Ｓを、整流素子としては、厚さ０．２５ｍｍ、１５ｍｍ×１５ｍｍの矩形板状をなすダイオード３Ｒを用いた。
　電力用半導体素子３の各主電極のうち、ＩＧＢＴ３Ｓのエミッタ電極３ｅを含む表側の主電極（３ａ、３ｅ）には、本発明の特徴であるリード端子６２の一端部が接合されている。また、ＩＧＢＴ３Ｓのコレクタ電極３ｃを含む、各素子の裏側の電極が接合された導電層２ａには、はんだ４によって、幅８ｍｍ×厚さ０．７ｍｍの銅板製のリード端子６１が接合されている。
　セラミック基板２は、４８ｍｍ×２８ｍｍ×高さ１２ｍｍのＰＰＳ（Poly　Phenylene　Sulfide）樹脂製のケース８の内部に、セラミック基材２ｉ部分との隙間を埋めるようにして、シリコーン製の接着剤９を用いて位置決め固定されている。なお、リード端子６１、リード端子６２、および信号端子５２は、それぞれ、ケース８にインサートモールド形成されており、リード端子６１とリード端子６２のケース８の上部（図中左側上部）から露出した幅１０ｍｍの端子部６１ｊ、６２ｊは、ネジ止め端子となっている。また、信号端子５２の一端部（幅：１．５ｍｍ）は、ケース８の内部でＩＧＢＴ３Ｓの制御電極であるゲート電極３ｇとボンディングワイヤ５１（アルミ製：φ０．１５ｍｍ）によって電気接続され、ケース８の上部（図中右側上部）から、ピン状の他端部が露出している。
　これにより、リード端子６１とリード端子６２とで、電力用半導体素子３と外部回路との主電流回路６が形成される。また、ＩＧＢＴ３Ｓのゲート電極３ｇ（１ｍｍ×２ｍｍ）などは、信号端子５２とボンディングワイヤ５１によって、外部との信号回路５が形成されている。そして、ケース８の内部は、ダイレクトポッティングによって、樹脂（封止体７）が充填され、加熱硬化されて絶縁封止されている。なお、封止体７の線膨張係数は、リード端子６２の線膨張係数とセラミック基板２の線膨張係数の中間の値になるように調整している。
　そして、本実施の形態１にかかる電力用半導体装置１の特徴であるリード端子６２は、長手方向の端部６２ｅに進むにつれ、セラミック基板２および電力用半導体素子３から離れるように傾斜面６２ｔが設けられている。傾斜面６２ｔは、リード端子６２の電力用半導体素子３に接合された平坦部６２ｆに対して、接合部分から（端子部６２ｊの反対側の）端部６２ｅの手前２ｍｍの部分に屈曲部６２ｂ（跳ね上げ角度４５度）を設けることで形成されている。つまり、リード端子６２の電力用半導体素子３あるいはセラミック基板２への対向面のうち、ケース８の内部で封止体７に封止される部分の端部６２ｅでは、端部６２ｅに向かうにつれ、電力用半導体素子３あるいはセラミック基板２から離れるように傾斜している（傾斜面６２ｔが設けられている）。
　つぎに、本実施の形態１にかかる電力用半導体装置１の製造方法について説明する。
　まず、図２（ａ）に示すように、モールドインサートにより、リード端子６１とリード端子６２、および信号端子５２を一体化したケース８を形成する。一方、セラミック基板２の回路面（導電層２ａ側）の所定位置に、それぞれはんだ４によって電力用半導体素子３を接合する。そして、上述したケース８の下部（図中下側）側から、電力用半導体素子３が実装されたセラミック基板２を挿入する。
　次に、図２（ｂ）に示すように、接着剤９を用いて、ケース８に対して、挿入したセラミック基板２を固定する。このとき、セラミック基材２ｉとケース８との隙間には、接着剤９が充填されるので、ケース８とセラミック基板２により、セラミック基板２を底部とし、上方が開放された容器が形成される。また、リード端子６１は導電層２ａに対して、２ｍｍの間隔をおいて対向しており、リード端子６２（平坦部６２ｆ）は電力用半導体素子３の各主電極３ａ、３ｅに対して所定の間隔をあけて対向している。そして、それぞれの間には、図示しないはんだ材が設置されている。
　つぎに、加熱して、上述したはんだをリフローさせたのちに冷却し、図２（ｃ）に示すように、リード端子６１と導電層２ａの間、リード端子６２と電力用半導体素子３の各主電極３ａ、３ｅとの間をはんだ４により接合する。さらに、信号端子５２のうち、ケース８内で露出した端部を、ボンディングワイヤ５１によって、ゲート電極３ｇを含む温度センサー電極などのＩＧＢＴ３Ｓの制御用電極と電気接続する。
　最後に、ダイレクトポッティング樹脂を６０℃に加熱した状態で、ケース８とセラミック基板２とで仕切られた空間内に流し込み、真空脱泡して、加熱（１００℃、１．５時間→１４０℃、１．５時間）して硬化させる。これにより、図１（ｂ）に示すように封止体７が形成されて封止を完了し、電力用半導体装置１（パワーモジュール）が完成する。
　つぎに、上述した電力用半導体装置１の動作と本発明の作用効果について説明する。
　セラミック基板２は、ＡｌＮ製のセラミック基材２ｉの両面に銅の導体層２ａ、２ｂが形成されており、基板全体での線膨張係数は約１０ｐｐｍ／Ｋであるのに対し、銅製のリード端子６２の線膨張係数は１６ｐｐｍ／Ｋである。リード端子６２の封止体７中での端部６２ｅ近傍には、屈曲部６２ｂにより、傾斜面６２ｔが形成されているため、リード端子６２と素子（本実施の形態１では、ＩＧＢＴ３Ｓ）との間隙は、端部６２ｅに向かうほど広がることになる。そのため、リード端子６２と素子との間に介在する封止体７の樹脂の厚さが、端部６２ｅに向かうほど漸増することになる。
　一方、本発明者らは、セラミック基板とリード電極の組みあわせによる電力用半導体装置の様々なサンプルに対して、数多くのヒートサイクル試験を実施してきた。その結果について解析したところ、多くのサンプルにおいて、主電極と接合されるリード端子の封止体内における端部が、破壊の起点となっていることが分かった。外部回路と電力用半導体素子の主電極とを電気接続するリード端子は、基本的には、回路面内を縦断するように延在しているが、その中でも、封止体内における端部に熱ひずみによる応力が集中し、破壊の起点となっていることが分かった。
　しかしながら、本発明の実施の形態１にかかる電力用半導体装置１においては、端部６２ｅに傾斜面６２ｔが形成されているので、端部６２ｅに向かうにつれ、素子との間隔が漸増する。つまり、端部６２ｅに向かうにつれ、線膨張係数が異なる物体の間に介在する封止体７の厚みが厚くなっていき、曲げ強度も大きくなっていく。一方、端部６２ｅよりさらに先に進むと、リード端子６２が途切れることにより、封止体７本体の厚みになる。　
　他方、一般的な電極リードを用いた場合は、端部に向かって封止体の厚みが変化することはなく一定であるが、この場合も、端部６２ｅよりさらに先に進むと、封止体７本体の厚みになる。いずれの場合でも、端子が途切れた部分で封止体７の厚みがステップ状に変化する。しかし、従来の場合、端部６２ｅ近傍で、長尺方向に沿って厚みが変化する部分は、端部６２ｅの一点のみである。それに対して本実施の形態１においては、リード端子６２に挟まれた部分でも厚み（および曲げ強度）が変化しており、厚みが変化する部分が端部６２ｅを含む長さをもった範囲（傾斜面６２ｔ）に分散している。そのため、封止体７にかかる応力の端部６２ｅとの境界部分への集中を緩和し、寿命を延ばすことが可能になる。
　さらに、上記構成の違いにより、応力の分布にも違いが生じる。図３には縦横にリード端子の端部近傍部分の４つの部分断面図を並べており、左側に従来例、右側に本発明の実施例を示している。そして、図中上段が常温時、つまり停止時の状態、下段が高温時、つまり起動時の状態を示す。図中、上段と下段を貫く破線は、それぞれ常温時の従来のリード端子６２Ｃの端部６２ｅの位置Ｐｅと、実施例にかかるリード端子６２の端部６２ｅの位置Ｐｅを示している。そして、破線の位置Ｐｅから電力用半導体素子３に向かう最初の交点は、素子の主面３ｐ上における、常温時の端部の直下となる位置Ｐｐとなる。
　この状態から起動すると、素子の発熱により温度が上昇し、下段に示す高温状態となり、従来例、実施例ともに、部材の膨張により、位置Ｐｅ、Ｐｐともに図中右側に移動する。しかし、線膨張係数の違いから、電力用半導体素子３の主面３ｐ上の位置Ｐｐよりも端子の端部（位置Ｐｅ）の方が右に多く進むため、端子と素子との間に変位が生じる。この変位自体は従来例でも実施例でも同様であるが、従来例と実施例では、端部６２ｅと素子との間隔（図中上下方向の距離）が異なっているため、かかる応力も異なってくる。
　熱応力は、常温時のリード端子６２（あるいは６２Ｃ）の素子への対向面の（図では端部の）位置Ｐｅと、直下の素子の主面３ｐ上の位置Ｐｐを基準とし、高温時における位置Ｐｅと位置Ｐｐを結ぶ線と主面３ｐに垂直な線との角度Ａｅの大きさに比例すると考えられる。そのため、実施例のように傾斜面６２ｔが形成されることで、端部６２ｅに向かうほど、間隔が広がることで角度Ａｅが小さくなり、ひずみが小さくなる。つまり、封止体７の端部６２ｅとの境界部分にかかる応力が従来よりも小さくなる。
　さらに、端部６２ｅを境とする応力の変化も、厚みの変化と同様、傾斜面６２ｔが形成された範囲まで続くので、破壊の起点の発生が端部６２ｅとの境界部分に集中するのを緩和し、結果として破壊に至るまでの寿命を延ばすことができる。なお、上記メカニズムは、実施の形態１に即して、素子の主面３ｐとリード端子６２との関係で説明したが、セラミック基板２の回路面とリード端子６２との関係でも同様の説明ができる。
第一変形例（リード端子の構造）
　上記例では、端部６２ｅに向かうほど、素子との距離が開く傾斜面６２ｔを形成する方法として、板材を曲げる屈曲部６２ｂを設ける例を示したが、これに限ることはない。例えば、図４に示す本変形例のように、コーナーカットのように、端部６２ｅ部分の肉厚を変化させることで、傾斜面６２ｔを形成するようにしてもよい。この場合も、応力や起点発生の集中を緩和し、寿命を延ばすことができる。
　なお、上記例では、セラミック基材２ｉには、ＡｌＮを用いた例を示したが、アルミナ（Ａｌ２Ｏ３）やチッ化ケイ素（ＳｉＮ）などを用いても同様の効果が得られる。また、導電層２ａ、２ｂには、銅を用いた例を示したが、アルミニウムを用いても同様の効果が得られる。さらに、電力用半導体素子３とセラミック基板２の接合、電力用半導体素子３とリード端子６２との接合、およびリード端子６１と導電層２ａとの接合に、はんだ４を用いた例を示したが、銀フィラーをエポキシ樹脂に分散させた導電性接着剤や、銀ナノパウダや銅ナノパウダのような、ナノ粒子を低温焼成させる、接合材料を用いても同様の効果が得られる。
　また、ケース８の材料としてＰＰＳを用いた例を示したが、ＬＣＰ（液晶ポリマー：liquid-crystal　polymer）を用いると、さらなる耐熱性の向上が期待できる。また、封止体７を形成するダイレクトポッティング樹脂については、流し込んで常温硬化させる種類のものでも同様の効果が得られる。
　また、上記例では、ダイオード３ＲとＩＧＢＴ３Ｓが１対１のいわゆる「１ｉｎ１」でのモジュール構成であったが、２対の「２ｉｎ１」や６対の「６ｉｎ１」であっても、リード端子となる金属板上に信号端子を配置することで同様の効果が得られる。さらに、スイッチング素子としては、ＩＧＢＴ３Ｓを用いた例を示したが、例えば、ＭＯＳＦＥＴ（Metal　Oxide　Semiconductor　Field　Effect　Transistor）でもよい。また、ダイオード３Ｒとしては、ＳＢＤ（Schottky　Barrier　Diode：ショットキーバリアダイオード）など、様々な種類の素子を用いることができる。また、素子数も２個に限ることはなく、それ以上でも、１個でもよい。
　また、信号回路５については、アルミ製のボンディングワイヤ５１を用いた例を示したが、銅製ワイヤやアルミ被覆銅ワイヤ、または金ワイヤを用いても同様の効果が得られる。また、リボンボンドを用いたり、金属板を超音波接合するバスバーなどを用いたりしても同様の効果が得られる。
第二変形例（封止体の構造）
　上記例では、ケース８内に樹脂をポッティングして封止体７を形成する例を示したが、これに限ることはない。例えば、図５に示す本変形例のように、ケースを用いずに、図示しない金型を用いてトランスファモールド成型によって、封止体７Ｍを形成する（トランスファモールドパッケージ）ようにしてもよい。
　以上のように、本実施の形態１にかかる電力用半導体装置１によれば、回路基板（セラミック基板２）と、一面に電極（例えば、３ａ、３ｅ）が形成され、他面が回路基板に接合された電力用半導体素子３と、一端側が電極に接合され、他端側が外部と電気接続されるリード端子６２と、リード端子６２の電極に接合された部分とともに電力用半導体素子３を封止する封止体７と、を備え、リード端子６２の一端側の端部６２ｅに、（厳密には、回路基板への対向面が、端部６２ｅに向かうにつれ）回路基板から遠ざかる傾斜面６２ｔが形成されている。そのため、例えば、封止体７のリード端子６２に挟まれた部分の厚み（および曲げ強度）が変化する部分が端部６２ｅを含む長さをもった範囲（傾斜面６２ｔ）に分散しているので、封止体７にかかる応力の端部６２ｅとの境界部分への集中を緩和する。あるいは、端部６２ｅに向かうほど、間隔が広がることで角度Ａｅが小さくなり、ひずみが小さくなり、封止体７の端部６２ｅとの境界部分にかかる応力が従来よりも小さくなる。その結果、大電流に対応するリード端子６２を用いても、寿命を延ばすことが可能になる。
　その際、例えば、端部６２ｅの近傍に屈曲部６２ｂを設ければ、容易に傾斜面６２ｔを形成することができる。
　あるいは、端部６２ｅに向けて肉厚が薄くなるように、例えば、コーナーカット部を設けても容易に傾斜面６２ｔを形成することができる。
　実施の形態２．
　本実施の形態２にかかる電力用半導体装置では、実施の形態１で説明した電力用半導体装置に対して、リード端子の形態を変更したものである。図６は、本発明の実施の形態２にかかる電力用半導体装置の構成について説明するためのもので、実施の形態１で用いた図１（ａ）のＡ－Ａ線に対応する断面図である。本実施の形態２においては、リード端子以外に構成については、変形例を含め実施の形態１で説明したものと同様であるので説明を省略する。また、図中、実施の形態１で説明したものと同様のものには同じ符号を付しており、重複する部分についての詳細な説明は省略する。
　本実施の形態２にかかる電力用半導体装置１も、図６に示すように、回路基板であるセラミック基板２の導電層２ａに、はんだ４によって電力用半導体素子３がダイボンド（接合）されている。
　セラミック基板２には、４０ｍｍ×２５ｍｍ×厚さ０．６３５ｍｍの窒化アルミニウム製のセラミック基材２ｉの両面に、厚さ０．４ｍｍの銅の導電層２ａ、２ｂを形成したものを用いた。電力用半導体素子３は、ワイドバンドギャップ半導体材料であるＳｉＣを用いた素子で、スイッチング素子としては、厚さ０．２５ｍｍ、１５ｍｍ角の矩形板状をなすＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）３Ｓを、整流素子としては、厚さ０．２５ｍｍ、１５ｍｍ×１５ｍｍの矩形板状をなすダイオード３Ｒを用いた。
　電力用半導体素子３の各主電極のうち、ＩＧＢＴ３Ｓのエミッタ電極３ｅを含む表側の主電極（３ａ、３ｅ）には、本発明の特徴であるリード端子６２の一端部が接合されている。また、ＩＧＢＴ３Ｓのコレクタ電極３ｃを含む、各素子の裏側の電極が接合された導電層２ａには、はんだ４によって、幅８ｍｍ×厚さ０．７ｍｍの銅板製のリード端子６１が接合されている。
　セラミック基板２は、４８ｍｍ×２８ｍｍ×高さ１２ｍｍのＰＰＳ（Poly　Phenylene　Sulfide）樹脂製のケース８の内部に、セラミック基材２ｉ部分との隙間を埋めるようにして、シリコーン製の接着剤９を用いて位置決め固定されている。なお、リード端子６１、リード端子６２、および信号端子５２は、それぞれ、ケース８にインサートモールド形成されており、リード端子６１とリード端子６２のケース８の上部（図中左側上部）から露出した幅１０ｍｍの端子部６１ｊ、６２ｊは、ネジ止め端子となっている。また、信号端子５２の一端部（幅：１．５ｍｍ）は、ケース８の内部でＩＧＢＴ３Ｓの制御電極であるゲート電極３ｇとボンディングワイヤ５１（アルミ製：φ０．１５ｍｍ）によって電気接続され、ケース８の上部（図中右側上部）から、ピン状の他端部が露出している。
　これにより、リード端子６１とリード端子６２とで、電力用半導体素子３と外部回路との主電流回路６が形成される。また、ＩＧＢＴ３Ｓのゲート電極３ｇなどは、信号端子５２とボンディングワイヤ５１によって、外部との信号回路５が形成されている。そして、ケース８の内部は、実施の形態１で説明したのと同様に、ダイレクトポッティングによって、樹脂（封止体７）が充填され、加熱硬化されて絶縁封止されている。なお、封止体７の線膨張係数は、リード端子６２の線膨張係数とセラミック基板２の線膨張係数の中間の値になるように調整している。
　そして、本実施の形態２にかかる電力用半導体装置１のリード端子６２は、長手方向の両端部が中央部よりもセラミック基板２から離れるように、素子との接合部分を含む領域にわたって下向きに凸になるように湾曲している（湾曲部６２ｃが形成されている）。湾曲部６２ｃが形成されたことにより、端部６２ｅ近傍部分は、端部６２ｅに向かうにつれ、セラミック基板２および電力用半導体素子３から離れている。つまり、リード端子６２の電力用半導体素子３あるいはセラミック基板２への対向面のうち、ケース８の内部で封止体７に封止される部分の端部６２ｅでは、端部６２ｅに向かうにつれ、電力用半導体素子３あるいはセラミック基板２から離れるように傾斜する傾斜面６２ｔが形成されていることになる。
　これにより、本実施の形態２にかかる電力用半導体装置１においても、破壊の起点の発生が端部６２ｅとの境界部分に集中するのを緩和し、結果として破壊に至るまでの寿命を延ばすことができる。また、実施の形態１で説明した屈曲部６２ｂを設ける構成、肉厚を変化させる構成、および本実施の形態２で説明した素子との接合部を含む領域にわたって湾曲する構成、については、適宜組み合わせることが可能である。
　なお、本実施の形態２においては、ケース８内に樹脂をポッティングして封止体７を形成する例を示したが、これに限ることはない。例えば、実施の形態１の変形例のように、ケースを用いずに、図示しない金型を用いてトランスファモールド成型によって、封止体を形成するようにしてもよい。
　以上のように、本実施の形態２にかかる電力用半導体装置１によれば、電力用半導体素子３（の電極）に接合された部分を含め、リード端子６２のセラミック基板２に対向している部分（湾曲部６２ｃ）が湾曲しているように構成しても、容易に傾斜面６２ｔを形成することができる。
　なお、上記各実施の形態においては、電力用半導体素子３には、ワイドバンドギャップ半導体材料であるＳｉＣを用いた例について説明したが、一般的なシリコンを用いた素子にも適用できることは言うまでもない。しかし、ＳｉＣをはじめ、窒化ガリウム（ＧａＮ）系材料、あるいはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料を用い、電流許容量が高く、高温動作が想定される場合に、特に顕著な効果があらわれる。それは、リード端子６２に必要とされる厚み（断面積）が厚くなるので、剛性が高くなるとともに、運転温度が高くなるため線膨張係数差による変位が大きくなる。
　そのため、上記のように、端部６２ｅに向かうにつれ、電力用半導体素子３あるいはセラミック基板２から離れるように傾斜する傾斜面６２ｔをリード端子６２に形成することで、破壊の起点の発生が端部６２ｅとの境界部分に集中するのを緩和し、結果として破壊に至るまでの寿命を延ばすことができるという効果をより発揮することができる。つまり、本発明の各実施の形態にかかるリード端子６２の構成を用いることで、ワイドバンドギャップ半導体の特性を生かした高性能な電力用半導体装置１を得ることが可能になる。
　１：電力用半導体装置、　２：セラミック基板（回路基板）、　２ａ，２ｂ：導電層、　２ｉ：セラミック基材、　３：電力用半導体素子、　４：はんだ（接合部）、　５：信号回路、　６：主電流回路、　７：封止体、　８：ケース、　９：接着剤、　６１：リード端子、　６２：リード端子、　６２ｃ：湾曲部、　６２ｅ：端部、　６２ｆ：平坦部、　６２ｔ：傾斜面。

Claims (8)

  1. 　回路基板と、
    　一面に電極が形成され、他面が前記回路基板に接合された電力用半導体素子と、
    　一端側が前記電極に接合され、他端側が外部と電気接続されるリード端子と、
    　前記リード端子の前記電極に接合された部分とともに前記電力用半導体素子を封止する封止体と、を備え、
    　前記リード端子の前記一端側の端部に、前記端部に向かうにつれ前記回路基板から遠ざかる傾斜面が形成されていることを特徴とする電力用半導体装置。
  2. 　前記リード端子は、前記傾斜面を形成するために、前記端部の近傍で屈曲していることを特徴とする請求項１に記載の電力用半導体装置。
  3. 　前記リード端子は、前記傾斜面を形成するために、前記端部に向けて肉厚が薄くなっていることを特徴とする請求項１または２に記載の電力用半導体装置。
  4. 　前記リード端子は、前記傾斜面を形成するために、前記電極に接合された部分を含め、前記回路基板に対向している部分が湾曲していることを特徴とする請求項１から３のいずれか１項に記載の電力用半導体装置。
  5. 　前記回路基板の基材が、セラミックで構成されていることを特徴とする請求項１から４のいずれか１項に記載の電力用半導体装置。
  6. 　前記リード端子が、銅板で構成されていることを特徴とする請求項１から５のいずれか１項に記載の電力用半導体装置。
  7. 　前記電力用半導体素子は、ワイドバンドギャップ半導体材料で形成されていることを特徴とする請求項１から６のいずれか１項に記載の電力用半導体装置。
  8. 　前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンドのうちのいずれかであることを特徴とする請求項７に記載の電力用半導体装置。
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