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WO2012102342A1 - Circuit amplificateur de puissance et dispositif de transmission et dispositif de communication faisant appel à celui-ci - Google Patents

Circuit amplificateur de puissance et dispositif de transmission et dispositif de communication faisant appel à celui-ci Download PDF

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Publication number
WO2012102342A1
WO2012102342A1 PCT/JP2012/051662 JP2012051662W WO2012102342A1 WO 2012102342 A1 WO2012102342 A1 WO 2012102342A1 JP 2012051662 W JP2012051662 W JP 2012051662W WO 2012102342 A1 WO2012102342 A1 WO 2012102342A1
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WO
WIPO (PCT)
Prior art keywords
signal
circuit
input
transistor
terminal
Prior art date
Application number
PCT/JP2012/051662
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English (en)
Japanese (ja)
Inventor
伸治 磯山
泰彦 福岡
昭 長山
Original Assignee
京セラ株式会社
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Filing date
Publication date
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Publication of WO2012102342A1 publication Critical patent/WO2012102342A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H03F1/0266—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0458—Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

Definitions

  • the present invention relates to a power amplifying circuit, a transmission device and a communication device using the same, and more particularly to a power amplifying circuit for amplifying a pulse signal and a transmission device and a communication device using the same.
  • a power amplifier circuit in which a signal is input to the gate terminal of a transistor and an amplified signal is output from the drain terminal of the transistor.
  • a DC blocking capacitor is provided between the input terminal and the gate terminal of the transistor. It is inserted (see, for example, Patent Document 1).
  • the above-described conventional power amplifier circuit has a problem that when the pulse signal is amplified, the efficiency decreases as the duty ratio increases.
  • the present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplifying circuit capable of amplifying a pulsed signal with high efficiency, and a transmission apparatus and communication using the same. To provide an apparatus.
  • the capacitor that outputs the second signal by inputting the first signal directly or with the amplitude changed, and the third signal or the first signal having a duty ratio equal to the first signal are input.
  • a conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal, and a second signal that is added to the gate terminal after the second signal and the fourth signal are added.
  • 1 transistor, a first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential, and a drain terminal of the first transistor And an output matching circuit connected thereto.
  • a pulse-shaped signal is a periodic and discrete signal.
  • the waveform is not limited to a rectangle, and includes a signal such as a half-end rectified wave, for example.
  • a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
  • FIG. 1 is a circuit diagram showing a power amplifier circuit of a first example of an embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an example of the integrating circuit 8 in FIG.
  • FIG. 3 is a circuit diagram showing an example of the DC addition circuit 11 in FIG.
  • the power amplifier circuit of this example includes a terminal 1, a terminal 2, a transistor 4, an amplifier 5, a capacitor 6, an output matching circuit 16, a low-pass filter circuit 17, and a conversion.
  • the circuit 31 is provided.
  • the transistor 4 is an n-channel FET, and its pinch-off voltage (threshold voltage for flowing drain current) is Vp.
  • the capacitor 6 has one end connected to the terminal 1 via the amplifier 5 and the other end connected to the gate terminal of the transistor 4.
  • the capacitor 6 prevents the DC bias voltage applied to the gate terminal of the transistor 4 from being applied to the amplifier 5 and an external circuit (not shown) connected to the terminal 1.
  • the terminal 1 receives a first signal S1 which is a pulse signal from an external circuit (not shown).
  • the first signal S1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and input to the gate terminal of the transistor 4 as the second signal S2.
  • the conversion circuit 31 includes a detection circuit 7, an integration circuit 8, a DC addition circuit 11, and a resistor 15.
  • the detection circuit 7 is composed of one resistor and one diode connected in series. One end is connected to the terminal 1 and the other end is connected to the terminal 9 of the integrating circuit 8.
  • the diode is oriented such that the anode is located on the terminal 1 side and the cathode is located on the integrating circuit 8 side.
  • the integration circuit 8 is configured such that the terminal 9 and the terminal 10 are connected via a resistor 21 and the terminal 10 is connected to a ground potential via a capacitor 22. With such a configuration, a low-pass filter circuit is formed, thereby constituting an integrating circuit.
  • the integration circuit 8 outputs a signal having a DC voltage having a magnitude corresponding to the duty ratio of the first signal S1.
  • An active low-pass filter or a passive low-pass filter may be added to attenuate high-frequency components.
  • the DC adder circuit 11 includes resistors 23, 24, and 26, an OP amplifier 25, and terminals 12, 13, and 14, as shown in FIG.
  • One ends of the resistors 23 and 24 are connected to each other and connected to one end of the resistor 26 and one input terminal of the OP amplifier.
  • the other ends of the resistors 23 and 24 are connected to terminals 12 and 13, respectively.
  • Terminal 12 is connected to terminal 10 of integrating circuit 8.
  • Terminal 13 is connected to DC bias potential Vg.
  • the output terminal of the OP amplifier is connected to the other end of the resistor 26 and the terminal 14.
  • the DC addition circuit 11 adds the output signal of the integration circuit 8 input to the terminal 12 and the DC bias voltage Vg input to the terminal 13 and outputs the result from the terminal 14.
  • the resistor 15 has one end connected to the terminal 14 of the DC addition circuit 11 and the other end connected to the other end of the capacitor 6 and the gate terminal of the transistor 4.
  • the conversion circuit 31 having such a configuration receives the first signal S1 and outputs a fourth signal S4 having a DC voltage that increases or decreases according to the increase or decrease of the duty ratio of the first signal S1.
  • the input to the conversion circuit 31 may be any signal having the same duty ratio as that of the first signal S1.
  • the gate terminal of the transistor 4 is connected to the other end of the capacitor 6 and the other end of the resistor 15 of the conversion circuit 31.
  • the second signal S2 and the fourth signal S4 are added and input to the gate terminal of the transistor 4. .
  • the low-pass filter circuit 17 is composed of one inductor, and one end is connected to the drain terminal of the transistor 4 and the other end is connected to the power supply potential Vdd.
  • the low-pass filter circuit 17 supplies the power supply potential Vdd to the drain terminal of the transistor 4 and prevents a high-frequency signal from flowing out to the power supply potential Vdd side.
  • the output matching circuit 16 has one end connected to the drain terminal of the transistor 4 and the other end connected to the terminal 2.
  • the output matching circuit 16 is for matching the impedance between the drain terminal of the transistor 4 and the terminal 2.
  • the output matching circuit 16 can be configured, for example, by connecting a DC cut capacitor and an LC series resonance circuit that resonates at the fundamental frequency in series. With this configuration, only the fundamental wave component of the signal output from the drain terminal of the transistor 4 can be output from the terminal 2.
  • the power amplifier circuit of this example having such a configuration can amplify the first signal S1 input to the terminal 1 by the amplifier 5 and the transistor 4 and output it from the terminal 2. Further, according to the power amplifier circuit of this example, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
  • FIGS. 4A to 4D are graphs for explaining the effect of the present invention, in which the horizontal axis indicates time and the vertical axis indicates the voltage of the pulse signal.
  • Vp is a pinch-off voltage of the transistor 4, and a drain current corresponding to the voltage of the pulse signal flows while the voltage of the pulse signal input to the gate terminal of the transistor 4 exceeds Vp.
  • the first signal S1 input to the terminal 1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and the second signal S2 is input to the gate terminal of the transistor 4.
  • the first signal S1 is a pulse-like signal
  • the DC component is cut by the capacitor 6 so that the waveform of the pulse signal is entirely shifted to the negative voltage side.
  • the shift amount at this time is proportional to the average voltage of the pulse signal. Therefore, the shift amount increases in accordance with the duty ratio of the pulse signal, and becomes maximum when the duty ratio is 0.5.
  • FIG. 4A The waveform of a square pulse wave with a duty ratio of 0.5 before the DC component is cut is shown in FIG. 4A, and the waveform of a square pulse wave with a duty ratio of 0.5 after the DC component is cut is shown.
  • FIG. 4C shows a waveform of a square pulse wave with a duty ratio of 0.1 before the DC component is cut, and a square pulse wave with a duty ratio of 0.1 after the DC component is cut.
  • the waveform is shown in FIG.
  • the shift amount to the negative voltage side due to the cut of the direct current component is 1 / th of the wave height of the pulse signal. 2
  • the shift amount to the negative voltage side due to the cut of the direct current component is the wave height of the pulse signal. 1/10.
  • the DC cut capacitor When the direct current component is cut, the voltage of the signal input to the gate terminal of the transistor decreases, and the signal output from the drain terminal of the transistor decreases. This reduces the efficiency of the power amplifier circuit. And the efficiency of a power amplifier circuit falls large, so that the duty ratio of the signal input into a power amplifier circuit is large.
  • the fourth signal S4 having a DC voltage that increases or decreases in accordance with the increase or decrease of the duty ratio of the input signal (first signal S1) is output from the conversion circuit 31, and is converted into the second signal S2. The sum is added to the gate terminal of the transistor 4.
  • the power amplifier circuit of this example functions as a power amplifier circuit capable of amplifying a pulse signal with high efficiency. Note that the effect of the power amplifier circuit of this example increases as the duty ratio of the input first signal S1 increases.
  • the present invention is not limited to this.
  • the first signal S1 input from the terminal 1 may be input to the capacitor 6 as it is.
  • the conversion circuit 31, the detection circuit 7, the integration circuit 8, the DC addition circuit 11, the low-pass filter circuit 17, and the output matching circuit 16 are limited to the circuit configuration described above. is not. Each can be replaced with another circuit configuration having a similar function.
  • FIG. 5 is a circuit diagram showing a power amplifier circuit according to a second example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
  • the output matching circuit 16 includes a capacitor 18, an LC series resonance circuit 19, and a low-pass filter circuit 20.
  • the LC series resonance circuit 19 is connected in series between the input and output of the output matching circuit 16 (between the drain terminal and the terminal 2 of the transistor 4).
  • the LC series resonant circuit 19 is composed of one inductor and one capacitor connected in series with each other, and the inductance of the inductor and the capacitance of the capacitor so as to resonate at the fundamental frequency of the first signal S1. Is set.
  • the low-pass filter circuit 20 is cascade-connected to the LC series resonance circuit 19 and connects the LC series resonance circuit 19 and the terminal 2.
  • the low-pass filter circuit 20 is composed of a ⁇ -type circuit composed of two capacitors and one inductor.
  • the low-pass filter circuit 20 allows a signal having a fundamental frequency of the first signal S1 to pass therethrough and harmonics of the first signal S1.
  • the capacitance of the capacitor and the inductance of the inductor are set so as to attenuate the wave frequency signal.
  • the capacitor 18 is connected between the drain terminal of the first transistor 4 and a reference potential (ground potential).
  • the output matching circuit 16 since the output matching circuit 16 includes the cascaded LC series resonance circuit 19 and the low-pass filter circuit 20, an input signal (first output) In a region where the duty ratio of one signal S1) is large, a high and constant efficiency can be obtained. Although the mechanism for obtaining this effect has not been clearly identified, it is considered that the output matching circuit 16 reflects the harmonic component in the signal output from the drain terminal of the transistor 4.
  • the low-pass filter circuit 20 is not limited to a ⁇ -type circuit composed of two capacitors and one inductor.
  • the low-pass filter circuit 20 may be constituted by one inductor connected in series between the input and output and one capacitor connecting between the input and output and the ground potential.
  • the low-pass filter circuit 20 may be provided.
  • FIG. 6 is a circuit diagram showing a power amplifier circuit of a third example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
  • the power amplifier circuit of this example does not include terminal 1 as compared with the power amplifier circuit shown in FIG. 1, and includes transistor 33, transistor 34, terminal 41, terminal 42, and so on. Is further provided.
  • the fifth signal S5 is input from the external circuit (not shown) to the terminal 41
  • the sixth signal S6 is input from the external circuit (not shown) to the terminal 42.
  • the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases.
  • the transistors 33 and 34 are n-channel FETs, and their pinch-off voltage (threshold voltage for flowing a drain current) is Vp.
  • the transistor 33 has a gate terminal connected to the terminal 42, a source terminal connected to the terminal 41, and a drain terminal connected to the gate terminal of the transistor 4 via the amplifier 5 and the capacitor 6.
  • the fifth signal S5 is input to the source terminal
  • the sixth signal S6 is input to the gate terminal
  • the output signal from the drain terminal is input to the amplifier 5 as the first signal S1.
  • the transistor 34 has a gate terminal connected to the terminal 41, a source terminal connected to the terminal 42, and a drain terminal connected to one end of the detection circuit 7.
  • the sixth signal S6 is input to the source terminal
  • the fifth signal S5 is input to the gate terminal
  • the output signal from the drain terminal is input to one end of the detection circuit 7 as the third signal S3. Is done.
  • a DC bias voltage is supplied to the gate terminals of the transistors 33 and 34 from a bias circuit (not shown).
  • the transistors 33 and 34 are n-channel transistors, when a positive voltage equal to or higher than the pinch-off voltage Vp is applied to the gate terminal, the drain terminal and the source terminal become conductive. Therefore, the transistor 33 passes the fifth signal S5 and outputs it as the first signal S1 from the drain terminal while the voltage of the sixth signal S6 is a positive voltage equal to or higher than Vp. While the fifth signal S5 is a positive voltage equal to or higher than Vp, the transistor 34 passes the sixth signal S6 and outputs it from the drain terminal as the third signal S3.
  • the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases, the first signal S1 output from the drain terminal of the transistor 33 and the output from the drain terminal of the transistor 34 are output.
  • the third signal S3 is a pulse signal having the same duty ratio.
  • the first signal S1 is output from the drain terminal of the transistor 33 only while the voltage of the sixth signal S6 is a positive voltage higher than Vp, the period during which the first signal S1 is a positive voltage higher than Vp. Corresponds to a period in which both the fifth signal S5 and the sixth signal S6 are positive voltages larger than the pinch-off voltage Vp.
  • the first signal S1 is amplified by the amplifier 5, passes through the capacitor 6, is input to the gate terminal of the transistor 4 as the second signal S2, and the transistor 4 is turned on and off.
  • the time during which the transistor 4 is ON varies depending on the phase difference between the fifth signal S5 and the sixth signal S6. That is, when the phase difference between the fifth signal S5 and the sixth signal S6 is small, the time during which the transistor 4 is ON is long, and when the phase difference between the fifth signal S5 and the sixth signal S6 is large, the transistor The time during which 4 is ON is shortened. Thereby, the increase / decrease in the phase difference between the fifth signal S5 and the sixth signal S6 is replaced with the increase / decrease in the time during which the transistor 4 is in the ON state.
  • the drain voltage of the transistor 4 also includes the same frequency component as the fifth signal S5 and the sixth signal S6.
  • the fundamental wave component (the same frequency component as the fifth signal S5 and the sixth signal S6) is extracted from the drain voltage of the transistor 4 by the output matching circuit 16, and is output from the terminal 2.
  • This output signal has an amplitude that increases and decreases contrary to the increase and decrease of the phase difference between the fifth signal S5 and the sixth signal S6, and is an amplified signal obtained by synthesizing the fifth signal S5 and the sixth signal S6. .
  • the power amplifier circuit functions as a power amplifier circuit that can amplify and output two constant envelope signals by vector addition.
  • the voltage drop applied to the gate terminal of the transistor 4 that occurs when the phase difference between the fifth signal S5 and the sixth signal S6 is small can be reduced by the conversion circuit 31. Therefore, according to the power amplifier circuit of this example, it is possible to obtain a power amplifier circuit in which a decrease in amplification efficiency when the phase difference between the fifth signal S5 and the sixth signal S6 is large is reduced.
  • the sixth signal S6 is input to the gate terminal of the transistor 33 and the fifth signal S5 is input to the gate terminal of the transistor 34.
  • the signal input to the gate terminal of the transistor 33 may be a signal in phase with the sixth signal S6, and the signal input to the gate terminal of the transistor 34 may be a signal in phase with the fifth signal S5.
  • FIG. 7 is a circuit diagram showing a power amplifier circuit according to a fourth example of the embodiment of the present invention. 7, in addition to the power amplifier circuit 61 shown in FIG. 6, the power amplifier circuit of this example is configured to convert an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal S5. And a constant envelope signal generation circuit 62 that converts the second constant envelope signal to be the sixth signal S6 and outputs the second constant envelope signal.
  • the first constant envelope signal (fifth signal S5) and the second constant envelope signal (sixth signal S6) are constant envelope signals having the same frequency and amplitude and different phases.
  • the constant envelope signal generation circuit 62 various well-known constant envelope signal generation circuits can be used, and either a digital circuit or an analog circuit may be used.
  • the first constant envelope signal and the second constant signal having a phase difference that increases or decreases the input signal having the envelope fluctuation in the opposite direction to the increase or decrease in the amplitude of the input signal.
  • the first constant envelope signal and the second constant signal After being converted into an envelope signal, it can be amplified with high power supply efficiency, and an output signal having an amplified envelope variation can be output. Thereby, a power amplifier circuit with high power supply efficiency can be obtained.
  • FIG. 8 is a block diagram showing a transmission apparatus according to a fifth example of the embodiment of the present invention.
  • the transmission apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, and an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70. Yes.
  • the transmission signal output from the transmission circuit 81 is amplified using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a transmitter with low power consumption can be obtained.
  • FIG. 9 is a block diagram showing a communication apparatus according to a sixth example of the embodiment of the present invention.
  • the communication apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70, and an antenna 82. And a receiving circuit 83 connected thereto.
  • An antenna sharing circuit 84 is inserted between the antenna 82 and the power amplification circuit 70 and the reception circuit 83. That is, the power amplifying circuit 70 and the receiving circuit 83 are connected to the antenna 82 via the antenna sharing circuit 84.
  • the transmission signal output from the transmission circuit 81 is amplified using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a communication apparatus with low power consumption can be obtained.
  • the antenna sharing circuit 84 is not always necessary and may be omitted.
  • the transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V.
  • the power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V.
  • the input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.
  • the graph shown in FIG. 10 shows that the power amplifier circuit of the present invention has higher drain efficiency than the power amplifier circuit of the comparative example.
  • the difference between the drain efficiency of the power amplifier circuit of the present invention and the drain efficiency of the power amplifier circuit of the comparative example may increase. Recognize.
  • the transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V.
  • the power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V.
  • the input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.
  • the capacitance of the capacitor 18 was 0.3 pF.
  • the LC series resonance circuit 19 is composed of an inductor of 11.8 nH and a capacitor of 4.3 pF.
  • the low-pass filter circuit 20 is composed of a ⁇ -type circuit composed of 3.9 pF and 3 pF capacitors and a 19.1 nH inductor.
  • the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5).
  • the vertical axis represents drain efficiency.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

Cette invention se rapporte à un circuit amplificateur de puissance capable d'amplifier un signal pulsé avec un rendement élevé ainsi qu'à un dispositif de transmission et à un dispositif de communication faisant appel à celui-ci. Ce circuit amplificateur de puissance est doté : d'un condensateur (6) dans lequel est entré un premier signal (S1) et qui délivre en sortie un deuxième signal (S2) ; d'un circuit conversion (31) dans lequel est entré un troisième signal (S3) qui présente le même rapport cyclique que celui du premier signal (S1), ou celui du premier signal (S1), et qui délivre en sortie un quatrième signal (S4) qui présente une tension continue qui augmente ou diminue selon une augmentation ou une diminution du rapport cyclique du signal qui a été entré ; d'un transistor (4) où le deuxième signal (S2) et le quatrième signal (S4) sont additionnés et entrés dans une borne de grille ; un premier circuit filtre passe-bas (17) de telle sorte qu'une extrémité soit connectée à la borne de drain du transistor (4) et que l'autre extrémité soit connectée à un potentiel d'alimentation (Vdd) ; et un circuit d'adaptation de sortie (16) qui est connecté à la borne de drain du transistor (4).
PCT/JP2012/051662 2011-01-27 2012-01-26 Circuit amplificateur de puissance et dispositif de transmission et dispositif de communication faisant appel à celui-ci WO2012102342A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2011-015427 2011-01-27
JP2011015427 2011-01-27
JP2011163347 2011-07-26
JP2011-163347 2011-07-26

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WO2012102342A1 true WO2012102342A1 (fr) 2012-08-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3360248A4 (fr) * 2016-07-27 2018-10-24 Elbit Systems Land and C4I Ltd. Réduction de la consommation d'énergie dans des amplificateurs de puissance intégrés à bande ultra-large

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311057A (ja) * 1993-04-26 1994-11-04 Nec Corp 無線電力送信装置
JP2003204590A (ja) * 2002-01-08 2003-07-18 Yamaha Corp Ｄ級増幅器
JP2004350276A (ja) * 2003-05-19 2004-12-09 Samsung Electronics Co Ltd 集積可能な電圧調整超高周波電力増幅器
JP2008167289A (ja) * 2006-12-28 2008-07-17 Samsung Electronics Co Ltd 送信装置
JP2009182906A (ja) * 2008-01-31 2009-08-13 Kyocera Corp 増幅器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311057A (ja) * 1993-04-26 1994-11-04 Nec Corp 無線電力送信装置
JP2003204590A (ja) * 2002-01-08 2003-07-18 Yamaha Corp Ｄ級増幅器
JP2004350276A (ja) * 2003-05-19 2004-12-09 Samsung Electronics Co Ltd 集積可能な電圧調整超高周波電力増幅器
JP2008167289A (ja) * 2006-12-28 2008-07-17 Samsung Electronics Co Ltd 送信装置
JP2009182906A (ja) * 2008-01-31 2009-08-13 Kyocera Corp 増幅器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3360248A4 (fr) * 2016-07-27 2018-10-24 Elbit Systems Land and C4I Ltd. Réduction de la consommation d'énergie dans des amplificateurs de puissance intégrés à bande ultra-large

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