WO2012102342A1

WO2012102342A1 - Power amplifier circuit, as well as transmission device and communication device using same

Info

Publication number: WO2012102342A1
Application number: PCT/JP2012/051662
Authority: WO
Inventors: 伸治磯山; 泰彦福岡; 昭長山
Original assignee: 京セラ株式会社
Priority date: 2011-01-27
Filing date: 2012-01-26
Publication date: 2012-08-02

Abstract

[Problem] To provide a power amplifier circuit capable of amplifying a pulsed signal with high efficiency as well as a transmission device and a communication device using the same. [Solution] This power amplifier circuit is provided with: a capacitor (6) into which is input a first signal (S1) and which outputs a second signal (S2); a conversion circuit (31) into which is input a third signal (S3) of the same duty ratio as the first signal (S1), or the first signal (S1), and which outputs a fourth signal (S4) having a DC voltage which increases or decreases according to an increase or decrease of the duty ratio of the signal which has been input; a transistor (4) for which the second signal (S2) and the fourth signal (S4) are summed and input into a gate terminal; a first lowpass filter circuit (17) such that one end is connected to the drain terminal of the transistor (4) and the other end is connected to a supply potential (Vdd); and an output matching circuit (16) which is connected to the drain terminal of the transistor (4).

Description

Power amplifier circuit and transmitter and communication device using the same

The present invention relates to a power amplifying circuit, a transmission device and a communication device using the same, and more particularly to a power amplifying circuit for amplifying a pulse signal and a transmission device and a communication device using the same.

Conventionally, a power amplifier circuit is known in which a signal is input to the gate terminal of a transistor and an amplified signal is output from the drain terminal of the transistor. In such a power amplifier circuit, in order to prevent the DC bias voltage supplied to the gate terminal of the transistor from being applied to the circuit on the previous stage, a DC blocking capacitor is provided between the input terminal and the gate terminal of the transistor. It is inserted (see, for example, Patent Document 1).

JP 2010-21927 A

However, the above-described conventional power amplifier circuit has a problem that when the pulse signal is amplified, the efficiency decreases as the duty ratio increases.

The present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplifying circuit capable of amplifying a pulsed signal with high efficiency, and a transmission apparatus and communication using the same. To provide an apparatus.

In the power amplifier circuit of the present invention, the capacitor that outputs the second signal by inputting the first signal directly or with the amplitude changed, and the third signal or the first signal having a duty ratio equal to the first signal are input. A conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal, and a second signal that is added to the gate terminal after the second signal and the fourth signal are added. 1 transistor, a first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential, and a drain terminal of the first transistor And an output matching circuit connected thereto.

In addition, in this specification, a pulse-shaped signal is a periodic and discrete signal. The waveform is not limited to a rectangle, and includes a signal such as a half-end rectified wave, for example.

According to the power amplifier circuit of the present invention, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.

It is a circuit diagram showing a power amplifier circuit of the 1st example of an embodiment of the invention. It is a circuit diagram which shows an example of the integration circuit in FIG. It is a circuit diagram which shows an example of the DC adder in FIG. (A)-(d) is a figure for demonstrating the mechanism in which the effect of this invention is acquired. It is a circuit diagram which shows the power amplifier circuit of the 2nd example of embodiment of this invention. It is a circuit diagram which shows the power amplifier circuit of the 3rd example of embodiment of this invention. It is a circuit diagram which shows the power amplifier circuit of the 4th example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 5th example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 6th example of embodiment of this invention. It is a graph which shows the simulation result of the power amplifier circuit of the 1st example of embodiment of this invention, and the power amplifier circuit of a comparative example. It is a graph which shows the simulation result of the power amplification circuit of the 2nd example of an embodiment of the invention.

Hereinafter, a power amplification circuit of the present invention and a transmission device and a communication device using the same will be described in detail with reference to the accompanying drawings.

(First example of embodiment)
FIG. 1 is a circuit diagram showing a power amplifier circuit of a first example of an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the integrating circuit 8 in FIG. FIG. 3 is a circuit diagram showing an example of the DC addition circuit 11 in FIG.

As shown in FIG. 1, the power amplifier circuit of this example includes a terminal 1, a terminal 2, a transistor 4, an amplifier 5, a capacitor 6, an output matching circuit 16, a low-pass filter circuit 17, and a conversion. The circuit 31 is provided. The transistor 4 is an n-channel FET, and its pinch-off voltage (threshold voltage for flowing drain current) is Vp.

The capacitor 6 has one end connected to the terminal 1 via the amplifier 5 and the other end connected to the gate terminal of the transistor 4. The capacitor 6 prevents the DC bias voltage applied to the gate terminal of the transistor 4 from being applied to the amplifier 5 and an external circuit (not shown) connected to the terminal 1. The terminal 1 receives a first signal S1 which is a pulse signal from an external circuit (not shown). The first signal S1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and input to the gate terminal of the transistor 4 as the second signal S2.

The conversion circuit 31 includes a detection circuit 7, an integration circuit 8, a DC addition circuit 11, and a resistor 15. The detection circuit 7 is composed of one resistor and one diode connected in series. One end is connected to the terminal 1 and the other end is connected to the terminal 9 of the integrating circuit 8. The diode is oriented such that the anode is located on the terminal 1 side and the cathode is located on the integrating circuit 8 side.

As shown in FIG. 2, the integration circuit 8 is configured such that the terminal 9 and the terminal 10 are connected via a resistor 21 and the terminal 10 is connected to a ground potential via a capacitor 22. With such a configuration, a low-pass filter circuit is formed, thereby constituting an integrating circuit. The integration circuit 8 outputs a signal having a DC voltage having a magnitude corresponding to the duty ratio of the first signal S1. An active low-pass filter or a passive low-pass filter may be added to attenuate high-frequency components.

The DC adder circuit 11 includes

resistors

23, 24, and 26, an OP amplifier 25, and

terminals

12, 13, and 14, as shown in FIG. One ends of the

resistors

23 and 24 are connected to each other and connected to one end of the resistor 26 and one input terminal of the OP amplifier. The other ends of the

resistors

23 and 24 are connected to

terminals

12 and 13, respectively. Terminal 12 is connected to terminal 10 of integrating circuit 8. Terminal 13 is connected to DC bias potential Vg. The output terminal of the OP amplifier is connected to the other end of the resistor 26 and the terminal 14. The DC addition circuit 11 adds the output signal of the integration circuit 8 input to the terminal 12 and the DC bias voltage Vg input to the terminal 13 and outputs the result from the terminal 14.

The resistor 15 has one end connected to the terminal 14 of the DC addition circuit 11 and the other end connected to the other end of the capacitor 6 and the gate terminal of the transistor 4.

The conversion circuit 31 having such a configuration receives the first signal S1 and outputs a fourth signal S4 having a DC voltage that increases or decreases according to the increase or decrease of the duty ratio of the first signal S1. Note that the input to the conversion circuit 31 may be any signal having the same duty ratio as that of the first signal S1.

The gate terminal of the transistor 4 is connected to the other end of the capacitor 6 and the other end of the resistor 15 of the conversion circuit 31. The second signal S2 and the fourth signal S4 are added and input to the gate terminal of the transistor 4. .

The low-pass filter circuit 17 is composed of one inductor, and one end is connected to the drain terminal of the transistor 4 and the other end is connected to the power supply potential Vdd. The low-pass filter circuit 17 supplies the power supply potential Vdd to the drain terminal of the transistor 4 and prevents a high-frequency signal from flowing out to the power supply potential Vdd side.

The output matching circuit 16 has one end connected to the drain terminal of the transistor 4 and the other end connected to the terminal 2. The output matching circuit 16 is for matching the impedance between the drain terminal of the transistor 4 and the terminal 2. The output matching circuit 16 can be configured, for example, by connecting a DC cut capacitor and an LC series resonance circuit that resonates at the fundamental frequency in series. With this configuration, only the fundamental wave component of the signal output from the drain terminal of the transistor 4 can be output from the terminal 2.

The power amplifier circuit of this example having such a configuration can amplify the first signal S1 input to the terminal 1 by the amplifier 5 and the transistor 4 and output it from the terminal 2. Further, according to the power amplifier circuit of this example, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.

The mechanism for obtaining this effect will be described with reference to FIGS. 4A to 4D are graphs for explaining the effect of the present invention, in which the horizontal axis indicates time and the vertical axis indicates the voltage of the pulse signal. Vp is a pinch-off voltage of the transistor 4, and a drain current corresponding to the voltage of the pulse signal flows while the voltage of the pulse signal input to the gate terminal of the transistor 4 exceeds Vp.

The first signal S1 input to the terminal 1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and the second signal S2 is input to the gate terminal of the transistor 4. When the first signal S1 is a pulse-like signal, the DC component is cut by the capacitor 6 so that the waveform of the pulse signal is entirely shifted to the negative voltage side. The shift amount at this time is proportional to the average voltage of the pulse signal. Therefore, the shift amount increases in accordance with the duty ratio of the pulse signal, and becomes maximum when the duty ratio is 0.5.

The waveform of a square pulse wave with a duty ratio of 0.5 before the DC component is cut is shown in FIG. 4A, and the waveform of a square pulse wave with a duty ratio of 0.5 after the DC component is cut is shown. As shown in FIG. FIG. 4C shows a waveform of a square pulse wave with a duty ratio of 0.1 before the DC component is cut, and a square pulse wave with a duty ratio of 0.1 after the DC component is cut. The waveform is shown in FIG.

As shown in FIGS. 4A and 4B, in the case of a square pulse signal with a duty ratio of 0.5, the shift amount to the negative voltage side due to the cut of the direct current component is 1 / th of the wave height of the pulse signal. 2 As shown in FIGS. 4C and 4D, in the case of a square pulse signal with a duty ratio of 0.1, the shift amount to the negative voltage side due to the cut of the direct current component is the wave height of the pulse signal. 1/10.

In this way, in the power amplifier circuit that inputs the input pulse-like signal to the gate terminal of the transistor via the DC cut capacitor and outputs the amplified signal from the drain terminal of the transistor, the DC cut capacitor When the direct current component is cut, the voltage of the signal input to the gate terminal of the transistor decreases, and the signal output from the drain terminal of the transistor decreases. This reduces the efficiency of the power amplifier circuit. And the efficiency of a power amplifier circuit falls large, so that the duty ratio of the signal input into a power amplifier circuit is large.

In the power amplifier circuit of this example, the fourth signal S4 having a DC voltage that increases or decreases in accordance with the increase or decrease of the duty ratio of the input signal (first signal S1) is output from the conversion circuit 31, and is converted into the second signal S2. The sum is added to the gate terminal of the transistor 4. As the duty ratio of the first signal S1 increases, the voltage of the fourth signal S4 increases accordingly, so that the voltage drop of the signal applied to the gate terminal of the transistor 4 can be reduced. Therefore, the power amplifier circuit of this example functions as a power amplifier circuit capable of amplifying a pulse signal with high efficiency. Note that the effect of the power amplifier circuit of this example increases as the duty ratio of the input first signal S1 increases.

In the power amplifier circuit of this example, the example in which the first signal S1 input from the terminal 1 is amplified by the amplifier 5 and then input to the capacitor 6 is shown, but the present invention is not limited to this. . For example, the first signal S1 input from the terminal 1 may be input to the capacitor 6 as it is.

In the power amplifier circuit of this example, the conversion circuit 31, the detection circuit 7, the integration circuit 8, the DC addition circuit 11, the low-pass filter circuit 17, and the output matching circuit 16 are limited to the circuit configuration described above. is not. Each can be replaced with another circuit configuration having a similar function.

(Second example of embodiment)
FIG. 5 is a circuit diagram showing a power amplifier circuit according to a second example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

In the power amplifier circuit of this example, as shown in FIG. 5, the output matching circuit 16 includes a capacitor 18, an LC series resonance circuit 19, and a low-pass filter circuit 20.

The LC series resonance circuit 19 is connected in series between the input and output of the output matching circuit 16 (between the drain terminal and the terminal 2 of the transistor 4). The LC series resonant circuit 19 is composed of one inductor and one capacitor connected in series with each other, and the inductance of the inductor and the capacitance of the capacitor so as to resonate at the fundamental frequency of the first signal S1. Is set.

The low-pass filter circuit 20 is cascade-connected to the LC series resonance circuit 19 and connects the LC series resonance circuit 19 and the terminal 2. The low-pass filter circuit 20 is composed of a π-type circuit composed of two capacitors and one inductor. The low-pass filter circuit 20 allows a signal having a fundamental frequency of the first signal S1 to pass therethrough and harmonics of the first signal S1. The capacitance of the capacitor and the inductance of the inductor are set so as to attenuate the wave frequency signal.

The capacitor 18 is connected between the drain terminal of the first transistor 4 and a reference potential (ground potential).

In the power amplifier circuit of this example having such a configuration, since the output matching circuit 16 includes the cascaded LC series resonance circuit 19 and the low-pass filter circuit 20, an input signal (first output) In a region where the duty ratio of one signal S1) is large, a high and constant efficiency can be obtained. Although the mechanism for obtaining this effect has not been clearly identified, it is considered that the output matching circuit 16 reflects the harmonic component in the signal output from the drain terminal of the transistor 4.

The low-pass filter circuit 20 is not limited to a π-type circuit composed of two capacitors and one inductor. For example, the low-pass filter circuit 20 may be constituted by one inductor connected in series between the input and output and one capacitor connecting between the input and output and the ground potential. The low-pass filter circuit 20 may be provided.

(Third example of embodiment)
FIG. 6 is a circuit diagram showing a power amplifier circuit of a third example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

As shown in FIG. 6, the power amplifier circuit of this example does not include terminal 1 as compared with the power amplifier circuit shown in FIG. 1, and includes transistor 33, transistor 34, terminal 41, terminal 42, and so on. Is further provided. In the power amplifier circuit of this example, the fifth signal S5 is input from the external circuit (not shown) to the terminal 41, and the sixth signal S6 is input from the external circuit (not shown) to the terminal 42. The fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases. The

transistors

33 and 34 are n-channel FETs, and their pinch-off voltage (threshold voltage for flowing a drain current) is Vp.

The transistor 33 has a gate terminal connected to the terminal 42, a source terminal connected to the terminal 41, and a drain terminal connected to the gate terminal of the transistor 4 via the amplifier 5 and the capacitor 6. In the transistor 33, the fifth signal S5 is input to the source terminal, the sixth signal S6 is input to the gate terminal, and the output signal from the drain terminal is input to the amplifier 5 as the first signal S1.

The transistor 34 has a gate terminal connected to the terminal 41, a source terminal connected to the terminal 42, and a drain terminal connected to one end of the detection circuit 7. In the transistor 34, the sixth signal S6 is input to the source terminal, the fifth signal S5 is input to the gate terminal, and the output signal from the drain terminal is input to one end of the detection circuit 7 as the third signal S3. Is done. A DC bias voltage is supplied to the gate terminals of the

transistors

33 and 34 from a bias circuit (not shown).

Since the

transistors

33 and 34 are n-channel transistors, when a positive voltage equal to or higher than the pinch-off voltage Vp is applied to the gate terminal, the drain terminal and the source terminal become conductive. Therefore, the transistor 33 passes the fifth signal S5 and outputs it as the first signal S1 from the drain terminal while the voltage of the sixth signal S6 is a positive voltage equal to or higher than Vp. While the fifth signal S5 is a positive voltage equal to or higher than Vp, the transistor 34 passes the sixth signal S6 and outputs it from the drain terminal as the third signal S3. Since the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases, the first signal S1 output from the drain terminal of the transistor 33 and the output from the drain terminal of the transistor 34 are output. The third signal S3 is a pulse signal having the same duty ratio.

Further, since the first signal S1 is output from the drain terminal of the transistor 33 only while the voltage of the sixth signal S6 is a positive voltage higher than Vp, the period during which the first signal S1 is a positive voltage higher than Vp. Corresponds to a period in which both the fifth signal S5 and the sixth signal S6 are positive voltages larger than the pinch-off voltage Vp. The first signal S1 is amplified by the amplifier 5, passes through the capacitor 6, is input to the gate terminal of the transistor 4 as the second signal S2, and the transistor 4 is turned on and off.

Therefore, the time during which the transistor 4 is ON varies depending on the phase difference between the fifth signal S5 and the sixth signal S6. That is, when the phase difference between the fifth signal S5 and the sixth signal S6 is small, the time during which the transistor 4 is ON is long, and when the phase difference between the fifth signal S5 and the sixth signal S6 is large, the transistor The time during which 4 is ON is shortened. Thereby, the increase / decrease in the phase difference between the fifth signal S5 and the sixth signal S6 is replaced with the increase / decrease in the time during which the transistor 4 is in the ON state.

Note that the period in which both the fifth signal S5 and the sixth signal S6 are positive voltages greater than Vp occurs in the same cycle as the fifth signal S5 and the sixth signal S6, and therefore the period in which the transistor 4 is in the ON state is also included. It is generated in the same cycle as the fifth signal S5 and the sixth signal S6. Therefore, the drain voltage of the transistor 4 also includes the same frequency component as the fifth signal S5 and the sixth signal S6.

Then, the fundamental wave component (the same frequency component as the fifth signal S5 and the sixth signal S6) is extracted from the drain voltage of the transistor 4 by the output matching circuit 16, and is output from the terminal 2. This output signal has an amplitude that increases and decreases contrary to the increase and decrease of the phase difference between the fifth signal S5 and the sixth signal S6, and is an amplified signal obtained by synthesizing the fifth signal S5 and the sixth signal S6. . In this way, the power amplifier circuit functions as a power amplifier circuit that can amplify and output two constant envelope signals by vector addition.

Moreover, the voltage drop applied to the gate terminal of the transistor 4 that occurs when the phase difference between the fifth signal S5 and the sixth signal S6 is small can be reduced by the conversion circuit 31. Therefore, according to the power amplifier circuit of this example, it is possible to obtain a power amplifier circuit in which a decrease in amplification efficiency when the phase difference between the fifth signal S5 and the sixth signal S6 is large is reduced.

In this example, the sixth signal S6 is input to the gate terminal of the transistor 33 and the fifth signal S5 is input to the gate terminal of the transistor 34. However, the present invention is not limited to this. The signal input to the gate terminal of the transistor 33 may be a signal in phase with the sixth signal S6, and the signal input to the gate terminal of the transistor 34 may be a signal in phase with the fifth signal S5.

(Fourth example of embodiment)
FIG. 7 is a circuit diagram showing a power amplifier circuit according to a fourth example of the embodiment of the present invention. 7, in addition to the power amplifier circuit 61 shown in FIG. 6, the power amplifier circuit of this example is configured to convert an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal S5. And a constant envelope signal generation circuit 62 that converts the second constant envelope signal to be the sixth signal S6 and outputs the second constant envelope signal. The first constant envelope signal (fifth signal S5) and the second constant envelope signal (sixth signal S6) are constant envelope signals having the same frequency and amplitude and different phases. As the constant envelope signal generation circuit 62, various well-known constant envelope signal generation circuits can be used, and either a digital circuit or an analog circuit may be used.

According to the power amplifier circuit of this example having such a configuration, the first constant envelope signal and the second constant signal having a phase difference that increases or decreases the input signal having the envelope fluctuation in the opposite direction to the increase or decrease in the amplitude of the input signal. After being converted into an envelope signal, it can be amplified with high power supply efficiency, and an output signal having an amplified envelope variation can be output. Thereby, a power amplifier circuit with high power supply efficiency can be obtained.

(Fifth example of embodiment)
FIG. 8 is a block diagram showing a transmission apparatus according to a fifth example of the embodiment of the present invention. As shown in FIG. 8, the transmission apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, and an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70. Yes. According to the transmission apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a transmitter with low power consumption can be obtained.

(Sixth example of embodiment)
FIG. 9 is a block diagram showing a communication apparatus according to a sixth example of the embodiment of the present invention. As shown in FIG. 9, the communication apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70, and an antenna 82. And a receiving circuit 83 connected thereto. An antenna sharing circuit 84 is inserted between the antenna 82 and the power amplification circuit 70 and the reception circuit 83. That is, the power amplifying circuit 70 and the receiving circuit 83 are connected to the antenna 82 via the antenna sharing circuit 84. According to the communication apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a communication apparatus with low power consumption can be obtained. The antenna sharing circuit 84 is not always necessary and may be omitted.

First, the electrical characteristics in the power amplifier circuit of the first example of the embodiment of the present invention shown in FIG. 1 were calculated by circuit simulation. The transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V. The power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V. The input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.

The result of this simulation is shown by a solid line in the graph of FIG. In the graph, the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5). The vertical axis represents drain efficiency. Further, a simulation result of the power amplifier circuit of the comparative example in which the conversion circuit 31 is removed from the power amplifier circuit shown in FIG. 1 is shown by a broken line in the graph of FIG.

The graph shown in FIG. 10 shows that the power amplifier circuit of the present invention has higher drain efficiency than the power amplifier circuit of the comparative example. In particular, when the back-off is close to 0 (when the duty ratio of the input signal is large), the difference between the drain efficiency of the power amplifier circuit of the present invention and the drain efficiency of the power amplifier circuit of the comparative example may increase. Recognize.

Next, the electrical characteristics in the power amplifier circuit of the second example of the embodiment of the present invention shown in FIG. 5 were calculated by circuit simulation. The transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V. The power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V. The input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V. The capacitance of the capacitor 18 was 0.3 pF. The LC series resonance circuit 19 is composed of an inductor of 11.8 nH and a capacitor of 4.3 pF. The low-pass filter circuit 20 is composed of a π-type circuit composed of 3.9 pF and 3 pF capacitors and a 19.1 nH inductor.

The results of this simulation are shown in the graph of FIG. In the graph, the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5). The vertical axis represents drain efficiency.

According to the graph shown in FIG. 11, a power amplifier having an excellent characteristic in which the drain efficiency is as high as about 80% in a region where the duty ratio of the input signal is large and the back-off is 0 to -14 dB. It can be seen that it is.

(9) The effectiveness of the present invention was confirmed by these simulation results.

4, 33, 34:

Transistor

6, 18, 22: Capacitor 16: Output matching circuit 17, 20: Low-pass filter circuit 19: LC series resonance circuit 61, 70: Power amplifier circuit 62: Constant envelope signal generation circuit 81 : Transmitter circuit 82: Antenna 83: Receiver circuit

Claims

A capacitor that receives the first signal directly or with a different amplitude and outputs the second signal;
A conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal when the third signal or the first signal having the same duty ratio as the first signal is input;
A first transistor in which the second signal and the fourth signal are added and input to a gate terminal;
A first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential;
And an output matching circuit connected to a drain terminal of the first transistor.
The output matching circuit includes:
An LC series resonance circuit that is connected in series between the input and output and resonates at the frequency of the fundamental wave of the first signal;
A second low-pass filter circuit cascaded to the LC series resonance circuit for passing the fundamental frequency signal of the first signal and attenuating the harmonic frequency signal;
The power amplifier circuit according to claim 1, further comprising at least a capacitor connected between a drain terminal of the first transistor and a reference potential.
A second signal in which a fifth signal is input to the source terminal, a sixth signal or a signal in phase with the sixth signal is input to the gate terminal, and a signal to be the first signal is output from the drain terminal; ,
The sixth signal is input to the source terminal, the fifth signal or a signal having the same phase as the fifth signal is input to the gate terminal, and a signal serving as the third signal is output from the drain terminal. A transistor,
The power amplification circuit according to claim 1, wherein the third signal is input to the conversion circuit.
A constant envelope signal generation circuit that converts an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal and a second constant envelope signal that becomes the sixth signal, and outputs the converted signal; The power amplifier circuit according to claim 3, further comprising:
A transmission device comprising: a transmission circuit; the power amplification circuit according to claim 4; and an antenna connected to the transmission circuit via the power amplification circuit.
It has at least a transmission circuit, the power amplification circuit according to claim 4, an antenna connected to the transmission circuit via the power amplification circuit, and a reception circuit connected to the antenna. A communication device.