JP5213823B2 - POWER AMPLIFICATION SYNTHESIS CIRCUIT, POWER AMPLIFICATION CIRCUIT USING THE SAME, TRANSMITTER DEVICE AND COMMUNICATION DEVICE - Google Patents

Description

  The present invention relates to a power amplification / synthesis circuit, and a power amplification circuit, a transmission device, and a communication device using the same, and more particularly, a power amplification / synthesis circuit having high power efficiency and a power amplification circuit, a transmission device, and a communication using the same. It relates to the device.

  2. Description of the Related Art Conventionally, there is known a power amplification and synthesis circuit that amplifies a plurality of input signals and then combines them (see, for example, Patent Document 1).

Special Table 2005-512375

  However, the above-described conventional power amplification and synthesis circuit has a problem that the power supply efficiency is lowered when the phase difference between the two input signals is large.

  The present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplification and synthesis circuit with high power supply efficiency, a power amplification circuit using the same, a transmission device, and a communication device. It is to provide.

  The power amplification and synthesis circuit of the present invention includes a first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, and a gate terminal that is the first input terminal. A first transistor having a source terminal connected to the ground potential via a first constant current source, a gate terminal connected to the second input terminal, and a source terminal connected to the second input terminal. A second transistor connected to the ground potential through a constant current source of the first transistor, and a first low-frequency region having one end connected to the drain terminal of the first transistor and the other end connected to the power supply potential A pass filter circuit; a second low-pass filter circuit having one end connected to the drain terminal of the second transistor and the other end connected to a power supply potential; and one end connected to the first transistor Do An output matching circuit connected to an in terminal and a drain terminal of the second transistor and having the other end connected to an output terminal; and the first and second input signals are input; Current control for outputting a current control signal for controlling the first and second constant current sources so that the current flowing through the first and second constant current sources decreases as the phase difference of the second input signal increases. And a circuit.

  The power amplifier circuit according to the present invention includes a constant envelope signal generation circuit that converts an input signal having an envelope variation into first and second constant envelope signals and outputs the first and second constant envelope signals, and the first and second constant envelopes. And a power amplifying / synthesizing circuit configured as described above, wherein a signal is input to the first and second input terminals as the first and second input signals.

  The transmitter of the present invention is characterized in that an antenna is connected to the transmitter circuit via the power amplifier circuit having the above-described configuration.

  The communication apparatus of the present invention is characterized in that an antenna is connected to the transmission circuit via the power amplifier circuit having the above-described configuration, and a reception circuit is connected to the antenna.

  According to the power amplification and synthesis circuit of the present invention having the above-described configuration, the current flowing through the first and second constant current sources decreases as the phase difference between the first and second input signals increases. And a current control circuit for outputting a current control signal for controlling the first and second constant current sources, so that the phase difference between the first and second input signals is increased and the output from the power amplification and synthesis circuit Since power consumption when power is reduced can be reduced, a power amplification and synthesis circuit with high power efficiency can be obtained.

  According to the power amplifier circuit of the present invention having the above-described configuration, the input signal having the envelope variation is converted into the first and second constant envelope signals, amplified with high power supply efficiency, and then synthesized and output. Therefore, a power amplifier circuit with high power supply efficiency can be obtained.

  According to the transmission apparatus of the present invention having the above-described configuration, it is possible to amplify and transmit a transmission signal having an envelope variation from the transmission circuit with high power efficiency, so that a transmission apparatus with low power consumption can be obtained. it can.

  According to the communication device of the present invention having the above-described configuration, it is possible to amplify and transmit a transmission signal having an envelope variation from the transmission circuit with high power efficiency, and thus it is possible to obtain a communication device with low power consumption. it can.

It is a circuit diagram which shows the power amplification synthetic | combination circuit of the 1st example of embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a current control circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of an output matching circuit in FIG. 1. It is a circuit diagram which shows an example of the low-pass filter in FIG. It is a circuit diagram which shows the power amplification synthetic | combination circuit of the 2nd example of embodiment of this invention. It is a circuit diagram which shows the power amplifier circuit of the 3rd example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 4th example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 5th example of embodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power amplification and synthesis circuit of the present invention, a power amplification circuit using the same, a transmission device, and a communication device will be described in detail with reference to the accompanying drawings.
(First example of embodiment)
FIG. 1 is a circuit diagram showing a power amplification / synthesis circuit of the first example of the embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the current control circuit in FIG. FIG. 3 is a circuit diagram showing an example of the output load circuit in FIG. FIG. 4 is a circuit diagram showing an example of the low-pass filter circuit in FIG.

  As shown in FIG. 1, the power amplification and synthesis circuit of this example includes a first input terminal 1, a second input terminal 2, an output terminal 3, a first transistor 4, and a second transistor 5. The first constant current source 6, the second constant current source 7, the first low-pass filter circuit 8, the second low-pass filter circuit 11, the first capacitor 14, the second Capacitor 15, output matching circuit 16, and current control circuit 19.

  A first input signal is input to the first input terminal 1 from an external circuit (not shown), and a second input signal is input to the second input terminal 2 from an external circuit (not shown). In the power amplification and synthesis circuit of this example, assuming that both the first input signal and the second input signal are constant envelope signals, the first input signal is hereinafter referred to as the first constant envelope signal. S1, the second input signal will be referred to as a second constant envelope signal S2. The first transistor 4 has a gate terminal connected to the first input terminal 1 and a source terminal connected to the ground potential via a circuit in which the first constant current source 6 and the first capacitor 14 are connected in parallel. It is connected. The second transistor 5 has a gate terminal connected to the second input terminal 2 and a source terminal connected to the ground potential via a circuit in which a second constant current source 7 and a second capacitor 15 are connected in parallel. It is connected to the. The first low-pass filter circuit 8 has one end connected to the drain terminal of the first transistor 4 and the other end connected to the power supply potential Vdd. The transistors described in the embodiments of the present invention are all n-channel FETs, and the pinch-off voltage (threshold voltage for flowing a drain current) is Vp. The second low-pass filter circuit 11 has one end connected to the drain terminal of the second transistor 7 and the other end connected to the power supply potential Vdd. The output matching circuit 16 is connected to the drain terminal of the first transistor 4, the drain terminal of the second transistor 5, and the output terminal 3. The current control circuit is connected to the first input terminal 1 and the second input terminal 2, and the first constant current source 6 and the second constant current source 7, and the first and second input signals are inputted. And a current control signal for controlling the first and second constant current sources so that the current flowing through the first and second constant current sources decreases as the phase difference between the first and second input signals increases. Output.

  FIG. 2 shows a detailed circuit configuration of the current control circuit 19. The first constant envelope signal S1 and the second constant envelope signal S2 are input to the first input terminal 20 and the second input terminal 21 of the current control circuit, respectively. The first input terminal 20 and the second input terminal 21 are connected to the gate terminals of the third transistor 23 and the fourth transistor 24, respectively. Note that a bias circuit (not shown) is provided, and a DC bias voltage is supplied to the gate terminals of the third transistor 23 and the fourth transistor 24.

  The drain terminal of the third transistor 23 is connected to the power supply voltage Vdd, the source terminal of the third transistor 23 is connected to the drain terminal of the fourth transistor 24, and the source terminal of the fourth transistor 24 is the fifth terminal. The drain terminal of the transistor 26 and the source terminal of the fifth transistor 26 are connected to the ground. The drain terminal of the fifth transistor 26 is connected to the gate terminal and functions as a reference current side transistor of the current mirror circuit.

  Normally, when a positive voltage equal to or higher than the pinch-off voltage is applied to the gate terminal, the n-channel transistor conducts between the drain and source terminals. Therefore, when the first constant envelope signal S1 and the second constant envelope signal S2 are positive voltages, the third transistor 23 and the fourth transistor 24 are turned on. In this circuit configuration, since the third transistor 23 and the fourth transistor 24 form an AND circuit, the first constant envelope signal S1 and the second constant envelope signal S2 are both positive voltages. As a result, the power supply voltage Vdd appears at the drain terminal of the fifth transistor 26. Therefore, the time during which both the third transistor 23 and the fourth transistor 24 are in the ON state corresponds to the phase difference between the first constant envelope signal S1 and the second constant envelope signal S2. That is, when the phase difference between the two constant envelope signals is small, the time for both ON states is long, and when the phase difference is large, the time for both ON states is short. As a result, the phase difference between the two constant envelope signals S1 and S2 is replaced with the supply time of the power supply voltage Vdd to the drain terminal of the fifth transistor 26.

  The fifth transistor 26 is equivalent to a diode because the gate terminal and the drain terminal are connected. As a result, a voltage corresponding to the current flowing through the drain terminal is obtained at the gate terminal. As described above, since the power supply voltage Vdd is supplied to the drain of the fifth transistor 26 in accordance with the phase difference between the two constant envelope signals S1 and S2, the gate terminal of the fifth transistor 26 is connected to the drain terminal of the fifth transistor 26. A voltage corresponding to the phase difference between the two constant envelope signals is generated. The gate voltage of the fifth transistor 26 is supplied to the current value setting terminals (not shown) of the first and second constant current sources 6 and 7 through the output terminal 22 of the current control circuit 19, and the first and second constant current sources 26 and 7 are supplied. A constant current corresponding to the phase difference between the envelope signals S1 and S2 can be obtained.

  FIG. 3 shows a detailed circuit configuration of the output matching circuit 16. The output matching circuit 16 is set so that the impedance when the output terminal 3 is viewed from the drain terminals of the first transistor 4 and the second transistor 5 is matched with the fundamental wave. The drain terminal of the first transistor 4 is connected to the first input terminal 17 of the output matching circuit 16, and the drain terminal of the second transistor 5 is connected to the second input terminal 18 of the output matching circuit 16.

  A third capacitor 27 and a fourth capacitor 28 are connected to the first input terminal 17 and the second input terminal 18 for the purpose of blocking DC. The connection point is connected to the output terminal 3 via a series circuit of a first inductor 29 and a fifth capacitor 30 for impedance matching with a fundamental wave. The inductance value of the first inductor 29 and the capacitance value of the fifth capacitor 30 are usually selected so as to resonate in series at the fundamental frequency.

  FIG. 4 shows a detailed circuit configuration of the first and second low-pass filter circuits 8 and 11. The first low-pass filter circuit 8 and the second low-pass filter circuit 11 are for preventing outflow of high-frequency signals. The first signal terminal 10 is connected to the drain terminal of the first transistor 4 or the second transistor 5, and the second signal terminal 9 is connected to the power supply voltage Vdd. The second inductor 32 is connected in series between the first signal terminal 9 and the second signal terminal 10 of the first low-pass filter circuit 8, and one of the sixth capacitors 31 is connected to the second signal terminal 10. The other is connected to ground. According to the first and second low-pass filter circuits 8 and 11 having such a configuration, the operation of the second inductor 32 prevents the high-frequency signal from flowing into the power supply voltage Vdd side, which is unnecessary. A harmonic signal can be passed through the sixth capacitor to ground.

  It should be noted that the voltages of the first constant envelope signal S1 and the second constant envelope signal S2 are voltages sufficient for the transistor to saturate, and the inductance of the first inductor 29 in the output matching circuit 16 By appropriately selecting the value, the capacitance value of the fifth capacitor 30, and the capacitance value of the sixth capacitor 31 of the first low-pass filter circuit 8, a class E amplifier circuit can be obtained. The class E amplifier circuit operates as a high-efficiency amplifier circuit with low power consumption by switching amplification of the first transistor 4 and the second transistor 5.

  When the first constant envelope signal S1 is applied to the gate terminal of the first transistor 4, when the pinch-off voltage Vp of the first transistor 4 is exceeded, the transistor is turned on, and the drain-source connection is Conduct. At this time, a current flows from the power supply voltage Vdd into the first transistor 4 via the low-pass filter circuit 8. Of the current flowing into the first transistor 4, the high frequency component including the fundamental wave passes through the first capacitor 14, and the direct current component flows through the first constant current source 6.

  When the first constant current source 6 is not provided on the source side of the first transistor 4, the drain current of the first transistor 4 flows freely. At this time, the DC component can be considered as a bias current, and the high frequency Since it is not a fundamental component of electric power, it is a loss. For this reason, power supply efficiency (ratio of fundamental wave output power to power supplied from the constant voltage power supply Vdd) has been a factor. Therefore, the drain current is limited by the phase difference between the two constant envelope signals S1 and S2 by the first constant current source 6 so that an appropriate bias current flows.

  When the phase difference between the two constant envelope signals S1 and S2 is small, the control voltage from the current control circuit 19 is large and the first constant current source 6 is also set to a large current value. As a result, the bias current flowing through the first transistor 4 increases and the power supplied to the output matching circuit 16 also increases. On the other hand, when the phase difference between the two constant envelope signals S1 and S2 is large, the control voltage from the current control circuit 19 is small, and a small current value is set in the first constant current source 6. As a result, the bias current that can flow through the first transistor 4 is small, and the power supplied to the output matching circuit 16 is small.

  The same applies to the second transistor 5 as in the case of the first transistor 4. When the second constant current source 7 is not provided on the source side of the second transistor 5, the drain current of the second transistor 5 flows freely. The direct current component can be considered as a bias current, and is not a fundamental wave component of the high frequency power, so it becomes a loss. Therefore, power supply efficiency (ratio of fundamental wave output power to power supplied from constant voltage power supply Vdd) has been a factor. Therefore, the drain current is limited by the phase difference between the two constant envelope signals S1 and S2 by the second constant current source 7 so that an appropriate bias current flows.

  When the phase difference between the two constant envelope signals S1 and S2 is small, the control voltage from the current control circuit 19 is large, and the second constant current source 7 is also set to a large current value. As a result, the bias current flowing through the second transistor 5 increases and the power supplied to the output matching circuit 16 increases. On the other hand, when the phase difference between the two constant envelope signals S1 and S2 is large, the control voltage from the current control circuit 19 is small, and a small current value is set in the second constant current source 7. As a result, the bias current that can flow through the second transistor 5 is small, and the power supplied to the output matching circuit 16 is also small.

  In this way, when the phase difference between the two constant envelope signals S1 and S2 that are input is large and the output power is thereby reduced, the bias current included in the drain current of the transistor is limited to a small value, which is unnecessary. Power consumption can be improved while suppressing excessive power consumption. As a result, it is possible to realize a power amplification and synthesis circuit with high power supply efficiency that can combine power while amplifying the two constant envelope signals S1 and S2 with high efficiency.

(Second example of embodiment)
FIG. 5 is a circuit diagram showing a power amplification / synthesis circuit of the second example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

  The power amplification and synthesis circuit of this example includes a sixth transistor 33 and a seventh transistor 34 in addition to the power amplification and synthesis circuit of the first example of the embodiment of the present invention shown in FIG. The sixth transistor 33 and the seventh transistor 34 constitute a transfer gate circuit.

  The sixth transistor 33 is turned on only when the voltage of the second constant envelope signal S2 is larger than the pinch-off voltage Vp, and passes the first constant envelope signal S1. The seventh transistor 34 is turned on only when the voltage of the first constant envelope signal S1 is larger than the pinch-off voltage Vp, and passes the second constant envelope signal S2. As a result, the first and second transistors 4 and 5 are turned on only during a period in which both the first constant envelope signal S1 and the second constant envelope signal S2 are greater than the pinch-off voltage Vp.

  Therefore, the first constant envelope signal S1 is applied to the gate terminal of the first transistor 4 as it is, and the second constant envelope signal S2 is applied to the gate terminal of the second transistor 5 as it is. As a result, the period during which the first and second transistors 4 and 5 are in the ON state is shortened, so that power consumption is reduced and power supply efficiency (ratio of output power to power supplied from the constant voltage power supply Vdd) is improved. A highly efficient power amplifier circuit can be obtained.

  Note that the period in which both the first constant envelope signal S1 and the second constant envelope signal S2 are larger than Vp is generated at the fundamental wave period, so that the first transistor 4 and the second transistor 5 are in the ON state. This period also occurs at the fundamental wave period. Therefore, the drain voltages of the first transistor 4 and the second transistor 5 also include a fundamental wave component.

  Accordingly, the fundamental component is extracted from the drain voltages of the first transistor 4 and the second transistor 5 by the output matching circuit 16, and the combined signal of the first constant envelope signal S1 and the second constant envelope signal S2. Are output from the output terminal 3. This output signal has an amplitude that increases or decreases opposite to the increase or decrease of the phase difference between the first constant envelope signal S1 and the second constant envelope signal S2, that is, increases or decreases according to the increase or decrease of the amplitude of the input signal. The input signal is amplified.

  The output matching circuit 16 is viewed from the drain terminal of the first transistor 4 and the drain terminal of the second transistor 5 in accordance with the phase difference between the first constant envelope signal S1 and the second constant envelope signal S2. A more efficient power amplification and synthesis circuit can be obtained by changing the impedance. As elements for changing the impedance of the output matching circuit 16 viewed from the drain terminal of the first transistor 4 and the drain terminal of the second transistor 5, the first inductor 29 and the third capacitor shown in FIG. There is a sixth capacitor 31 shown.

  When the first constant envelope signal S1 and the second constant envelope signal S2 are in phase and have no phase difference, the series resonance circuit composed of the first inductor 29 and the third capacitor resonates at the fundamental frequency. To choose. For the sixth capacitor 31, a capacitance value based on the design theory of a known class E amplifier circuit is selected. As a result, the power from the constant voltage power supply Vdd converted into the high frequency power by the switching amplification of the first transistor 4 and the second transistor 5 is efficiently applied to a load circuit such as an antenna (not shown) via the output terminal 3. Can be supplied well.

  On the other hand, when the phase difference between the first constant envelope signal S1 and the second constant envelope signal S2 becomes large, the series resonant circuit composed of the first inductor 29 and the third capacitor is more fundamental than the fundamental frequency. Also select to resonate at a lower frequency. For the sixth capacitor 31, a value smaller than the capacitance value based on the known design theory of the class E amplifier circuit is selected. As a result, the impedance when the output matching circuit 16 is viewed from the drain terminals of the first transistor 4 and the second transistor 5 is increased, and the high-frequency signal is returned to the transistor side and passes through the output matching circuit 16 to the load circuit. Do not communicate to. Therefore, since the power from the constant voltage power supply Vdd converted into the high frequency power by the switching amplification of the first transistor 4 and the second transistor 5 is not supplied to the load circuit more than necessary, the output is particularly low. It can be operated with high efficiency even during power.

  As described above, it is possible to realize a high-efficiency power amplification and synthesis circuit that can combine power while amplifying the two constant envelope signals S1 and S2 with high efficiency.

(Third example of embodiment)
FIG. 6 is a circuit diagram showing a power amplifier circuit according to a third example of the embodiment of the present invention. As shown in FIG. 3, the power amplification and synthesis circuit of this example converts the input signal having the envelope variation into the first and second constant envelope signals by converting the power amplification and synthesis circuit 61 described above into a power amplification circuit. There are provided constant envelope signal generation circuits 62 for outputting to 61 first input terminal 1 and second input terminal 2 respectively.

  According to the power amplifier circuit of this example having such a configuration, the first and second constant envelope signals can be amplified and synthesized and output, so that an input signal having an envelope variation is Since it can be converted into the first and second constant envelope signals, amplified with high power efficiency and then combined and output, a power amplifier circuit with high power efficiency can be obtained.

(Fourth example of embodiment)
FIG. 7 is a block diagram showing a transmission apparatus according to a fourth example of the embodiment of the present invention.

  In the transmission apparatus of this example, as shown in FIG. 7, an antenna 82 is connected to a transmission circuit 81 via a power amplification circuit 70 shown in FIG. According to the transmission apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified and synthesized using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency. Therefore, it is possible to obtain a transmission apparatus with low power consumption and a long transmission time.

(Fifth example of embodiment)
FIG. 8 is a block diagram showing a communication apparatus according to a fifth example of the embodiment of the present invention.

  In the communication apparatus of this example, as shown in FIG. 8, an antenna 82 is connected to the transmission circuit 81 via the power amplification circuit 70 shown in FIG. 1, and a reception circuit 83 is connected to the antenna 82. An antenna sharing circuit 84 is inserted between the antenna 82 and the transmission circuit 81 and the reception circuit 83. According to the communication apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified and synthesized using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency. Therefore, it is possible to obtain a transmission apparatus with low power consumption and a long transmission time.

  Next, a specific example of the power amplifier circuit of the present invention will be described.

  The electric characteristics in the power amplification synthesis circuit of the second example of the embodiment of the present invention shown in FIG. 5 were calculated by circuit simulation. The first and second transistors 4 and 5 were gallium arsenide FETs, and the power supply voltage was 4.5V. The third, fourth, and fifth transistors 23, 24, and 26 in the current control circuit 19 are n-channel MOSFETs, the power supply voltage is 1.5 V, and the frequency of the input signal is 1 GHz. As a result, when two constant envelope signals S1 and S2 having a phase difference of about 40 ° are input, the power added efficiency of the power amplification and synthesis circuit to which the present invention is not applied was 89%. In the synthesis circuit, the power added efficiency was improved to 94%. This confirmed the effectiveness of the present invention.

1: First input terminal 2: Second input terminal 3: Output terminal 4: First transistor 5: Second transistor 6: First constant current source 7: Second constant current source 8: First Low pass filter circuit
11: Second low-pass filter circuit
16: Output matching circuit
19: Current control circuit
61: Power amplification synthesis circuit
62: Constant envelope signal generation circuit
70: Power amplifier circuit
81: Transmitter circuit
82: Antenna
83: Receiver circuit

Claims (4)

A first input terminal to which a first input signal is input;
A second input terminal to which a second input signal is input;
A first transistor having a gate terminal connected to the first input terminal and a source terminal connected to a ground potential via a first constant current source;
A second transistor having a gate terminal connected to the second input terminal and a source terminal connected to a ground potential via a second constant current source;
A first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential;
A second low-pass filter circuit having one end connected to the drain terminal of the second transistor and the other end connected to the power supply potential;
An output matching circuit having one end connected to the drain terminal of the first transistor and the drain terminal of the second transistor and the other end connected to the output terminal;
When the first and second input signals are input and the phase difference between the first and second input signals increases, the current flowing through the first and second constant current sources decreases. And a current control circuit that outputs a current control signal for controlling the second constant current source.   A constant envelope signal generation circuit for converting an input signal having an envelope variation into first and second constant envelope signals and outputting them, and the first and second constant envelope signals are the first and second constant envelope signals. A power amplification circuit comprising: the power amplification synthesis circuit according to claim 1 that is input to the first and second input terminals as an input signal.   An antenna is connected to the transmission circuit via the power amplifier circuit according to claim 2.   An antenna is connected to the transmitting circuit via the power amplifier circuit according to claim 2, and a receiving circuit is connected to the antenna.

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