WO2012077256A1 - Semiconductor device and method for manufacturing same - Google Patents
Semiconductor device and method for manufacturing same Download PDFInfo
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- WO2012077256A1 WO2012077256A1 PCT/JP2011/004078 JP2011004078W WO2012077256A1 WO 2012077256 A1 WO2012077256 A1 WO 2012077256A1 JP 2011004078 W JP2011004078 W JP 2011004078W WO 2012077256 A1 WO2012077256 A1 WO 2012077256A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 318
- 239000002184 metal Substances 0.000 claims abstract description 318
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 183
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 183
- 239000010703 silicon Substances 0.000 claims abstract description 183
- 230000004888 barrier function Effects 0.000 claims abstract description 58
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000005669 field effect Effects 0.000 claims description 35
- 229910052715 tantalum Inorganic materials 0.000 claims description 27
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 27
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 23
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- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- -1 tantalum magnesium nitride Chemical class 0.000 claims description 11
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- 239000007769 metal material Substances 0.000 claims description 6
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
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- 229910021334 nickel silicide Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 3
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- 239000011733 molybdenum Substances 0.000 claims description 3
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- 239000004332 silver Substances 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Definitions
- the present invention relates to a semiconductor device including a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, and a method for manufacturing the semiconductor device.
- a gate insulating film made of a high dielectric constant insulator In order to further reduce the thickness of the EOT, a metal electrode made of titanium nitride or tantalum nitride is sandwiched between a silicon electrode conventionally used as a gate electrode and a gate insulating film (Metal Inserted Poly- Many researches and developments have been made on silicon-stacked FET (MIPS FET) (see, for example, Patent Document 1). In this MIPS FET, since the metal electrode is formed on the lower side (gate insulating film side) of the silicon electrode, depletion of the silicon electrode can be suppressed, so that the performance of the transistor can be improved. .
- MIPS FET silicon-stacked FET
- a relatively thin metal electrode having a thickness of about 5 nm is formed under a silicon electrode having a relatively large thickness of 50 nm to 100 nm, which has been conventionally used as a gate electrode. It is realized by. Because it is easy to make the shape of the gate electrode, that is, the size and height of the gate electrode, the same as that of the conventionally used silicon electrode, it is a powerful gate for the generation of FETs smaller than 32 nm in the semiconductor manufacturing process. Research and development have been conducted as one of electrode structures (see, for example, Non-Patent Document 1).
- FIG. 7 shows a schematic cross-sectional configuration of a P-type FET having a conventional MIPS structure.
- An active region 302 surrounded by an element isolation region 301 is formed on a semiconductor substrate 300 made of silicon (Si) containing an N-type impurity such as an N well.
- a gate insulating film 305 made of, for example, a laminated film of a silicon oxide film 303 and a hafnium oxide film 304 is formed.
- a gate electrode 308 composed of a metal electrode 306 made of tantalum nitride (TaN) and a P-type silicon electrode 307 made of P-type polysilicon is formed.
- Side wall spacers 309 are formed on both side surfaces of the gate insulating film 305 and the gate electrode 308.
- a P-type extension region 310 is formed in a region above the N-type active region 302 and on both sides of the gate electrode 308, and further on both sides of the gate electrode 308 above the N-type active region 302.
- P-type source / drain regions 311 connected to the P-type extension regions 310 are formed in regions outside both sides of the P-type extension region 310, respectively.
- the interfacial resistance generated at the interface between the metal electrode 306 and the P-type silicon electrode 307 depends on the height of the Schottky barrier, which is the difference in work function of each constituent material.
- the work function of tantalum nitride is about 4.5 eV
- the work function of P-type polysilicon is about 5.1 eV. Therefore, the height of the Schottky barrier formed at the interface between the metal electrode 306 and the P-type silicon electrode 307 is a relatively large value of about 0.6 eV.
- FIG. 8 shows an energy band when the metal electrode 306 made of tantalum nitride and the P-type silicon electrode 307 are brought into contact with each other. Since the work function of P-type polysilicon (P-Si) is larger than the work function of tantalum nitride (TaN), when both are brought into contact, the energy band of P-type polysilicon bends downward. A depletion layer (a portion where the band is bent) is formed at the interface. As a result, an interface resistance is generated at the interface between the metal electrode 306 and the P-type silicon electrode 307.
- P-Si P-type polysilicon
- TaN tantalum nitride
- the P-type silicon electrode 307 is generally formed by ion-implanting a P-type impurity such as boron (B) into an undoped polysilicon film. Specifically, in order to prevent boron, which is an implanted ion, from penetrating into the semiconductor substrate 300, ion implantation is performed at a depth of 20 nm to 30 nm from the upper portion of the undoped polysilicon film, for example, from the upper surface, and the subsequent heat treatment is performed to polycrystal. A technique is adopted in which the entire silicon film is made into a P-type semiconductor.
- boron boron
- the P-type impurity concentration at the interface between the P-type silicon electrode 307 made of P-type polysilicon and the metal electrode 306, that is, at the lower part of the P-type silicon electrode 307 is smaller than that at the upper part.
- the P-type impurity concentration at the interface between the P-type silicon electrode 307 and the metal electrode 306 is 7 ⁇ 10 19 atoms / cm 3 and the Schottky barrier height is 0.6 eV
- the interface resistance Is about 2 ⁇ 10 ⁇ 6 ⁇ cm 2 . This value is extremely large with respect to a value of 1 ⁇ 10 ⁇ 7 ⁇ cm 2 or less, which is generally desired in the 32 nm generation in the semiconductor manufacturing process.
- the reduction of the interface resistance can be realized by increasing the P-type impurity concentration below the P-type silicon electrode 307, but from the viewpoint of preventing the penetration of implanted ions into the substrate, the above-described P-type impurities are also included. Since the concentration of 7 ⁇ 10 19 atoms / cm 3 is close to the impurity solubility limit of 2 ⁇ 10 20 atoms / cm 3 (after activation annealing at 1050 ° C.), the P-type impurity concentration is increased. It is extremely difficult to greatly reduce the interfacial resistance by the technique of making it happen.
- the present invention solves the above-described problem and realizes a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode.
- the object is to reduce the interfacial resistance generated at the interface.
- the present invention provides a metal layer (upper metal layer) capable of reducing the interface resistance generated at the interface between the metal electrode and the silicon electrode between the metal electrode and the silicon electrode in the semiconductor device. Electrode).
- a semiconductor device includes a first conductivity type first field effect transistor formed in a first active region of a semiconductor substrate, and the first field effect transistor includes: And a first gate electrode formed on the first gate insulating film, wherein the first gate electrode is a first gate electrode.
- a first lower layer metal electrode formed on the insulating film, a first upper layer metal electrode formed on the first lower layer metal electrode, and formed on the first upper layer metal electrode A metal or a metal compound constituting the first upper metal electrode and a metal or metal compound constituting the first upper metal electrode and silicon constituting the first silicon electrode.
- the height of the first Schottky barrier formed between It has a work function smaller than the height of the second Schottky barrier formed when the metal or metal compound constituting the metal electrode and the silicon constituting the first silicon electrode are brought into direct contact with each other. .
- the first gate electrode has the first upper layer metal electrode formed between the first lower layer metal electrode and the first silicon electrode, and
- the metal or metal compound constituting one upper metal electrode is a first Schottky barrier formed between the metal or metal compound constituting the first upper metal electrode and the silicon constituting the first silicon electrode. Is higher than the height of the second Schottky barrier formed when the metal or metal compound constituting the first lower metal electrode and the silicon constituting the first silicon electrode are brought into direct contact with each other. Has a smaller work function. For this reason, since the height of the Schottky barrier between the first upper metal electrode and the first silicon electrode is reduced, the interface resistance in the first gate electrode can be reduced.
- the height of the first Schottky barrier is preferably less than 0.4 eV.
- the height of the second Schottky barrier may be 0.4 eV or more.
- the film thickness of the first upper metal electrode may be not less than 1.5 nm and not more than 15 nm.
- the first field effect transistor is an N-type transistor
- the work function of the metal or metal compound constituting the first upper metal electrode is the metal constituting the first lower metal electrode. Or it is preferable that it is smaller than the work function of a metal compound.
- the first silicon electrode is made of N-type silicon
- the first upper metal electrode is tantalum carbide, tantalum magnesium nitride, titanium, titanium magnesium magnesium, titanium aluminum, titanium aluminum nitride, tungsten silicide.
- Aluminum, tantalum, silver, molybdenum, lanthanum, hafnium, zirconium or manganese can be used.
- the first field effect transistor is a P-type transistor, and the work function of the metal or metal compound constituting the first upper metal electrode constitutes the first lower metal electrode. It is preferable that it is larger than the work function of the metal or metal compound.
- the first silicon electrode is made of P-type silicon
- the first upper metal electrode includes tantalum carbonitride oxide, tantalum carbonitride, titanium nitride, tungsten platinum silicide, tantalum carbide oxide, platinum silicide.
- Tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold, or tungsten can be used.
- the semiconductor device of the present invention further includes a second conductivity type second field effect transistor formed in the second active region of the semiconductor substrate, and the second field effect transistor includes the second active region.
- the metal or metal compound constituting the second upper metal electrode is formed between the metal or metal compound constituting the second upper metal electrode and the silicon constituting the second silicon electrode.
- the height of the third Schottky barrier is Having a work function that is smaller than the height of the fourth Schottky barrier formed when the metal or metal compound that constitutes the silicon and the silicon that constitutes the second silicon electrode are brought into direct contact with each other. preferable.
- the complementary MISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) having the MIPS structure is composed of the first field effect transistor and the second field effect transistor having different conductivity types. Interfacial resistance with the silicon electrode can be reduced.
- the height of the third Schottky barrier is preferably less than 0.4 eV.
- the height of the fourth Schottky barrier may be 0.4 eV or more.
- the thickness of the second upper metal electrode may be 1.5 nm or more and 15 nm or less.
- the second field-effect transistor is a P-type transistor
- the work function of the metal or metal compound constituting the second upper metal electrode Is preferably larger than the work function of the metal or metal compound constituting the second lower layer metal electrode.
- the second silicon electrode is made of P-type silicon
- the second upper metal electrode includes tantalum carbonitride oxide, tantalum carbonitride, nitridation. Titanium, tungsten platinum silicide, tantalum carbide oxide, platinum silicide, tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold, or tungsten can be used.
- the semiconductor device of the present invention includes the second field effect transistor
- the first lower metal electrode and the second lower metal electrode may be made of the same metal material.
- the semiconductor device of the present invention further includes a second conductivity type second field effect transistor formed in the second active region of the semiconductor substrate, and the second field effect transistor includes the second active effect transistor.
- the metal electrode is made of the same metal material, and the height of the fifth Schottky barrier formed between the metal or metal compound constituting the second lower metal electrode and the silicon constituting the second silicon electrode.
- the thickness is preferably less than 0.4 eV.
- the metal electrode and the silicon electrode in the complementary MISFET having the MIPS structure can be reduced.
- the work function of the metal or metal compound constituting the first upper metal electrode constitutes the first silicon electrode and the work function of the metal or metal compound constituting the first lower metal electrode. It may be located between the work function of silicon.
- the method for manufacturing a semiconductor device includes a step (a) of forming a gate insulating film on a first active region in a semiconductor substrate, and a step (b) of forming a gate electrode on the gate insulating film.
- the gate electrode comprises: a lower metal electrode formed on the gate insulating film; an upper metal electrode formed on the lower metal electrode; and a silicon electrode formed on the upper metal electrode.
- the metal or metal compound constituting the upper metal electrode has a height of the first Schottky barrier formed between the metal or metal compound constituting the upper metal electrode and the silicon constituting the silicon electrode, It has a work function smaller than the height of the second Schottky barrier formed when the metal or metal compound constituting the lower metal electrode and the silicon constituting the silicon electrode are brought into direct contact with each other. .
- the gate electrode includes a lower layer metal electrode formed on the gate insulating film, an upper layer metal electrode formed on the lower layer metal electrode, and an upper layer metal electrode. Further, the metal or metal compound constituting the upper metal electrode is formed between the metal or metal compound constituting the upper metal electrode and the silicon constituting the silicon electrode.
- the height of the first Schottky barrier is higher than the height of the second Schottky barrier formed when the metal or metal compound constituting the lower metal electrode and the silicon constituting the silicon electrode are brought into direct contact with each other. Has a smaller work function. For this reason, since the height of the Schottky barrier between the upper metal electrode and the silicon electrode is reduced, the interface resistance in the gate electrode can be reduced.
- the semiconductor device and the manufacturing method thereof according to the present invention when realizing a field effect transistor having a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, impurities in the silicon electrode Even when the concentration is low enough to be easily realized, the interface resistance generated at the interface between the metal electrode and the silicon electrode can be reduced. As a result, it is possible to prevent the deterioration of the AC characteristics of the semiconductor integrated circuit.
- FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an energy band between the upper metal electrode and the silicon electrode in the semiconductor device according to the embodiment of the present invention.
- FIG. 3A to FIG. 3C are schematic cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- 4A to 4C are schematic cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 5A to FIG. 5C are schematic cross-sectional views showing the method of manufacturing a semiconductor device according to one embodiment of the present invention.
- FIG. 6C are schematic cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 7 is a schematic cross-sectional view showing a semiconductor device having a conventional MIPS structure.
- FIG. 8 is a diagram showing an energy band between a metal electrode and a silicon electrode in a semiconductor device having a conventional MIPS structure.
- the semiconductor device includes, for example, a P-type FET region 10 and an N-type FET region 20 formed in a semiconductor substrate 100 made of P-type silicon (Si). .
- An N well region 101a and an N type active region 103a surrounded by an element isolation region 102 in the N well region 101a are formed in the P type FET region 10 on the semiconductor substrate 100.
- a P well region 101b and a P type active region 103b surrounded by the element isolation region 102 in the P well region 101b are formed in the N type FET region 20 in the upper portion of the semiconductor substrate 100.
- a P-type field effect transistor (FET) formed in the P-type FET region 10 of the semiconductor substrate 100 includes a lower metal electrode 107a formed on the N-type active region 103a with a gate insulating film 106a interposed therebetween, An upper metal electrode 108a formed on the lower metal electrode 107a, a P-type silicon electrode 109a formed on the upper metal electrode 108a, and both side surfaces from the gate insulating film 106a to the P-type silicon electrode 109a Side wall spacer 110a formed, P-type extension region 111a formed on both sides of P-type silicon electrode 109a above N-type active region 103a, and P-type extension region above N-type active region 103a P-type source / drain region 112a formed in a region outside 111a There.
- the P-type source / drain region 112a contains a higher concentration of P-type impurities than the P-type extension region 111a.
- the lower metal electrode 107a, the upper metal electrode 108a, and the P-type silicon electrode 109a are collectively referred to as a gate electrode 113a.
- the gate insulating film 106a is, for example, a base insulating film 104a made of silicon oxide having a thickness of 1 nm and a high dielectric constant insulator such as hafnium oxide having a thickness of 2 nm formed on the base insulating film 104a. And a high dielectric constant insulating film 105a made of a metal oxide.
- the high dielectric constant insulator refers to a substance having a dielectric constant higher than that of silicon nitride (SiN) (for example, an insulator having a relative dielectric constant of 8 or more).
- the gate electrode 113a includes a lower metal electrode 107a made of a metal or a conductive metal compound formed on the gate insulating film 106a, and a tantalum carbonitride oxide (TaCNO) formed on the lower metal electrode 107a. ) And a P-type silicon electrode 109a made of P-type polysilicon or the like formed on the upper metal electrode 108a.
- the lower metal electrode 107a is made of tantalum nitride (TaN) having a film thickness of 5 nm.
- the film thickness of the upper metal electrode 108a is 2 nm.
- the film thickness of the P-type silicon electrode 109a formed on the upper metal electrode 108a is 100 nm.
- the impurity concentration of P-type impurities made of, for example, boron (B) at the lower portion of the P-type silicon electrode 109a, that is, at the interface with the upper metal electrode 108a is about 7 ⁇ 10 19 atoms / cm 3 .
- the gate length of the gate electrode 113a is about 40 nm, and the width of the sidewall spacer 110a is about 40 nm.
- the P-type extension region 111a is located below the sidewall spacer 110a in the upper part of the N-type active region 103a, and is provided so as to overlap each end of the gate electrode 113a on the gate length direction side in plan view. Further, the P-type extension region 111a is doped with a P-type impurity such as boron (B), and the maximum value of the impurity concentration is about 2 ⁇ 10 20 atoms / cm 3 .
- the junction depth of the P-type extension region 111a that is, the depth of the PN junction surface formed with the N-type active region 103a from the lower surface of the sidewall spacer 110a (the surface of the semiconductor substrate 100) is about 20 nm. .
- an N-type impurity such as arsenic (As) or phosphorus (P) so as to cover the P-type extension region 111a from below and from the side in the N-type active region 103a of the semiconductor substrate 100.
- a well-known pocket region doped with (for example, N-type impurity concentration is about 3 ⁇ 10 18 atoms / cm 3 ) may be formed.
- the P-type source / drain region 112a is formed in a region outside the P-type extension region 111a with respect to the gate electrode 113a above the N-type active region 103a and connected to the P-type extension region 111a.
- the P-type source / drain region 112a is doped with a P-type impurity such as boron (B), and the maximum value of the impurity concentration is about 1 ⁇ 10 21 atoms / cm 3 .
- the junction depth of the P-type source / drain region 112a that is, the depth from the surface of the semiconductor substrate 100 of the PN junction surface formed with the N-type active region 103a is about 80 nm.
- a portion of the N-type active region 103a located below the gate electrode 113a is doped with N-type impurities for forming the N-well region 101a and controlling the threshold voltage.
- the N-type impurity is arsenic (As), phosphorus (P), or the like, and the impurity concentration is about 1 ⁇ 10 17 atoms / cm 3 .
- an N-type field effect transistor (FET) formed in the N-type FET region 20 of the semiconductor substrate 100 includes a lower metal electrode 107b formed on the P-type active region 103b with a gate insulating film 106b interposed therebetween.
- the N-type source / drain region 112b contains a higher concentration of N-type impurities than the N-type extension region 111b.
- the lower metal electrode 107b, the upper metal electrode 108b, and the N-type silicon electrode 109b are collectively referred to as a gate electrode 113b.
- the gate insulating film 106b is, for example, a base insulating film 104b made of silicon oxide having a thickness of 1 nm, and a high dielectric constant insulating film 105b made of hafnium oxide having a thickness of 2 nm, for example, formed on the base insulating film 104b. It is composed of
- the gate electrode 113b is made of, for example, tantalum carbide (TaC) formed on the lower metal electrode 107b and a lower metal electrode 107b made of a metal or a conductive metal compound formed on the gate insulating film 106b. And an N-type silicon electrode 109b made of N-type polysilicon or the like formed on the upper-layer metal electrode 108b.
- TaC tantalum carbide
- the lower metal electrode 107b is made of tantalum nitride (TaN) having a film thickness of 5 nm.
- the film thickness of the upper metal electrode 108b is 2 nm.
- the film thickness of the N-type silicon electrode 109b formed on the upper metal electrode 108b is 100 nm.
- the impurity concentration of an N-type impurity made of, for example, phosphorus (P) at the lower portion of the N-type silicon electrode 109b, that is, at the interface with the upper metal electrode 108b is about 7 ⁇ 10 19 atoms / cm 3 .
- the gate length of the gate electrode 113b is about 40 nm, and the width of the sidewall spacer 110b is about 40 nm.
- the N-type extension region 111b is located below the sidewall spacer 110b above the P-type active region 103b, and is provided so as to overlap each end of the gate electrode 113b on the gate length direction side in plan view. Further, the N-type extension region 111b is doped with an N-type impurity such as arsenic (As), and the maximum value of the impurity concentration is about 2 ⁇ 10 20 atoms / cm 3 .
- the junction depth of the N-type extension region 111b that is, the depth of the PN junction surface formed with the P-type active region 103b from the lower surface of the sidewall spacer 110b (the surface of the semiconductor substrate 100) is about 20 nm. .
- a P-type impurity such as boron (B) or indium (In) so as to cover the N-type extension region 111b from below and from the side in the P-type active region 103b of the semiconductor substrate 100.
- a well-known pocket region doped with (for example, the P-type impurity concentration is about 3 ⁇ 10 18 atoms / cm 3 ) may be formed.
- the N-type source / drain region 112b is formed in a region outside the N-type extension region 111b with respect to the gate electrode 113b above the P-type active region 103b and connected to the N-type extension region 111b.
- the N-type source / drain region 112b is doped with N-type impurities such as arsenic (As) or phosphorus (P), and the maximum value of the impurity concentration is about 1 ⁇ 10 21 atoms / cm 3 .
- the junction depth of the N-type source / drain region 112b that is, the depth of the PN junction surface formed with the P-type active region 103b from the surface of the semiconductor substrate 100 is about 80 nm.
- a portion of the P-type active region 103b located below the gate electrode 113b is doped with a P-type impurity for forming the P well region 101b and controlling the threshold voltage.
- the P-type impurity is boron, indium or the like, and the impurity concentration is about 1 ⁇ 10 17 atoms / cm 3 .
- FIG. 2 shows an energy band diagram in a direction perpendicular to the substrate surface of the gate electrode constituting the P-type FET shown in FIG.
- a lower metal electrode made of tantalum nitride (TaN) having a work function of 4.5 eV and a P-type silicon electrode made of P-type polysilicon having a work function of 5.1 eV are brought into direct contact with each other.
- the P-type FET according to the present embodiment has a work function at the interface between the lower metal electrode 107a made of tantalum nitride (TaN) and the P-type silicon electrode 109a made of P-type polysilicon in the gate electrode 113a.
- interfaces are formed in the gate electrode 113a at two locations, that is, the interface between the lower metal electrode 107a and the upper metal electrode 108a and the interface between the upper metal electrode 108 and the P-type silicon electrode 109a.
- the interface between the lower metal electrode 107a and the upper metal electrode 108a is both made of metal (metal compound), the interface resistance is extremely small.
- the height of the Schottky barrier is reduced to about 0.2 eV at the interface between the upper metal electrode 108a and the P-type silicon electrode 109a made of P-type polysilicon.
- the bending of the energy band in the silicon electrode 109a is reduced. That is, the work function is 4. between the lower metal electrode 107a made of a metal or metal compound having a work function of about 4.5 eV and the P-type silicon electrode 109a made of P-type polysilicon having a work function of about 5.1 eV.
- the height of the Schottky barrier can be reduced from about 0.6 eV to about 0.2 eV.
- the interfacial resistance due to the Schottky barrier is extremely small, 1 ⁇ 10 ⁇ 7 ⁇ cm 2 or less.
- the upper metal electrode 108a having a work function larger than that of the lower metal electrode 107a is formed between the metal electrode 107a having the conventional structure and the P-type silicon electrode 109a made of P-type polysilicon.
- the interface resistance generated inside the gate electrode 113a can be reduced. Therefore, it is possible to suppress the deterioration of the AC characteristics of the semiconductor integrated circuit including the P-type FET.
- the interface resistance generated at the interface between the lower metal electrode 107b and the N-type silicon electrode 109b made of N-type polysilicon can be reduced by the same mechanism as that of the P-type FET. Therefore, it is possible to suppress the deterioration of the AC characteristics of the semiconductor integrated circuit.
- the bending direction of the energy band forming the Schottky barrier is bent upward as opposed to the case of the P-type FET, so that the work function of the upper metal electrode 108b formed on the lower metal electrode 107b Needs to be smaller than the lower metal electrode 107b.
- tantalum carbide having a work function of about 4.2 eV between a metal electrode 107b having a work function of about 4.5 eV and an N-type silicon electrode 109b made of N-type polysilicon having a work function of about 4.1 eV.
- the upper metal electrode 108b made of (TaCx)
- the Schottky barrier height can be reduced from about 0.4 eV to about 0.1 eV.
- the interface resistance generated inside the gate electrode 113b can be reduced.
- the semiconductor device includes the lower layer metal electrode 107a and the P-type silicon electrode 109a thereon, and the lower layer metal electrode 107b and the upper N-type silicon electrode 109b at each interface.
- the upper metal electrodes 108a and 108b are formed to reduce the height of the Schottky barrier generated when the 107a and 107b and the silicon electrodes 109a and 109b are in contact with each other. As a result, the interface resistance formed inside each gate electrode 113a, 113b can be reduced, so that the deterioration of the AC characteristics of the semiconductor integrated circuit including the P-type FET and the N-type FET can be suppressed.
- the upper metal electrodes 108a and 108b The constituent materials are not limited to these. That is, by forming the upper metal electrodes 108a and 108b at the interface between the lower metal electrode 107a and the P-type silicon electrode 109a and the interface between the lower metal electrode 107b and the N-type silicon electrode 109b, respectively, the gate electrode 113a and the gate electrode Any height can be selected as long as the height of the Schottky barrier formed inside 113b can be reduced.
- the height of the Schottky barrier between the upper metal electrode 108a and the P-type silicon electrode 109a is preferably less than 0.4 eV from the viewpoint of reducing the interface resistance.
- the work function (4) located between the work function (about 4.5 eV) of the lower metal electrode 107a and the work function (about 5.1 eV) of the P-type silicon electrode 109a is preferably used as the upper metal electrode 108a.
- tantalum carbonitride oxide having about 0.9 eV
- the work function is higher than that of the P-type silicon electrode 109a (about 5.1 eV)
- Any material can be used as long as the height of the Schottky barrier between them can be less than 0.4 eV (for example, a material having a work function of 5.3 eV).
- tantalum carbonitride oxide TaCNO
- tantalum carbonitride TaCN
- titanium nitride TiN
- tungsten platinum silicide WPtSi
- tantalum carbide oxide TaCO
- Platinum silicide PtSi
- tungsten nitride WNx
- nickel silicide NiSi
- MoxN molybdenum nitride
- platinum (Pt) nickel (Ni), palladium (Pd), gold (Au) or tungsten (W) Etc.
- the height of the Schottky barrier between the upper metal electrode 108b and the N-type silicon electrode 109b is preferably less than 0.4 eV from the viewpoint of reducing the interface resistance.
- the work function (4) located between the work function (about 4.5 eV) of the lower metal electrode 107b and the work function (about 4.1 eV) of the N-type silicon electrode 109b has been described.
- any material that can make the height of the Schottky barrier less than 0.4 eV for example, a material having a work function of 3.9 eV may be used.
- tantalum magnesium nitride Ti
- titanium Ti
- titanium magnesium nitride TiMgN
- titanium aluminum TiAl
- titanium aluminum nitride as the constituent material of the upper metal electrode 108b (TiAlN)
- tungsten silicide WSi
- aluminum Al
- tantalum Ta
- silver Ag
- molybdenum Mo
- lanthanum La
- hafnium Hf
- Zr zirconium
- manganese Mn
- the preferable film thickness of the upper metal electrodes 108a and 108b is as follows. These lower limit film thicknesses are such that the height of the Schottky barrier formed at the interface between the upper metal electrodes 108a and 108b and the P-type silicon electrode 109a and the N-type silicon electrode 109b formed thereon, respectively, It must be thick enough not to be affected by the lower layer metal electrodes 107a and 107b formed under the electrodes 108a and 108b, and preferably 1.5 nm or more.
- the upper limit metal thickness of the upper metal electrodes 108a and 108b is desirably thin enough not to improve the difficulty in gate processing, and is desirably 15 nm or less. That is, it is desirable that the film thickness of the upper metal electrodes 108a and 108b is 1.5 nm or more and 15 nm or less.
- each lower layer metal electrode 107a, 107b is not limited to tantalum nitride (TaN).
- TaN tantalum nitride
- the present invention reduces the height of the Schottky barrier generated when the lower metal electrodes 107a and 107b are brought into contact with the P-type silicon electrode 109a and the N-type silicon electrode 109b, respectively, In order to reduce the interface resistance, the upper metal electrodes 108a and 108b are provided at the interface between them.
- a material having a relationship that the work function of the metal or metal compound constituting the lower layer metal electrode 107a is smaller than the work function of P type polysilicon constituting the P type silicon electrode 109a is used as the lower layer metal.
- the present invention is effective when used for the electrode 107a.
- a material having a relationship that the work function of the metal or metal compound constituting the lower metal electrode 107b is larger than the work function of the N-type polysilicon constituting the N-type silicon electrode 109b is used as the lower layer.
- the present invention is effective when used for the metal electrode 107b.
- the present invention when the difference in work function between the lower layer metal electrodes 107a and 107b and the respective silicon electrodes 109a and 109b thereon, that is, the height of the Schottky barrier is 0.4 eV or more, the present invention is more effective. It is effective.
- each lower layer metal electrode 107a, 107b is 1.5 nm or more in order to suppress characteristic variation such as threshold voltage (Vt) variation due to upper layer metal electrodes 108a, 108b formed thereon. It is desirable to be.
- the lower layer metal electrodes 107a and 107b do not have to be a single layer as described above, and may have a laminated structure.
- the uppermost metal material in the stacked structure determines the interface resistance between the P-type silicon electrode 109a and the N-type silicon electrode 109b, the height of the Schottky barrier between the uppermost metal material and the silicon electrode is set.
- the upper metal electrodes 108a and 108b made of a material to be reduced may be selected.
- the lower metal electrodes 107a and 107b formed on the gate insulating films 106a and 106b are made of the same material.
- the impurity concentrations at the lower part of the P-type silicon electrode 109a and the lower part of the N-type silicon electrode 109b are not limited to the above example.
- the value of the interface resistance between silicon and metal is determined by the combination of the height of the Schottky barrier and the impurity concentration. Therefore, the impurity concentration may be small if the height of the Schottky barrier can be reduced. Conversely, if the height of the Schottky barrier cannot be made sufficiently small, it is desirable to increase the impurity concentration as much as possible.
- the present invention is effective when the impurity concentration in the lower part of the P-type silicon electrode 109a and the lower part of the N-type silicon electrode 109b is 1 ⁇ 10 19 atoms / cm 3 or more and 2 ⁇ 10 20 atoms / cm 3 or less. It is.
- polysilicon containing germanium (Ge) that can improve the solid solution limit of impurities such as boron (B), that is, polysilicon germanium can be used.
- the P-type FET is provided with the upper metal electrode 108a on the gate electrode 113a
- the N-type FET is provided with the upper metal electrode 108b on the gate electrode 113b.
- 108a and 108b are not necessarily provided in both FETs.
- a material having a relatively large work function such as tungsten (W) having a work function of about 4.9 eV
- the lower layer metal electrodes 107a and P in the P-type FET are used.
- the height of the Schottky barrier formed by the type silicon electrode 109a is as small as about 0.2 eV.
- the upper metal electrode 108a is not necessarily provided for the P-type FET. That is, in the P-type FET, if the height of the Schottky barrier between the metal or metal compound constituting the lower metal electrode 107a and the P-type polysilicon constituting the P-type silicon electrode 109a is less than 0.4 eV. It is not necessary to provide the upper metal electrode 108a.
- the upper layer metal electrode 108a is provided only for the P-type FET.
- the interface resistance can be effectively reduced. That is, in the N-type FET, if the height of the Schottky barrier between the metal or metal compound constituting the lower metal electrode 107b and the N-type polysilicon constituting the N-type silicon electrode 109b is less than 0.4 eV. It is not necessary to provide the upper metal electrode 108b.
- a shallow trench isolation (STI) method or the like is used to form an upper portion of a semiconductor substrate 100 made of silicon (Si) containing P-type impurities such as boron (B).
- the element isolation region 102 that partitions the P-type FET region 10 and the N-type FET region 20 is selectively formed.
- an N well region 101a and a P well region 101b are formed in the P type FET region 10 and the N type FET region 20, respectively.
- an impurity for adjusting the threshold voltage is doped into the N well region 101a and the P well region 101b, respectively, so that the impurity concentration suitable for the P type FET and the N type FET is 1 ⁇ 10 17 atoms /
- An N-type active region 103 a and a P-type active region 103 b of about cm 3 are formed in a region surrounded by the element isolation region 102.
- a silicon oxide film 104 with a thickness of 1 nm and a hafnium oxide film 105 with a thickness of 2 nm for forming a gate insulating film are formed on the active regions 103a and 103b.
- a thermal oxidation method can be used to form the silicon oxide film 104
- a chemical vapor deposition (CVD) method can be used to form the hafnium oxide film 105, for example.
- CVD chemical vapor deposition
- a tantalum nitride (TaN) film 107 having a thickness of 5 nm for forming a lower metal electrode is deposited on the hafnium oxide film 105.
- a silicon film 201 having a thickness of 3 nm, which is used as a hard mask in a later process is deposited.
- a first resist pattern 202 having an opening pattern in the N-type FET region 20 is formed on the semiconductor substrate 100 by lithography. Thereafter, the silicon film 201 formed in the N-type FET region 20 is removed using the first resist pattern 202 as a mask. Specifically, the silicon film 201 is removed with a tetramethylammonium hydroxide (Tetra Methyl Ammonium Hydroxide: TMAH) solution. As a result, the tantalum nitride film 107 is exposed from the silicon film 201 in the N-type FET region 20. Thereafter, the first resist pattern 202 is removed.
- TMAH tetramethylammonium hydroxide
- a tantalum carbide (TaCx) film 108B having a film thickness of 2 nm and a silicon film 203 having a film thickness of 3 nm to be used as a hard mask in the subsequent process are sequentially deposited on the upper metal electrode of the N-type FET.
- a second resist pattern 204 having an opening pattern in the P-type FET region 10 is formed on the semiconductor substrate 100 by lithography.
- the silicon film 203, the tantalum carbide film 108B, and the silicon film 201 formed in the P-type FET region 10 are sequentially removed using the second resist pattern 204 as a mask.
- the silicon film 203 is removed with a TMAH solution
- the tantalum carbide film 108B is removed with an ammonia water hydrogen peroxide solution mixture (APM).
- APM ammonia water hydrogen peroxide solution mixture
- the silicon film 201 is removed with a TMAH solution.
- the tantalum nitride film 107 is exposed from the silicon film 203 and the tantalum carbide film 108B in the P-type FET region 10.
- an organic resist material is used for the second resist pattern 204, it is removed during the APM treatment, and therefore it is desirable to use an inorganic resist material.
- the entire surface of the semiconductor substrate 100 that is, the tantalum nitride film 107 in the P-type FET region 10 is formed.
- a tantalum carbon oxynitride (TaCNO) film 108A having a film thickness of 2 nm is deposited on the silicon film 203 to serve as the upper metal electrode of the P-type FET.
- a third resist pattern 205 having an opening pattern in the N-type FET region 20 is formed on the semiconductor substrate 100 by lithography. Thereafter, using the third resist pattern 205 as a mask, the tantalum carbonitride oxide film 108A and the silicon film 203 formed in the N-type FET region 20 are sequentially removed. Specifically, the tantalum carbonitride oxide film 108A is removed by APM, and then the silicon film 203 is removed by a TMAH solution. As a result, in the N-type FET region 20, the tantalum carbide film 108B is exposed from the tantalum carbonitride oxide film 108A and the silicon film 203.
- an organic resist material is used for the third resist pattern 205, it is removed during the APM treatment, and therefore it is desirable to use an inorganic resist material.
- the entire surface of the semiconductor substrate 100 that is, in the P-type FET region 10, over the tantalum carbonitride oxide film 108A.
- a polysilicon film 109 for forming a silicon electrode and having a film thickness of 100 nm and not doped with impurities is deposited on the tantalum carbide film 108B. Note that although an undoped polysilicon film is used as the polysilicon film 109, a polysilicon germanium film may be used.
- the N-type FET region 20 is masked with a fourth resist pattern (not shown), and boron (B) is added to the P-type FET region 10 of the polysilicon film 109.
- boron B
- the polysilicon film 109 in the P-type FET region 10 is changed to a P-type polysilicon film 109A.
- the P-type FET region 10 is masked with a fifth resist pattern (not shown), and phosphorus (P) is added to the N-type FET region 20 of the polysilicon film 109.
- P phosphorus
- the polysilicon film 109 in the N-type FET region 20 is changed to an N-type polysilicon film 109B.
- the fifth resist pattern is removed, and the amorphous region and crystal defects are recovered (crystallized) from the P-type polysilicon film 109A and the N-type polysilicon film 109B doped by ion implantation.
- Annealing is performed in a nitrogen atmosphere at 750 ° C. for 30 seconds.
- the order of forming the P-type polysilicon film 109A and the N-type polysilicon film 109B is not particularly limited.
- a sixth resist pattern (not shown) for forming each gate electrode is formed on the doped P-type polysilicon film 109A and N-type polysilicon film 109B.
- the formed sixth resist pattern as a mask, in the P-type FET region 10, the P-type polysilicon film 109A, the tantalum carbonitride oxide film 108A, the tantalum nitride film 107, the hafnium oxide film 105, and the silicon oxide film 104 Then, dry etching is performed for patterning sequentially.
- the N-type polysilicon film 109B, the tantalum carbide film 108B, the tantalum nitride film 107, the hafnium oxide film 105, and the silicon oxide film 104 are dry. Etching is performed to sequentially pattern.
- the etching gas for example, a mixed gas of chlorine (Cl 2 ) and hydrogen bromide (HBr) can be used.
- a base insulating film 104a is formed from the patterned silicon oxide film 104 in the P-type FET region 10, and a high dielectric constant insulating film 105a is formed from the patterned hafnium oxide film 105, thereby forming the base insulating film 104a.
- a gate insulating film 106a made of the high dielectric constant insulating film 105a is formed.
- a lower metal electrode 107a is formed from the patterned tantalum nitride film 107, and an upper metal electrode 108a is formed from the patterned tantalum carbonitride oxide film 108A.
- a P-type silicon electrode 109a is formed from the patterned P-type polysilicon film 109A to obtain a gate electrode 113a.
- a base insulating film 104b is formed from the patterned silicon oxide film 104, and a high dielectric constant insulating film 105b is formed from the patterned hafnium oxide film 105 to form the base insulating film 104b.
- a gate insulating film 106b made of the high dielectric constant insulating film 105b is formed.
- the lower metal electrode 107b is formed from the patterned tantalum nitride film 107
- the upper metal electrode 108b is formed from the patterned tantalum carbide film 108B.
- an N-type silicon electrode 109b is formed from the patterned N-type polysilicon film 109B to obtain a gate electrode 113b.
- the gate length of each gate electrode 113a, 113b is 40 nm as described above.
- the sixth resist pattern is removed, and then a seventh resist pattern (not shown) for masking the N-type FET region 20 is formed.
- boron difluoride (BF 2 ) is ion-implanted into the N-type active region 103a in the P-type FET region 10 using the formed seventh resist pattern and the gate electrode 113a as a mask.
- P-type extension implantation regions 111A are formed in regions on both sides of the gate electrode 113a on the N-type active region 103a.
- the seventh resist pattern is removed, and then an eighth resist pattern (not shown) that masks the P-type FET region 10 is formed.
- arsenic (As) is ion-implanted into the active region 103b in the N-type FET region 20 using the formed eighth resist pattern and the gate electrode 113b as a mask.
- N-type extension implantation regions 111B are formed in regions on both sides of the gate electrode 113b on the P-type active region 103b.
- the order of the formation of the P-type extension implantation region 111A in the P-type FET region 10 and the formation of the N-type extension implantation region 111B in the N-type FET region 20 are not particularly limited.
- N-type pocket implantation may be performed in the P-type FET region 10 before or after the P-type extension implantation.
- P-type pocket implantation may be performed in the N-type FET region 20 before or after the N-type extension implantation.
- a silicon nitride film having a thickness of about 40 nm is formed on the semiconductor substrate 100 including the gate electrodes 113a and 113b by the CVD method. Thereafter, the formed silicon nitride film is etched back entirely by dry etching, thereby forming side wall spacers 110a and 110b made of a silicon nitride film having a width of about 40 nm on the side surfaces of the gate electrodes 113a and 113b, respectively. To do.
- a ninth resist pattern (not shown) that covers the N-type FET region 20 is formed, and the P-type FET region 10 is formed using the formed ninth resist pattern, the gate electrode 113a, and the sidewall spacer 110a as a mask.
- Boron ions are implanted into the N-type active region 103a.
- a P-type source / drain implantation region connected to the P-type extension implantation region 111A is formed on the side of the gate electrode 113a in the N-type active region 103a.
- boron ion implantation is performed under the conditions of an acceleration energy of 3 keV and a dose of 4 ⁇ 10 15 atoms / cm 2 .
- a tenth resist pattern (not shown) covering the P-type FET region 10 is formed, and the formed tenth resist pattern, the gate electrode 113b, and the sidewall spacer 110b are formed.
- phosphorus is ion-implanted into the P-type active region 103b of the N-type FET region 20.
- an N-type source / drain implantation region connected to the N-type extension implantation region 111B is formed on the side of the gate electrode 113b in the P-type active region 103b.
- phosphorus ion implantation is performed under the conditions of an acceleration energy of 8 keV and a dose of 4 ⁇ 10 15 atoms / cm 2 .
- the order of forming the P-type source / drain implantation region and the N-type source / drain implantation region is not particularly limited.
- spike annealing at a temperature of 1000 ° C. is performed to activate impurities introduced by ion implantation.
- boron in the P-type extension implantation region 111A is diffused to form a P-type extension region 111a.
- arsenic in the N-type extension implantation region 111B is diffused to form the N-type extension region 111b.
- boron in the P-type source / drain implantation region and phosphorus in the N-type source / drain implantation region are diffused to form a P-type source / drain region 112a and an N-type source / drain region 112b, respectively. .
- junction depths after activation annealing in the P-type extension region 111a, the N-type extension region 111b, the P-type source / drain region 112a, and the N-type source / drain region 112b are about 20 nm and 80 nm, respectively.
- the method of the semiconductor device according to the present embodiment includes the lower metal electrodes 107a and 107b and the P-type silicon electrode 109a and the N-type silicon electrode 109b formed thereon. And a step of forming upper metal electrodes 108a and 108b, respectively.
- the height of the Schottky barrier formed when the lower metal electrodes 107a and 107b are brought into contact with the P-type silicon electrode 109a and the N-type silicon electrode 109b thereon can be reduced.
- the method of forming the upper metal electrodes 108a and 108b is not particularly limited, but it is desirable to form the upper metal electrodes 108a and 108b by an atomic layer deposition (ALD) method in order to reduce variations in film thickness.
- ALD atomic layer deposition
- tantalum carbonitride oxide (TaCNO) is used as the upper metal electrode 108a, but is not limited to tantalum carbonitride oxide (TaCNO), and as described above, the work function is higher than that of the lower metal electrode 107a.
- TaCNO tantalum carbonitride oxide
- the work function is higher than that of the lower metal electrode 107a.
- tantalum carbide (TaCx) is used as the upper metal electrode 108b, but is not limited to tantalum carbide (TaCx).
- TaCx tantalum carbide
- TaCx tantalum carbide
- a material having a work function smaller than that of the lower metal electrode 107b is used. Just choose.
- the upper metal electrodes 108a and 108b for reducing the interface resistance are formed on both the P-type FET and the N-type FET.
- the upper metal electrode is formed only on one of the FETs. May be. That is, if the height of the Schottky barrier generated between the lower layer metal electrode and the silicon electrode on it is small and the interface resistance between the two is small enough not to cause a problem, an FET with a small interface resistance There is no need to provide an upper metal electrode.
- a semiconductor device and a manufacturing method thereof according to the present invention realize a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, the metal electrode, the silicon electrode, This is effective for a semiconductor integrated circuit device or the like that requires good AC characteristics.
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Abstract
A semiconductor device contains a P-type FET that is formed in an N-type active region (103a) of a semiconductor substrate (100). The P-type FET comprises a gate insulating film (106a) that is formed on the N-type active region and a gate electrode (113a) that is formed on the gate insulating film. The gate electrode comprises a lower metal electrode layer (107a) that is formed on the gate insulating film, an upper metal electrode layer (108a) that is formed on the lower metal electrode layer, and a P-type silicon electrode (109a) that is formed on the upper metal electrode layer. The work function of a metal or metal compound that constitutes the upper metal electrode layer has such a value that the height of the Schottky barrier between the upper metal electrode layer and the P-type silicon electrode is lower than the height of the Schottky barrier that is formed in cases where the lower metal electrode layer and the P-type silicon electrode are in direct contact with each other.
Description
本発明は、金属電極と該金属電極の上に形成されたシリコン電極とを有するゲート電極を備えた電界効果型トランジスタを含む半導体装置及びその製造方法に関する。
The present invention relates to a semiconductor device including a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, and a method for manufacturing the semiconductor device.
半導体装置のデザインルールの縮小に伴い、半導体集積回路の集積度は飛躍的に向上し、１チップに１億個以上の電界効果型トランジスタ（Field Effect Transistor:ＦＥＴ）の搭載も可能となっている。高性能なトランジスタを実現するには、該トランジスタのゲート長を縮小するだけでなく、ゲート絶縁膜の薄膜化も求められる。従来、ゲート絶縁膜として、シリコン酸化膜又はその窒化膜であるシリコン酸窒化膜が用いられてきたが、等価酸化膜厚（Equivalent Oxide Thickness：ＥＯＴ）が２ｎｍ以下の薄膜領域となると、ゲートリーク電流が増大して、集積回路の消費電力が増大するという不具合が発生する。
As the design rules of semiconductor devices have been reduced, the degree of integration of semiconductor integrated circuits has dramatically improved, and more than 100 million field effect transistors (FETs) can be mounted on a single chip. . In order to realize a high-performance transistor, not only reducing the gate length of the transistor but also reducing the thickness of the gate insulating film is required. Conventionally, a silicon oxide film or a silicon oxynitride film, which is a nitride film thereof, has been used as a gate insulating film. However, when an equivalent oxide thickness (EOT) is a thin film region of 2 nm or less, a gate leakage current is obtained. Increases, which causes a problem that the power consumption of the integrated circuit increases.
そこで、ゲートリーク電流を低減しつつ、ＥＯＴの薄膜化を実現するために、高誘電率絶縁体からなるゲート絶縁膜に関心が寄せられている。また、さらなるＥＯＴの薄膜化を図るために、窒化チタン又は窒化タンタル等からなる金属電極を、従来からゲート電極として用いられているシリコン電極とゲート絶縁膜との間に挟み込んだ（Metal Inserted Poly-silicon Stacked FET：ＭＩＰＳ ＦＥＴ）について、多くの研究及び開発がなされている（例えば、特許文献１を参照。）。このＭＩＰＳ ＦＥＴは、金属電極がシリコン電極の下側（ゲート絶縁膜側）に形成されるため、シリコン電極の空乏化を抑制することが可能となるので、トランジスタの高性能化を図ることができる。
Therefore, in order to reduce the gate leakage current and realize the thinning of the EOT, there is an interest in a gate insulating film made of a high dielectric constant insulator. In order to further reduce the thickness of the EOT, a metal electrode made of titanium nitride or tantalum nitride is sandwiched between a silicon electrode conventionally used as a gate electrode and a gate insulating film (Metal Inserted Poly- Many researches and developments have been made on silicon-stacked FET (MIPS FET) (see, for example, Patent Document 1). In this MIPS FET, since the metal electrode is formed on the lower side (gate insulating film side) of the silicon electrode, depletion of the silicon electrode can be suppressed, so that the performance of the transistor can be improved. .
ＭＩＰＳ ＦＥＴは、従来からゲート電極として用いられている膜厚が５０ｎｍ～１００ｎｍと比較的に厚い膜厚を有するシリコン電極の下に、膜厚が５ｎｍ程度と比較的に薄い金属電極を形成することにより実現される。ゲート電極の形状、すなわちゲート電極の寸法及び高さ等を従来から用いられているシリコン電極と同程度とすることが容易であるため、半導体製造プロセスにおける３２ｎｍ以細の世代のＦＥＴに対する有力なゲート電極構造の１つとして、研究及び開発がなされている（例えば、非特許文献１を参照。）。
In MIPS FET, a relatively thin metal electrode having a thickness of about 5 nm is formed under a silicon electrode having a relatively large thickness of 50 nm to 100 nm, which has been conventionally used as a gate electrode. It is realized by. Because it is easy to make the shape of the gate electrode, that is, the size and height of the gate electrode, the same as that of the conventionally used silicon electrode, it is a powerful gate for the generation of FETs smaller than 32 nm in the semiconductor manufacturing process. Research and development have been conducted as one of electrode structures (see, for example, Non-Patent Document 1).
しかしながら、ＭＩＰＳ構造を有するＦＥＴ（ＭＩＰＳ ＦＥＴ）を実現しようとすると、金属電極とシリコン電極との界面に生じる界面抵抗のために、半導体集積回路の交流特性が劣化するという問題がある。
However, when an FET having a MIPS structure (MIPS FET) is to be realized, there is a problem that the AC characteristics of the semiconductor integrated circuit deteriorate due to the interface resistance generated at the interface between the metal electrode and the silicon electrode.
図７は従来のＭＩＰＳ構造を有するＰ型ＦＥＴの模式的な断面構成を示している。Ｎウェル等のＮ型不純物を含むシリコン（Ｓｉ）からなる半導体基板３００の上部に、素子分離領域３０１に囲まれた活性領域３０２が形成されている。Ｎ型活性領域３０２の上には、例えばシリコン酸化膜３０３とハフニウム酸化膜３０４との積層膜からなるゲート絶縁膜３０５が形成されている。ゲート絶縁膜３０５の上には、例えば、窒化タンタル（ＴａＮ）からなる金属電極３０６とＰ型ポリシリコンからなるＰ型シリコン電極３０７とから構成されたゲート電極３０８が形成されている。
FIG. 7 shows a schematic cross-sectional configuration of a P-type FET having a conventional MIPS structure. An active region 302 surrounded by an element isolation region 301 is formed on a semiconductor substrate 300 made of silicon (Si) containing an N-type impurity such as an N well. On the N-type active region 302, a gate insulating film 305 made of, for example, a laminated film of a silicon oxide film 303 and a hafnium oxide film 304 is formed. On the gate insulating film 305, for example, a gate electrode 308 composed of a metal electrode 306 made of tantalum nitride (TaN) and a P-type silicon electrode 307 made of P-type polysilicon is formed.
ゲート絶縁膜３０５及びゲート電極３０８の両側面上には、サイドウォールスペーサ３０９がそれ形成されている。
Side wall spacers 309 are formed on both side surfaces of the gate insulating film 305 and the gate electrode 308.
Ｎ型活性領域３０２の上部であって、ゲート電極３０８の両側方に位置する領域にはＰ型エクステンション領域３１０が形成され、さらに、Ｎ型活性領域３０２の上部におけるゲート電極３０８の両側方であって、Ｐ型エクステンション領域３１０の両外側の領域には、各Ｐ型エクステンション領域３１０と接続されたＰ型ソース／ドレイン領域３１１がそれぞれ形成されている。
A P-type extension region 310 is formed in a region above the N-type active region 302 and on both sides of the gate electrode 308, and further on both sides of the gate electrode 308 above the N-type active region 302. In addition, P-type source / drain regions 311 connected to the P-type extension regions 310 are formed in regions outside both sides of the P-type extension region 310, respectively.
金属電極３０６とＰ型シリコン電極３０７との界面に生じる界面抵抗は、各構成材料が持つ仕事関数の差であるショットキーバリアの高さに依存する。窒化タンタルの仕事関数は４．５ｅＶ程度であるのに対し、Ｐ型ポリシリコンの仕事関数は５．１ｅＶ程度である。従って、金属電極３０６とＰ型シリコン電極３０７との界面に形成されるショットキーバリアの高さは０．６ｅＶ程度と比較的に大きい値となる。
The interfacial resistance generated at the interface between the metal electrode 306 and the P-type silicon electrode 307 depends on the height of the Schottky barrier, which is the difference in work function of each constituent material. The work function of tantalum nitride is about 4.5 eV, whereas the work function of P-type polysilicon is about 5.1 eV. Therefore, the height of the Schottky barrier formed at the interface between the metal electrode 306 and the P-type silicon electrode 307 is a relatively large value of about 0.6 eV.
図８は、窒化タンタルからなる金属電極３０６とＰ型シリコン電極３０７とを接触させた場合のエネルギーバンドを示している。窒化タンタル（ＴａＮ）の仕事関数に対して、Ｐ型ポリシリコン（Ｐ－Ｓｉ）の仕事関数が大きいため、両者を接触させた場合は、Ｐ型ポリシリコンのエネルギーバンドが下方に曲がり、両者の界面に空乏層（バンドが曲がっている部分）が形成される。その結果、金属電極３０６とＰ型シリコン電極３０７との界面に界面抵抗が発生する。
FIG. 8 shows an energy band when the metal electrode 306 made of tantalum nitride and the P-type silicon electrode 307 are brought into contact with each other. Since the work function of P-type polysilicon (P-Si) is larger than the work function of tantalum nitride (TaN), when both are brought into contact, the energy band of P-type polysilicon bends downward. A depletion layer (a portion where the band is bent) is formed at the interface. As a result, an interface resistance is generated at the interface between the metal electrode 306 and the P-type silicon electrode 307.
Ｐ型シリコン電極３０７は、一般にアンドープのポリシリコン膜にボロン（Ｂ）等のＰ型の不純物をイオン注入することにより形成される。具体的には、注入イオンであるボロンが半導体基板３００に突き抜けることを抑制するため、アンドープのポリシリコン膜の上部、例えば上面から２０ｎｍ～３０ｎｍの深さにイオン注入を行い、その後の熱処理によってポリシリコン膜の全体をＰ型半導体にするという手法が採られる。
The P-type silicon electrode 307 is generally formed by ion-implanting a P-type impurity such as boron (B) into an undoped polysilicon film. Specifically, in order to prevent boron, which is an implanted ion, from penetrating into the semiconductor substrate 300, ion implantation is performed at a depth of 20 nm to 30 nm from the upper portion of the undoped polysilicon film, for example, from the upper surface, and the subsequent heat treatment is performed to polycrystal. A technique is adopted in which the entire silicon film is made into a P-type semiconductor.
このため、Ｐ型ポリシリコンからなるＰ型シリコン電極３０７の金属電極３０６との界面、すなわちＰ型シリコン電極３０７の下部におけるＰ型の不純物濃度はその上部と比べて小さくなる。ここで、Ｐ型シリコン電極３０７と金属電極３０６との界面のＰ型の不純物濃度を７×１０１９ａｔｏｍｓ／ｃｍ３とし、ショットキーバリアの高さを０．６ｅＶとした場合は、その界面抵抗は２×１０－６Ωｃｍ２程度となる。この値は、半導体製造プロセスにおける３２ｎｍ世代で一般的に要望されている、１×１０－７Ωｃｍ２以下という値に対して極めて大きい。
Therefore, the P-type impurity concentration at the interface between the P-type silicon electrode 307 made of P-type polysilicon and the metal electrode 306, that is, at the lower part of the P-type silicon electrode 307 is smaller than that at the upper part. Here, when the P-type impurity concentration at the interface between the P-type silicon electrode 307 and the metal electrode 306 is 7 × 10 19 atoms / cm 3 and the Schottky barrier height is 0.6 eV, the interface resistance Is about 2 × 10 −6 Ωcm 2 . This value is extremely large with respect to a value of 1 × 10 −7 Ωcm 2 or less, which is generally desired in the 32 nm generation in the semiconductor manufacturing process.
界面抵抗の低減は、Ｐ型シリコン電極３０７の下部のＰ型の不純物濃度を高めることによって実現可能ではあるが、注入イオンの基板中への突き抜け防止の観点から、また、上述したＰ型の不純物濃度の７×１０１９ａｔｏｍｓ／ｃｍ３が不純物の固溶限界である２×１０２０ａｔｏｍｓ／ｃｍ３（１０５０℃の活性化アニール後）に近い値であることから、Ｐ型の不純物濃度を増大させるという手法により界面抵抗を大幅に低減することは極めて困難である。
The reduction of the interface resistance can be realized by increasing the P-type impurity concentration below the P-type silicon electrode 307, but from the viewpoint of preventing the penetration of implanted ions into the substrate, the above-described P-type impurities are also included. Since the concentration of 7 × 10 19 atoms / cm 3 is close to the impurity solubility limit of 2 × 10 20 atoms / cm 3 (after activation annealing at 1050 ° C.), the P-type impurity concentration is increased. It is extremely difficult to greatly reduce the interfacial resistance by the technique of making it happen.
また、Ｎ型ＦＥＴに対しても、Ｐ型ＦＥＴと同様の問題が生じる。
Also, problems similar to those of P-type FETs occur with respect to N-type FETs.
本発明は、前記の問題を解決し、金属電極と該金属電極の上に形成されたシリコン電極とを有するゲート電極を備えた電界効果型トランジスタを実現する際に、金属電極とシリコン電極との界面に生じる界面抵抗を低減できるようにすることを目的とする。
The present invention solves the above-described problem and realizes a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode. The object is to reduce the interfacial resistance generated at the interface.
前記の目的を達成するため、本発明は、半導体装置における金属電極とシリコン電極との間に、該金属電極とシリコン電極との界面に生じる界面抵抗を低減することが可能な金属層（上層金属電極）を設ける構成とする。
In order to achieve the above object, the present invention provides a metal layer (upper metal layer) capable of reducing the interface resistance generated at the interface between the metal electrode and the silicon electrode between the metal electrode and the silicon electrode in the semiconductor device. Electrode).
具体的に、本発明に係る半導体装置は、半導体基板における第１の活性領域に形成された第１導電型の第１の電界効果型トランジスタを備え、第１の電界効果型トランジスタは、第１の活性領域の上に形成された第１のゲート絶縁膜と、第１のゲート絶縁膜の上に形成された第１のゲート電極とを有し、第１のゲート電極は、第１のゲート絶縁膜の上に形成された第１の下層金属電極と、該第１の下層金属電極の上に形成された第１の上層金属電極と、該第１の上層金属電極の上に形成された第１のシリコン電極とを有し、第１の上層金属電極を構成する金属又は金属化合物は、第１の上層金属電極を構成する金属又は金属化合物と第１のシリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、第１の下層金属電極を構成する金属又は金属化合物と第１のシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している。
Specifically, a semiconductor device according to the present invention includes a first conductivity type first field effect transistor formed in a first active region of a semiconductor substrate, and the first field effect transistor includes: And a first gate electrode formed on the first gate insulating film, wherein the first gate electrode is a first gate electrode. A first lower layer metal electrode formed on the insulating film, a first upper layer metal electrode formed on the first lower layer metal electrode, and formed on the first upper layer metal electrode A metal or a metal compound constituting the first upper metal electrode and a metal or metal compound constituting the first upper metal electrode and silicon constituting the first silicon electrode. The height of the first Schottky barrier formed between It has a work function smaller than the height of the second Schottky barrier formed when the metal or metal compound constituting the metal electrode and the silicon constituting the first silicon electrode are brought into direct contact with each other. .
本発明の半導体装置によると、第１のゲート電極は、第１の下層金属電極と第１のシリコン電極との間に形成される第１の上層金属電極を有しており、さらに、該第１の上層金属電極を構成する金属又は金属化合物は、第１の上層金属電極を構成する金属又は金属化合物と第１のシリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、第１の下層金属電極を構成する金属又は金属化合物と第１のシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している。このため、第１の上層金属電極と第１のシリコン電極との間のショットキーバリアの高さが小さくなるので、第１のゲート電極内における界面抵抗の低減が可能となる。
According to the semiconductor device of the present invention, the first gate electrode has the first upper layer metal electrode formed between the first lower layer metal electrode and the first silicon electrode, and The metal or metal compound constituting one upper metal electrode is a first Schottky barrier formed between the metal or metal compound constituting the first upper metal electrode and the silicon constituting the first silicon electrode. Is higher than the height of the second Schottky barrier formed when the metal or metal compound constituting the first lower metal electrode and the silicon constituting the first silicon electrode are brought into direct contact with each other. Has a smaller work function. For this reason, since the height of the Schottky barrier between the first upper metal electrode and the first silicon electrode is reduced, the interface resistance in the first gate electrode can be reduced.
本発明の半導体装置において、第１のショットキーバリアの高さは、０．４ｅＶ未満であることが好ましい。
In the semiconductor device of the present invention, the height of the first Schottky barrier is preferably less than 0.4 eV.
このような場合に、本発明の効果が顕著となる。
In such a case, the effect of the present invention becomes remarkable.
本発明の半導体装置において、第２のショットキーバリアの高さは、０．４ｅＶ以上であってもよい。
In the semiconductor device of the present invention, the height of the second Schottky barrier may be 0.4 eV or more.
このような場合に、本発明の効果が顕著となる。
In such a case, the effect of the present invention becomes remarkable.
本発明の半導体装置において、第１の上層金属電極の膜厚は、１．５ｎｍ以上且つ１５ｎｍ以下であってもよい。
In the semiconductor device of the present invention, the film thickness of the first upper metal electrode may be not less than 1.5 nm and not more than 15 nm.
本発明の半導体装置において、第１の電界効果型トランジスタは、Ｎ型トランジスタであり、第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、第１の下層金属電極を構成する金属又は金属化合物の仕事関数よりも小さいことが好ましい。
In the semiconductor device of the present invention, the first field effect transistor is an N-type transistor, and the work function of the metal or metal compound constituting the first upper metal electrode is the metal constituting the first lower metal electrode. Or it is preferable that it is smaller than the work function of a metal compound.
本発明の半導体装置において、第１のシリコン電極はＮ型シリコンからなり、第１の上層金属電極には、炭化タンタル、窒化タンタルマグネシウム、チタン、窒化チタンマグネシウム、チタンアルミニウム、窒化チタンアルミニウム、タングステンシリサイド、アルミニウム、タンタル、銀、モリブデン、ランタン、ハフニウム、ジルコニウム又はマンガンを用いることができる。
In the semiconductor device of the present invention, the first silicon electrode is made of N-type silicon, and the first upper metal electrode is tantalum carbide, tantalum magnesium nitride, titanium, titanium magnesium magnesium, titanium aluminum, titanium aluminum nitride, tungsten silicide. Aluminum, tantalum, silver, molybdenum, lanthanum, hafnium, zirconium or manganese can be used.
また、本発明の半導体装置において、第１の電界効果型トランジスタは、Ｐ型トランジスタであり、第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、第１の下層金属電極を構成する金属又は金属化合物の仕事関数よりも大きいことが好ましい。
In the semiconductor device of the present invention, the first field effect transistor is a P-type transistor, and the work function of the metal or metal compound constituting the first upper metal electrode constitutes the first lower metal electrode. It is preferable that it is larger than the work function of the metal or metal compound.
本発明の半導体装置において、第１のシリコン電極はＰ型シリコンからなり、第１の上層金属電極には、炭窒化酸化タンタル、炭窒化タンタル、窒化チタン、タングステン白金シリサイド、炭化酸化タンタル、白金シリサイド、窒化タングステン、ニッケルシリサイド、窒化モリブデン、白金、ニッケル、パラジウム、金又はタングステンを用いることができる。
In the semiconductor device of the present invention, the first silicon electrode is made of P-type silicon, and the first upper metal electrode includes tantalum carbonitride oxide, tantalum carbonitride, titanium nitride, tungsten platinum silicide, tantalum carbide oxide, platinum silicide. , Tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold, or tungsten can be used.
本発明の半導体装置は、半導体基板における第２の活性領域に形成された第２導電型の第２の電界効果型トランジスタをさらに備え、第２の電界効果型トランジスタは、第２の活性領域の上に形成された第２のゲート絶縁膜と、第２のゲート絶縁膜の上に形成された第２のゲート電極とを有し、第２のゲート電極は、第２のゲート絶縁膜の上に形成された第２の下層金属電極と、該第２の下層金属電極の上に形成された第２の上層金属電極と、該第２の上層金属電極の上に形成された第２のシリコン電極とを有し、第２の上層金属電極を構成する金属又は金属化合物は、第２の上層金属電極を構成する金属又は金属化合物と第２のシリコン電極を構成するシリコンとの間に形成される第３のショットキーバリアの高さが、第２の下層金属電極を構成する金属又は金属化合物と第２のシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第４のショットキーバリアの高さよりも小さくなる仕事関数を有していることが好ましい。
The semiconductor device of the present invention further includes a second conductivity type second field effect transistor formed in the second active region of the semiconductor substrate, and the second field effect transistor includes the second active region. A second gate insulating film formed on the second gate insulating film; and a second gate electrode formed on the second gate insulating film, wherein the second gate electrode is formed on the second gate insulating film. A second lower metal electrode formed on the second lower metal electrode, a second upper metal electrode formed on the second lower metal electrode, and a second silicon formed on the second upper metal electrode. And the metal or metal compound constituting the second upper metal electrode is formed between the metal or metal compound constituting the second upper metal electrode and the silicon constituting the second silicon electrode. The height of the third Schottky barrier is Having a work function that is smaller than the height of the fourth Schottky barrier formed when the metal or metal compound that constitutes the silicon and the silicon that constitutes the second silicon electrode are brought into direct contact with each other. preferable.
このようにすると、互いに導電型が異なる第１の電界効果型トランジスタ及び第２の電界効果型トランジスタからなり、ＭＩＰＳ構造を有する相補型ＭＩＳＦＥＴ（Complementary Metal Insulator Semiconductor Field Effect Transistor）においても、金属電極とシリコン電極との界面抵抗を低減することができる。
In this manner, the complementary MISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) having the MIPS structure is composed of the first field effect transistor and the second field effect transistor having different conductivity types. Interfacial resistance with the silicon electrode can be reduced.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第３のショットキーバリアの高さは、０．４ｅＶ未満であることが好ましい。
When the semiconductor device of the present invention includes the second field effect transistor, the height of the third Schottky barrier is preferably less than 0.4 eV.
このような場合に、本発明の効果が顕著となる。
In such a case, the effect of the present invention becomes remarkable.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第４のショットキーバリアの高さは、０．４ｅＶ以上であってもよい。
When the semiconductor device of the present invention includes the second field effect transistor, the height of the fourth Schottky barrier may be 0.4 eV or more.
このような場合に、本発明の効果が顕著となる。
In such a case, the effect of the present invention becomes remarkable.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第２の上層金属電極の膜厚は、１．５ｎｍ以上且つ１５ｎｍ以下であってもよい。
When the semiconductor device of the present invention includes the second field effect transistor, the thickness of the second upper metal electrode may be 1.5 nm or more and 15 nm or less.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第２の電界効果型トランジスタは、Ｐ型トランジスタであり、第２の上層金属電極を構成する金属又は金属化合物の仕事関数は、第２の下層金属電極を構成する金属又は金属化合物の仕事関数よりも大きいことが好ましい。
When the semiconductor device of the present invention includes the second field-effect transistor, the second field-effect transistor is a P-type transistor, and the work function of the metal or metal compound constituting the second upper metal electrode Is preferably larger than the work function of the metal or metal compound constituting the second lower layer metal electrode.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第２のシリコン電極はＰ型シリコンからなり、第２の上層金属電極には、炭窒化酸化タンタル、炭窒化タンタル、窒化チタン、タングステン白金シリサイド、炭化酸化タンタル、白金シリサイド、窒化タングステン、ニッケルシリサイド、窒化モリブデン、白金、ニッケル、パラジウム、金又はタングステンを用いることができる。
When the semiconductor device of the present invention includes the second field-effect transistor, the second silicon electrode is made of P-type silicon, and the second upper metal electrode includes tantalum carbonitride oxide, tantalum carbonitride, nitridation. Titanium, tungsten platinum silicide, tantalum carbide oxide, platinum silicide, tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold, or tungsten can be used.
本発明の半導体装置は、第２の電界効果型トランジスタを備える場合に、第１の下層金属電極と第２の下層金属電極とは、同一の金属材料からなっていてもよい。
When the semiconductor device of the present invention includes the second field effect transistor, the first lower metal electrode and the second lower metal electrode may be made of the same metal material.
また、本発明の半導体装置は、半導体基板における第２の活性領域に形成された第２導電型の第２の電界効果型トランジスタをさらに備え、第２の電界効果型トランジスタは、第２の活性領域の上に形成された第２のゲート絶縁膜と、第２のゲート絶縁膜の上に形成された第２のゲート電極とを有し、第２のゲート電極は、第２のゲート絶縁膜の上に形成された第２の下層金属電極と、該第２の下層金属電極の上に接して形成された第２のシリコン電極とを有し、第１の下層金属電極と第２の下層金属電極とは、同一の金属材料からなり、第２の下層金属電極を構成する金属又は金属化合物と第２のシリコン電極を構成するシリコンとの間に形成される第５のショットキーバリアの高さは、０．４ｅＶ未満であることが好ましい。
The semiconductor device of the present invention further includes a second conductivity type second field effect transistor formed in the second active region of the semiconductor substrate, and the second field effect transistor includes the second active effect transistor. A second gate insulating film formed on the region; and a second gate electrode formed on the second gate insulating film, the second gate electrode being a second gate insulating film A second lower metal electrode formed on the second lower metal electrode, and a second silicon electrode formed on and in contact with the second lower metal electrode, the first lower metal electrode and the second lower metal electrode The metal electrode is made of the same metal material, and the height of the fifth Schottky barrier formed between the metal or metal compound constituting the second lower metal electrode and the silicon constituting the second silicon electrode. The thickness is preferably less than 0.4 eV.
このように、第２の電界効果型トランジスタにおける第２のゲート電極に第２の上層金属電極を設けない構成の場合であっても、ＭＩＰＳ構造を有する相補型ＭＩＳＦＥＴにおける金属電極とシリコン電極との界面抵抗を低減することができる。
Thus, even when the second gate electrode in the second field effect transistor is not provided with the second upper metal electrode, the metal electrode and the silicon electrode in the complementary MISFET having the MIPS structure The interface resistance can be reduced.
本発明の半導体装置において、第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、第１の下層金属電極を構成する金属又は金属化合物の仕事関数と第１のシリコン電極を構成するシリコンの仕事関数との間に位置してもよい。
In the semiconductor device of the present invention, the work function of the metal or metal compound constituting the first upper metal electrode constitutes the first silicon electrode and the work function of the metal or metal compound constituting the first lower metal electrode. It may be located between the work function of silicon.
本発明に係る半導体装置の製造方法は、半導体基板における第１の活性領域の上にゲート絶縁膜を形成する工程（ａ）と、ゲート絶縁膜の上にゲート電極を形成する工程（ｂ）とを備え、ゲート電極は、ゲート絶縁膜の上に形成された下層金属電極と、該下層金属電極の上に形成された上層金属電極と、該上層金属電極の上に形成されたシリコン電極とを有し、上層金属電極を構成する金属又は金属化合物は、上層金属電極を構成する金属又は金属化合物とシリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、下層金属電極を構成する金属又は金属化合物とシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している。
The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a gate insulating film on a first active region in a semiconductor substrate, and a step (b) of forming a gate electrode on the gate insulating film. The gate electrode comprises: a lower metal electrode formed on the gate insulating film; an upper metal electrode formed on the lower metal electrode; and a silicon electrode formed on the upper metal electrode. The metal or metal compound constituting the upper metal electrode has a height of the first Schottky barrier formed between the metal or metal compound constituting the upper metal electrode and the silicon constituting the silicon electrode, It has a work function smaller than the height of the second Schottky barrier formed when the metal or metal compound constituting the lower metal electrode and the silicon constituting the silicon electrode are brought into direct contact with each other. .
本発明の半導体装置の製造方法によると、ゲート電極は、ゲート絶縁膜の上に形成された下層金属電極と、該下層金属電極の上に形成された上層金属電極と、該上層金属電極の上に形成されたシリコン電極とを有しており、さらに、上層金属電極を構成する金属又は金属化合物は、上層金属電極を構成する金属又は金属化合物とシリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、下層金属電極を構成する金属又は金属化合物とシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している。このため、このため、上層金属電極とシリコン電極との間のショットキーバリアの高さが小さくなるので、ゲート電極内における界面抵抗の低減が可能となる。
According to the method for manufacturing a semiconductor device of the present invention, the gate electrode includes a lower layer metal electrode formed on the gate insulating film, an upper layer metal electrode formed on the lower layer metal electrode, and an upper layer metal electrode. Further, the metal or metal compound constituting the upper metal electrode is formed between the metal or metal compound constituting the upper metal electrode and the silicon constituting the silicon electrode. The height of the first Schottky barrier is higher than the height of the second Schottky barrier formed when the metal or metal compound constituting the lower metal electrode and the silicon constituting the silicon electrode are brought into direct contact with each other. Has a smaller work function. For this reason, since the height of the Schottky barrier between the upper metal electrode and the silicon electrode is reduced, the interface resistance in the gate electrode can be reduced.
本発明に係る半導体装置及びその製造方法によると、金属電極と該金属電極の上に形成されたシリコン電極とを有するゲート電極を備えた電界効果型トランジスタを実現する際に、シリコン電極中の不純物濃度が容易に実現できる程度の低い値であっても、金属電極とシリコン電極との界面に生じる界面抵抗を低減することができる。その結果、半導体集積回路の交流特性の劣化を防止することが可能となる。
According to the semiconductor device and the manufacturing method thereof according to the present invention, when realizing a field effect transistor having a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, impurities in the silicon electrode Even when the concentration is low enough to be easily realized, the interface resistance generated at the interface between the metal electrode and the silicon electrode can be reduced. As a result, it is possible to prevent the deterioration of the AC characteristics of the semiconductor integrated circuit.
（一実施形態）
本発明の一実施形態に係る半導体装置について図１を参照しながら説明する。 (One embodiment)
A semiconductor device according to an embodiment of the present invention will be described with reference to FIG.
本発明の一実施形態に係る半導体装置について図１を参照しながら説明する。 (One embodiment)
A semiconductor device according to an embodiment of the present invention will be described with reference to FIG.
図１に示すように、本実施形態に係る半導体装置は、例えば、Ｐ型シリコン（Ｓｉ）からなる半導体基板１００に形成されたＰ型ＦＥＴ領域１０とＮ型ＦＥＴ領域２０とを有している。半導体基板１００の上部におけるＰ型ＦＥＴ領域１０には、Ｎウェル領域１０１ａと、該Ｎウェル領域１０１ａのうち素子分離領域１０２に囲まれてなるＮ型活性領域１０３ａとが形成されている。同様に、半導体基板１００の上部におけるＮ型ＦＥＴ領域２０には、Ｐウェル領域１０１ｂと、該Ｐウェル領域１０１ｂのうち素子分離領域１０２に囲まれてなるＰ型活性領域１０３ｂとが形成されている。
As shown in FIG. 1, the semiconductor device according to the present embodiment includes, for example, a P-type FET region 10 and an N-type FET region 20 formed in a semiconductor substrate 100 made of P-type silicon (Si). . An N well region 101a and an N type active region 103a surrounded by an element isolation region 102 in the N well region 101a are formed in the P type FET region 10 on the semiconductor substrate 100. Similarly, a P well region 101b and a P type active region 103b surrounded by the element isolation region 102 in the P well region 101b are formed in the N type FET region 20 in the upper portion of the semiconductor substrate 100. .
（Ｐ型ＦＥＴ）
半導体基板１００のＰ型ＦＥＴ領域１０に形成されるＰ型電界効果型トランジスタ（ＦＥＴ）は、Ｎ型活性領域１０３ａの上にゲート絶縁膜１０６ａを介在させて形成された下層金属電極１０７ａと、該下層金属電極１０７ａの上に形成された上層金属電極１０８ａと、該上層金属電極１０８ａの上に形成されたＰ型シリコン電極１０９ａと、ゲート絶縁膜１０６ａからＰ型シリコン電極１０９ａまでの両側面上に形成されたサイドウォールスペーサ１１０ａと、Ｎ型活性領域１０３ａの上部におけるＰ型シリコン電極１０９ａの両側方の領域に形成されたＰ型エクステンション領域１１１ａと、Ｎ型活性領域１０３ａの上部におけるＰ型エクステンション領域１１１ａの外側の領域に形成されたＰ型ソース／ドレイン領域１１２ａとを有している。ここで、Ｐ型ソース／ドレイン領域１１２ａは、Ｐ型エクステンション領域１１１ａよりも高濃度のＰ型の不純物を含んでいる。また、Ｐ型ＦＥＴにおいて、下層金属電極１０７ａ、上層金属電極１０８ａ及びＰ型シリコン電極１０９ａを併せてゲート電極１１３ａと呼ぶ。 (P-type FET)
A P-type field effect transistor (FET) formed in the P-type FET region 10 of the semiconductor substrate 100 includes a lower metal electrode 107a formed on the N-type active region 103a with a gate insulating film 106a interposed therebetween, An upper metal electrode 108a formed on the lower metal electrode 107a, a P-type silicon electrode 109a formed on the upper metal electrode 108a, and both side surfaces from the gate insulating film 106a to the P-type silicon electrode 109a Side wall spacer 110a formed, P-type extension region 111a formed on both sides of P-type silicon electrode 109a above N-type active region 103a, and P-type extension region above N-type active region 103a P-type source / drain region 112a formed in a region outside 111a There. Here, the P-type source / drain region 112a contains a higher concentration of P-type impurities than the P-type extension region 111a. In the P-type FET, the lower metal electrode 107a, the upper metal electrode 108a, and the P-type silicon electrode 109a are collectively referred to as a gate electrode 113a.
半導体基板１００のＰ型ＦＥＴ領域１０に形成されるＰ型電界効果型トランジスタ（ＦＥＴ）は、Ｎ型活性領域１０３ａの上にゲート絶縁膜１０６ａを介在させて形成された下層金属電極１０７ａと、該下層金属電極１０７ａの上に形成された上層金属電極１０８ａと、該上層金属電極１０８ａの上に形成されたＰ型シリコン電極１０９ａと、ゲート絶縁膜１０６ａからＰ型シリコン電極１０９ａまでの両側面上に形成されたサイドウォールスペーサ１１０ａと、Ｎ型活性領域１０３ａの上部におけるＰ型シリコン電極１０９ａの両側方の領域に形成されたＰ型エクステンション領域１１１ａと、Ｎ型活性領域１０３ａの上部におけるＰ型エクステンション領域１１１ａの外側の領域に形成されたＰ型ソース／ドレイン領域１１２ａとを有している。ここで、Ｐ型ソース／ドレイン領域１１２ａは、Ｐ型エクステンション領域１１１ａよりも高濃度のＰ型の不純物を含んでいる。また、Ｐ型ＦＥＴにおいて、下層金属電極１０７ａ、上層金属電極１０８ａ及びＰ型シリコン電極１０９ａを併せてゲート電極１１３ａと呼ぶ。 (P-type FET)
A P-type field effect transistor (FET) formed in the P-
ゲート絶縁膜１０６ａは、例えば膜厚が１ｎｍの酸化シリコンからなる下地絶縁膜１０４ａと、該下地絶縁膜１０４ａの上に形成され、例えば膜厚が２ｎｍの酸化ハフニウム等の高誘電率絶縁体である金属酸化物からなる高誘電率絶縁膜１０５ａとから構成される。ここで、高誘電率絶縁体とは、窒化シリコン（ＳｉＮ）よりも誘電率が高い物質（例えば、比誘電率が８以上の絶縁体）を指す。
The gate insulating film 106a is, for example, a base insulating film 104a made of silicon oxide having a thickness of 1 nm and a high dielectric constant insulator such as hafnium oxide having a thickness of 2 nm formed on the base insulating film 104a. And a high dielectric constant insulating film 105a made of a metal oxide. Here, the high dielectric constant insulator refers to a substance having a dielectric constant higher than that of silicon nitride (SiN) (for example, an insulator having a relative dielectric constant of 8 or more).
ゲート電極１１３ａは、ゲート絶縁膜１０６ａの上に形成された金属又は導電性を持つ金属化合物からなる下層金属電極１０７ａと、該下層金属電極１０７ａの上に形成された、例えば炭窒化酸化タンタル（ＴａＣＮＯ）からなる上層金属電極１０８ａと、該上層金属電極１０８ａの上に形成されたＰ型のポリシリコン等からなるＰ型シリコン電極１０９ａとから構成される。
The gate electrode 113a includes a lower metal electrode 107a made of a metal or a conductive metal compound formed on the gate insulating film 106a, and a tantalum carbonitride oxide (TaCNO) formed on the lower metal electrode 107a. ) And a P-type silicon electrode 109a made of P-type polysilicon or the like formed on the upper metal electrode 108a.
例えば、下層金属電極１０７ａは、膜厚が５ｎｍの窒化タンタル（ＴａＮ）等からなる。また、上層金属電極１０８ａの膜厚は２ｎｍである。上層金属電極１０８ａの上に形成されたＰ型シリコン電極１０９ａの膜厚は１００ｎｍである。Ｐ型シリコン電極１０９ａの下部、すなわち上層金属電極１０８ａとの界面における、例えばボロン（Ｂ）からなるＰ型の不純物の不純物濃度は、７×１０１９ａｔｏｍｓ／ｃｍ３程度である。また、例えば、ゲート電極１１３ａのゲート長は４０ｎｍ程度であり、サイドウォールスペーサ１１０ａの幅は、４０ｎｍ程度である。
For example, the lower metal electrode 107a is made of tantalum nitride (TaN) having a film thickness of 5 nm. The film thickness of the upper metal electrode 108a is 2 nm. The film thickness of the P-type silicon electrode 109a formed on the upper metal electrode 108a is 100 nm. The impurity concentration of P-type impurities made of, for example, boron (B) at the lower portion of the P-type silicon electrode 109a, that is, at the interface with the upper metal electrode 108a is about 7 × 10 19 atoms / cm 3 . For example, the gate length of the gate electrode 113a is about 40 nm, and the width of the sidewall spacer 110a is about 40 nm.
Ｐ型エクステンション領域１１１ａは、Ｎ型活性領域１０３ａの上部におけるサイドウォールスペーサ１１０ａの下側に位置すると共に、平面視においてゲート電極１１３ａのゲート長方向側の各端部とそれぞれ重なるように設けられる。さらに、Ｐ型エクステンション領域１１１ａは、ボロン（Ｂ）等のＰ型の不純物がドープされ、その不純物濃度の最大値は２×１０２０ａｔｏｍｓ／ｃｍ３程度である。Ｐ型エクステンション領域１１１ａの接合深さ、すなわちＮ型活性領域１０３ａとの間で形成されるＰＮ接合面の、サイドウォールスペーサ１１０ａの下面（半導体基板１００の表面）からの深さは２０ｎｍ程度である。また、図示はしていないが、半導体基板１００のＮ型活性領域１０３ａにおいてＰ型エクステンション領域１１１ａを下方及び側方からそれぞれ覆うように、砒素（Ａｓ）又はリン（Ｐ）等のＮ型の不純物をドープした公知のポケット領域（例えばＮ型の不純物濃度は３×１０１８ａｔｏｍｓ／ｃｍ３程度）を形成してもよい。このようなＮ型のポケット領域をＮ型活性領域１０３ａに形成することにより、Ｐ型ＦＥＴの短チャネル特性を改善することが可能となる。
The P-type extension region 111a is located below the sidewall spacer 110a in the upper part of the N-type active region 103a, and is provided so as to overlap each end of the gate electrode 113a on the gate length direction side in plan view. Further, the P-type extension region 111a is doped with a P-type impurity such as boron (B), and the maximum value of the impurity concentration is about 2 × 10 20 atoms / cm 3 . The junction depth of the P-type extension region 111a, that is, the depth of the PN junction surface formed with the N-type active region 103a from the lower surface of the sidewall spacer 110a (the surface of the semiconductor substrate 100) is about 20 nm. . Although not shown, an N-type impurity such as arsenic (As) or phosphorus (P) so as to cover the P-type extension region 111a from below and from the side in the N-type active region 103a of the semiconductor substrate 100. A well-known pocket region doped with (for example, N-type impurity concentration is about 3 × 10 18 atoms / cm 3 ) may be formed. By forming such an N-type pocket region in the N-type active region 103a, the short channel characteristics of the P-type FET can be improved.
Ｐ型ソース／ドレイン領域１１２ａは、Ｎ型活性領域１０３ａの上部におけるゲート電極１１３ａに対してＰ型エクステンション領域１１１ａの外側の領域に該Ｐ型エクステンション領域１１１ａと接続されて形成される。Ｐ型ソース／ドレイン領域１１２ａは、ボロン（Ｂ）等のＰ型の不純物がドープされ、その不純物濃度の最大値は１×１０２１ａｔｏｍｓ／ｃｍ３程度である。Ｐ型ソース／ドレイン領域１１２ａの接合深さ、すなわちＮ型活性領域１０３ａとの間で形成されるＰＮ接合面の、半導体基板１００の表面からの深さは８０ｎｍ程度である。
The P-type source / drain region 112a is formed in a region outside the P-type extension region 111a with respect to the gate electrode 113a above the N-type active region 103a and connected to the P-type extension region 111a. The P-type source / drain region 112a is doped with a P-type impurity such as boron (B), and the maximum value of the impurity concentration is about 1 × 10 21 atoms / cm 3 . The junction depth of the P-type source / drain region 112a, that is, the depth from the surface of the semiconductor substrate 100 of the PN junction surface formed with the N-type active region 103a is about 80 nm.
Ｎ型活性領域１０３ａのうち、ゲート電極１１３ａの下側に位置する部分は、Ｎウェル領域１０１ａの形成及びしきい値電圧の制御のためのＮ型の不純物がドープされる。Ｎ型の不純物は、砒素（Ａｓ）又はリン（Ｐ）等であり、その不純物濃度は１×１０１７ａｔｏｍｓ／ｃｍ３程度である。
A portion of the N-type active region 103a located below the gate electrode 113a is doped with N-type impurities for forming the N-well region 101a and controlling the threshold voltage. The N-type impurity is arsenic (As), phosphorus (P), or the like, and the impurity concentration is about 1 × 10 17 atoms / cm 3 .
（Ｎ型ＦＥＴ）
一方、半導体基板１００のＮ型ＦＥＴ領域２０に形成されるＮ型電界効果型トランジスタ（ＦＥＴ）は、Ｐ型活性領域１０３ｂの上にゲート絶縁膜１０６ｂを介在させて形成された下層金属電極１０７ｂと、該下層金属電極１０７ｂの上に形成された上層金属電極１０８ｂと、該上層金属電極１０８ｂの上に形成されたＮ型シリコン電極１０９ｂと、ゲート絶縁膜１０６ｂからＮ型シリコン電極１０９ｂまでの両側面上に形成されたサイドウォールスペーサ１１０ｂと、Ｐ型活性領域１０３ｂの上部におけるＮ型シリコン電極１０９ｂの両側方の領域に形成されたＮ型エクステンション領域１１１ｂと、Ｐ型活性領域１０３ｂの上部におけるＮ型エクステンション領域１１１ｂの外側の領域に形成されたＮ型ソース／ドレイン領域１１２ｂとを有している。ここで、Ｎ型ソース／ドレイン領域１１２ｂは、Ｎ型エクステンション領域１１１ｂよりも高濃度のＮ型の不純物を含んでいる。また、Ｎ型ＦＥＴにおいて、下層金属電極１０７ｂ、上層金属電極１０８ｂ及びＮ型シリコン電極１０９ｂを併せてゲート電極１１３ｂと呼ぶ。 (N-type FET)
On the other hand, an N-type field effect transistor (FET) formed in the N-type FET region 20 of the semiconductor substrate 100 includes a lower metal electrode 107b formed on the P-type active region 103b with a gate insulating film 106b interposed therebetween. The upper metal electrode 108b formed on the lower metal electrode 107b, the N-type silicon electrode 109b formed on the upper metal electrode 108b, and both side surfaces from the gate insulating film 106b to the N-type silicon electrode 109b Side wall spacers 110b formed above, N-type extension regions 111b formed on both sides of the N-type silicon electrode 109b above the P-type active region 103b, and N-type above the P-type active region 103b An N-type source / drain region 112b formed in a region outside the extension region 111b; It has. Here, the N-type source / drain region 112b contains a higher concentration of N-type impurities than the N-type extension region 111b. In the N-type FET, the lower metal electrode 107b, the upper metal electrode 108b, and the N-type silicon electrode 109b are collectively referred to as a gate electrode 113b.
一方、半導体基板１００のＮ型ＦＥＴ領域２０に形成されるＮ型電界効果型トランジスタ（ＦＥＴ）は、Ｐ型活性領域１０３ｂの上にゲート絶縁膜１０６ｂを介在させて形成された下層金属電極１０７ｂと、該下層金属電極１０７ｂの上に形成された上層金属電極１０８ｂと、該上層金属電極１０８ｂの上に形成されたＮ型シリコン電極１０９ｂと、ゲート絶縁膜１０６ｂからＮ型シリコン電極１０９ｂまでの両側面上に形成されたサイドウォールスペーサ１１０ｂと、Ｐ型活性領域１０３ｂの上部におけるＮ型シリコン電極１０９ｂの両側方の領域に形成されたＮ型エクステンション領域１１１ｂと、Ｐ型活性領域１０３ｂの上部におけるＮ型エクステンション領域１１１ｂの外側の領域に形成されたＮ型ソース／ドレイン領域１１２ｂとを有している。ここで、Ｎ型ソース／ドレイン領域１１２ｂは、Ｎ型エクステンション領域１１１ｂよりも高濃度のＮ型の不純物を含んでいる。また、Ｎ型ＦＥＴにおいて、下層金属電極１０７ｂ、上層金属電極１０８ｂ及びＮ型シリコン電極１０９ｂを併せてゲート電極１１３ｂと呼ぶ。 (N-type FET)
On the other hand, an N-type field effect transistor (FET) formed in the N-
ゲート絶縁膜１０６ｂは、例えば膜厚が１ｎｍの酸化シリコンからなる下地絶縁膜１０４ｂと、該下地絶縁膜１０４ｂの上に形成され、例えば膜厚が２ｎｍの酸化ハフニウムからなる高誘電率絶縁膜１０５ｂとから構成されている。
The gate insulating film 106b is, for example, a base insulating film 104b made of silicon oxide having a thickness of 1 nm, and a high dielectric constant insulating film 105b made of hafnium oxide having a thickness of 2 nm, for example, formed on the base insulating film 104b. It is composed of
ゲート電極１１３ｂは、ゲート絶縁膜１０６ｂの上に形成された金属又は導電性を持つ金属化合物からなる下層金属電極１０７ｂと、該下層金属電極１０７ｂの上に形成された、例えば炭化タンタル（ＴａＣ）からなる上層金属電極１０８ｂと、該上層金属電極１０８ｂの上に形成されたＮ型のポリシリコン等からなるＮ型シリコン電極１０９ｂとから構成される。
The gate electrode 113b is made of, for example, tantalum carbide (TaC) formed on the lower metal electrode 107b and a lower metal electrode 107b made of a metal or a conductive metal compound formed on the gate insulating film 106b. And an N-type silicon electrode 109b made of N-type polysilicon or the like formed on the upper-layer metal electrode 108b.
例えば、下層金属電極１０７ｂは、膜厚が５ｎｍの窒化タンタル（ＴａＮ）等からなる。また、上層金属電極１０８ｂの膜厚は２ｎｍである。上層金属電極１０８ｂの上に形成されたＮ型シリコン電極１０９ｂの膜厚は１００ｎｍである。Ｎ型シリコン電極１０９ｂの下部、すなわち上層金属電極１０８ｂとの界面における、例えばリン（Ｐ）からなるＮ型の不純物の不純物濃度は、７×１０１９ａｔｏｍｓ／ｃｍ３程度である。また、例えば、ゲート電極１１３ｂのゲート長は４０ｎｍ程度であり、サイドウォールスペーサ１１０ｂの幅は、４０ｎｍ程度である。
For example, the lower metal electrode 107b is made of tantalum nitride (TaN) having a film thickness of 5 nm. The film thickness of the upper metal electrode 108b is 2 nm. The film thickness of the N-type silicon electrode 109b formed on the upper metal electrode 108b is 100 nm. The impurity concentration of an N-type impurity made of, for example, phosphorus (P) at the lower portion of the N-type silicon electrode 109b, that is, at the interface with the upper metal electrode 108b is about 7 × 10 19 atoms / cm 3 . For example, the gate length of the gate electrode 113b is about 40 nm, and the width of the sidewall spacer 110b is about 40 nm.
Ｎ型エクステンション領域１１１ｂは、Ｐ型活性領域１０３ｂの上部におけるサイドウォールスペーサ１１０ｂの下側に位置すると共に、平面視においてゲート電極１１３ｂのゲート長方向側の各端部とそれぞれ重なるように設けられる。さらに、Ｎ型エクステンション領域１１１ｂは、砒素（Ａｓ）等のＮ型の不純物がドープされ、その不純物濃度の最大値は２×１０２０ａｔｏｍｓ／ｃｍ３程度である。Ｎ型エクステンション領域１１１ｂの接合深さ、すなわちＰ型活性領域１０３ｂとの間で形成されるＰＮ接合面の、サイドウォールスペーサ１１０ｂの下面（半導体基板１００の表面）からの深さは２０ｎｍ程度である。また、図示はしていないが、半導体基板１００のＰ型活性領域１０３ｂにおいてＮ型エクステンション領域１１１ｂを下方及び側方からそれぞれ覆うように、ボロン（Ｂ）又はインジウム（Ｉｎ）等のＰ型の不純物をドープした公知のポケット領域（例えばＰ型の不純物濃度は３×１０１８ａｔｏｍｓ／ｃｍ３程度）を形成してもよい。このようなＰ型のポケット領域をＰ型活性領域１０３ｂに形成することにより、Ｎ型ＦＥＴの短チャネル特性を改善することが可能となる。
The N-type extension region 111b is located below the sidewall spacer 110b above the P-type active region 103b, and is provided so as to overlap each end of the gate electrode 113b on the gate length direction side in plan view. Further, the N-type extension region 111b is doped with an N-type impurity such as arsenic (As), and the maximum value of the impurity concentration is about 2 × 10 20 atoms / cm 3 . The junction depth of the N-type extension region 111b, that is, the depth of the PN junction surface formed with the P-type active region 103b from the lower surface of the sidewall spacer 110b (the surface of the semiconductor substrate 100) is about 20 nm. . Although not shown, a P-type impurity such as boron (B) or indium (In) so as to cover the N-type extension region 111b from below and from the side in the P-type active region 103b of the semiconductor substrate 100. A well-known pocket region doped with (for example, the P-type impurity concentration is about 3 × 10 18 atoms / cm 3 ) may be formed. By forming such a P-type pocket region in the P-type active region 103b, the short channel characteristics of the N-type FET can be improved.
Ｎ型ソース／ドレイン領域１１２ｂは、Ｐ型活性領域１０３ｂの上部におけるゲート電極１１３ｂに対してＮ型エクステンション領域１１１ｂの外側の領域に該Ｎ型エクステンション領域１１１ｂと接続されて形成される。Ｎ型ソース／ドレイン領域１１２ｂは、砒素（Ａｓ）又はリン（Ｐ）等のＮ型の不純物がドープされ、その不純物濃度の最大値は１×１０２１ａｔｏｍｓ／ｃｍ３程度である。Ｎ型ソース／ドレイン領域１１２ｂの接合深さ、すなわちＰ型活性領域１０３ｂとの間で形成されるＰＮ接合面の、半導体基板１００の表面からの深さは８０ｎｍ程度である。
The N-type source / drain region 112b is formed in a region outside the N-type extension region 111b with respect to the gate electrode 113b above the P-type active region 103b and connected to the N-type extension region 111b. The N-type source / drain region 112b is doped with N-type impurities such as arsenic (As) or phosphorus (P), and the maximum value of the impurity concentration is about 1 × 10 21 atoms / cm 3 . The junction depth of the N-type source / drain region 112b, that is, the depth of the PN junction surface formed with the P-type active region 103b from the surface of the semiconductor substrate 100 is about 80 nm.
また、Ｐ型活性領域１０３ｂのうち、ゲート電極１１３ｂの下側に位置する部分は、Ｐウェル領域１０１ｂの形成及びしきい値電圧の制御のためのＰ型の不純物がドープされる。Ｐ型不純物は、ボロン又はインジウム等であり、その不純物濃度は１×１０１７ａｔｏｍｓ／ｃｍ３程度である。
A portion of the P-type active region 103b located below the gate electrode 113b is doped with a P-type impurity for forming the P well region 101b and controlling the threshold voltage. The P-type impurity is boron, indium or the like, and the impurity concentration is about 1 × 10 17 atoms / cm 3 .
以下、前記のように構成された半導体装置において、Ｐ型ＦＥＴのゲート電極１１３ａ及びＮ型ＦＥＴのゲート電極１１３ｂの各内部において界面抵抗が低減するメカニズムについて図２を参照しながら説明する。
Hereinafter, in the semiconductor device configured as described above, a mechanism for reducing the interface resistance in each of the gate electrode 113a of the P-type FET and the gate electrode 113b of the N-type FET will be described with reference to FIG.
図２は、図１に示したＰ型ＦＥＴを構成するゲート電極の基板面に垂直な方向におけるエネルギーバンド図を示している。前述したように、仕事関数が４．５ｅＶの窒化タンタル（ＴａＮ）からなる下層金属電極と、仕事関数が５．１ｅＶのＰ型ポリシリコンからなるＰ型シリコン電極とを直接に接触させた場合は、エネルギーバンドは図８に示したようになる。すなわち、金属電極とＰ型シリコン電極との界面において、Ｐ型ポリシリコンのエネルギーバンドが下側に曲がり、ショットキーバリア（バリア高さ＝０．６ｅＶ）が形成される。
FIG. 2 shows an energy band diagram in a direction perpendicular to the substrate surface of the gate electrode constituting the P-type FET shown in FIG. As described above, when a lower metal electrode made of tantalum nitride (TaN) having a work function of 4.5 eV and a P-type silicon electrode made of P-type polysilicon having a work function of 5.1 eV are brought into direct contact with each other. The energy band is as shown in FIG. That is, at the interface between the metal electrode and the P-type silicon electrode, the energy band of the P-type polysilicon is bent downward, and a Schottky barrier (barrier height = 0.6 eV) is formed.
これに対し、本実施形態に係るＰ型ＦＥＴは、ゲート電極１１３ａにおいて、窒化タンタル（ＴａＮ）からなる下層金属電極１０７ａとＰ型ポリシリコンからなるＰ型シリコン電極１０９ａとの界面に、仕事関数が下層金属電極１０７ａよりも大きい値を持つ、例えば仕事関数が４．９ｅＶ程度の炭窒化酸化タンタル（ＴａＣＮＯ）からなる上層金属電極１０８ａを設けている。
In contrast, the P-type FET according to the present embodiment has a work function at the interface between the lower metal electrode 107a made of tantalum nitride (TaN) and the P-type silicon electrode 109a made of P-type polysilicon in the gate electrode 113a. An upper metal electrode 108a made of tantalum carbonitride oxide (TaCNO) having a larger value than that of the lower metal electrode 107a, for example, having a work function of about 4.9 eV is provided.
この構成によると、ゲート電極１１３ａの内部においては、下層金属電極１０７ａと上層金属電極１０８ａとの界面及び上層金属電極１０８とＰ型シリコン電極１０９ａとの界面の２ヶ所に界面が形成される。但し、下層金属電極１０７ａと上層金属電極１０８ａとの界面は、双方が共に金属（金属化合物）からなるため、その界面抵抗はきわめて小さい。
According to this configuration, interfaces are formed in the gate electrode 113a at two locations, that is, the interface between the lower metal electrode 107a and the upper metal electrode 108a and the interface between the upper metal electrode 108 and the P-type silicon electrode 109a. However, since the interface between the lower metal electrode 107a and the upper metal electrode 108a is both made of metal (metal compound), the interface resistance is extremely small.
また、図２に示すように、上層金属電極１０８ａとＰ型ポリシリコンからなるＰ型シリコン電極１０９ａとの界面においては、そのショットキーバリアの高さが０．２ｅＶ程度に小さくなるため、Ｐ型シリコン電極１０９ａにおけるエネルギーバンドの曲がりが小さくなる。すなわち、仕事関数が４．５ｅＶ程度の金属又は金属化合物からなる下層金属電極１０７ａと仕事関数が５．１ｅＶ程度のＰ型ポリシリコンからなるＰ型シリコン電極１０９ａとの間に、仕事関数が４．９ｅＶ程度の金属又は金属化合物からなる上層金属電極１０８ａを形成することにより、ショットキーバリアの高さを、０．６ｅＶ程度から０．２ｅＶ程度にまで小さくすることができる。その結果、ショットキーバリアによる界面抵抗は、１×１０－７Ωｃｍ２以下と極めて小さくなる。
Further, as shown in FIG. 2, the height of the Schottky barrier is reduced to about 0.2 eV at the interface between the upper metal electrode 108a and the P-type silicon electrode 109a made of P-type polysilicon. The bending of the energy band in the silicon electrode 109a is reduced. That is, the work function is 4. between the lower metal electrode 107a made of a metal or metal compound having a work function of about 4.5 eV and the P-type silicon electrode 109a made of P-type polysilicon having a work function of about 5.1 eV. By forming the upper metal electrode 108a made of a metal or a metal compound of about 9 eV, the height of the Schottky barrier can be reduced from about 0.6 eV to about 0.2 eV. As a result, the interfacial resistance due to the Schottky barrier is extremely small, 1 × 10 −7 Ωcm 2 or less.
以上説明したように、仕事関数が下層金属電極１０７ａよりも大きい上層金属電極１０８ａを、従来の構造である金属電極１０７ａとＰ型ポリシリコンからなるＰ型シリコン電極１０９ａとの間に形成することにより、ゲート電極１１３ａの内部に生じる界面抵抗を低減することが可能となる。従って、Ｐ型ＦＥＴを含む半導体集積回路の交流特性の劣化を抑制することができる。
As described above, the upper metal electrode 108a having a work function larger than that of the lower metal electrode 107a is formed between the metal electrode 107a having the conventional structure and the P-type silicon electrode 109a made of P-type polysilicon. The interface resistance generated inside the gate electrode 113a can be reduced. Therefore, it is possible to suppress the deterioration of the AC characteristics of the semiconductor integrated circuit including the P-type FET.
また、Ｎ型ＦＥＴにおいても、Ｐ型ＦＥＴと同様のメカニズムにより、下層金属電極１０７ｂとＮ型ポリシリコンからなるＮ型シリコン電極１０９ｂとの界面に生じる界面抵抗を低減することが可能となる。従って、半導体集積回路の交流特性の劣化を抑制することができる。但し、Ｎ型ＦＥＴの場合は、ショットキーバリアを形成するエネルギーバンドの曲がる向きがＰ型ＦＥＴの場合と反対に上側に曲がるため、下層金属電極１０７ｂの上に形成する上層金属電極１０８ｂの仕事関数は、下層金属電極１０７ｂよりも小さい値である必要がある。すなわち、仕事関数が４．５ｅＶ程度の金属電極１０７ｂと仕事関数が４．１ｅＶ程度のＮ型ポリシリコンからなるＮ型シリコン電極１０９ｂとの間に、仕事関数が４．２ｅＶ程度の、例えば炭化タンタル（ＴａＣｘ）からなる上層金属電極１０８ｂを形成することにより、ショットキーバリア高さを、０．４ｅＶ程度から０．１ｅＶ程度にまで小さくすることができる。その結果、ゲート電極１１３ｂの内部に生じる界面抵抗を低減することが可能となる。
In the N-type FET, the interface resistance generated at the interface between the lower metal electrode 107b and the N-type silicon electrode 109b made of N-type polysilicon can be reduced by the same mechanism as that of the P-type FET. Therefore, it is possible to suppress the deterioration of the AC characteristics of the semiconductor integrated circuit. However, in the case of an N-type FET, the bending direction of the energy band forming the Schottky barrier is bent upward as opposed to the case of the P-type FET, so that the work function of the upper metal electrode 108b formed on the lower metal electrode 107b Needs to be smaller than the lower metal electrode 107b. That is, for example, tantalum carbide having a work function of about 4.2 eV between a metal electrode 107b having a work function of about 4.5 eV and an N-type silicon electrode 109b made of N-type polysilicon having a work function of about 4.1 eV. By forming the upper metal electrode 108b made of (TaCx), the Schottky barrier height can be reduced from about 0.4 eV to about 0.1 eV. As a result, the interface resistance generated inside the gate electrode 113b can be reduced.
このように、本実施形態に係る半導体装置は、下層金属電極１０７ａとその上のＰ型シリコン電極１０９ａ、及び下層金属電極１０７ｂとその上のＮ型シリコン電極１０９ｂとの各界面に、下層金属電極１０７ａ、１０７ｂと各シリコン電極１０９ａ、１０９ｂとがそれぞれ接触した場合に生じるショットキーバリアの高さを低減する上層金属電極１０８ａ、１０８ｂを形成することを特徴としている。これにより、各ゲート電極１１３ａ、１１３ｂの内部に形成される界面抵抗を低減できるので、Ｐ型ＦＥＴ及びＮ型ＦＥＴを含む半導体集積回路の交流特性の劣化を抑制することができる。
As described above, the semiconductor device according to the present embodiment includes the lower layer metal electrode 107a and the P-type silicon electrode 109a thereon, and the lower layer metal electrode 107b and the upper N-type silicon electrode 109b at each interface. The upper metal electrodes 108a and 108b are formed to reduce the height of the Schottky barrier generated when the 107a and 107b and the silicon electrodes 109a and 109b are in contact with each other. As a result, the interface resistance formed inside each gate electrode 113a, 113b can be reduced, so that the deterioration of the AC characteristics of the semiconductor integrated circuit including the P-type FET and the N-type FET can be suppressed.
なお、Ｐ型ＦＥＴにおける上層金属電極１０８ａには炭窒化酸化タンタル（ＴａＣＮＯ）を用い、Ｎ型ＦＥＴにおける上層金属電極１０８ｂには、炭化タンタル（ＴａＣｘ）を用いたが、上層金属電極１０８ａ、１０８ｂの構成材料はこれらに限定されない。すなわち、上層金属電極１０８ａ、１０８ｂを下層金属電極１０７ａとＰ型シリコン電極１０９ａとの界面、及び下層金属電極１０７ｂとＮ型シリコン電極１０９ｂとの界面にそれぞれ形成することにより、ゲート電極１１３ａ及びゲート電極１１３ｂの内部に形成されるショットキーバリアの高さをそれぞれ低減できればよく、任意に選択することができる。
Although tantalum carbonitride (TaCNO) was used for the upper metal electrode 108a in the P-type FET and tantalum carbide (TaCx) was used for the upper metal electrode 108b in the N-type FET, the upper metal electrodes 108a and 108b The constituent materials are not limited to these. That is, by forming the upper metal electrodes 108a and 108b at the interface between the lower metal electrode 107a and the P-type silicon electrode 109a and the interface between the lower metal electrode 107b and the N-type silicon electrode 109b, respectively, the gate electrode 113a and the gate electrode Any height can be selected as long as the height of the Schottky barrier formed inside 113b can be reduced.
例えば、Ｐ型ＦＥＴの場合は、上層金属電極１０８ａとして、仕事関数が下層金属電極１０７ａよりも大きい材料を用いることが有効である。但し、上層金属電極１０８ａとＰ型シリコン電極１０９ａとの間のショットキーバリアの高さを０．４ｅＶ未満にすることが、界面抵抗の低減の観点から好ましい。本実施形態においては、上層金属電極１０８ａとして、下層金属電極１０７ａの仕事関数（４．５ｅＶ程度）とＰ型シリコン電極１０９ａの仕事関数（５．１ｅＶ程度）との間に位置する仕事関数（４．９ｅＶ程度）を有する炭窒化酸化タンタル（ＴａＣＮＯ）を用いて説明したが、Ｐ型シリコン電極１０９ａの仕事関数（５．１ｅＶ程度）よりも仕事関数が高くても、Ｐ型シリコン電極１０９ａとの間のショットキーバリアの高さを０．４ｅＶ未満にすることができる材料（例えば、仕事関数が５．３ｅＶの材料）であればよい。例えば、上層金属電極１０８ａの構成材料として、上記の炭窒化酸化タンタル（ＴａＣＮＯ）以外にも、炭窒化タンタル（ＴａＣＮ）、窒化チタン（ＴｉＮ）、タングステン白金シリサイド（ＷＰｔＳｉ）、炭化酸化タンタル（ＴａＣＯ）、白金シリサイド（ＰｔＳｉ）、窒化タングステン（ＷＮｘ）、ニッケルシリサイド（ＮｉＳｉ）、モリブデンナイトライド（ＭｏｘＮ）、白金（Ｐｔ）、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）、金（Ａｕ）又はタングステン（Ｗ）等などを用いることができる。
For example, in the case of a P-type FET, it is effective to use a material having a work function larger than that of the lower layer metal electrode 107a as the upper layer metal electrode 108a. However, the height of the Schottky barrier between the upper metal electrode 108a and the P-type silicon electrode 109a is preferably less than 0.4 eV from the viewpoint of reducing the interface resistance. In the present embodiment, as the upper metal electrode 108a, the work function (4) located between the work function (about 4.5 eV) of the lower metal electrode 107a and the work function (about 5.1 eV) of the P-type silicon electrode 109a. Although tantalum carbonitride oxide (TaCNO) having about 0.9 eV) has been described, even if the work function is higher than that of the P-type silicon electrode 109a (about 5.1 eV), Any material can be used as long as the height of the Schottky barrier between them can be less than 0.4 eV (for example, a material having a work function of 5.3 eV). For example, as a constituent material of the upper metal electrode 108a, in addition to the above tantalum carbonitride oxide (TaCNO), tantalum carbonitride (TaCN), titanium nitride (TiN), tungsten platinum silicide (WPtSi), tantalum carbide oxide (TaCO) Platinum silicide (PtSi), tungsten nitride (WNx), nickel silicide (NiSi), molybdenum nitride (MoxN), platinum (Pt), nickel (Ni), palladium (Pd), gold (Au) or tungsten (W) Etc. can be used.
一方、Ｎ型ＦＥＴの場合は、上層金属電極１０８ｂとして、仕事関数が下層金属電極１０７ｂよりも小さい材料を用いることが有効である。特に、上層金属電極１０８ｂとＮ型シリコン電極１０９ｂとの間のショットキーバリアの高さを０．４ｅＶ未満にすることが、界面抵抗の低減の観点から好ましい。本実施形態においては、上層金属電極１０８ｂとして、下層金属電極１０７ｂの仕事関数（４．５ｅＶ程度）とＮ型シリコン電極１０９ｂの仕事関数（４．１ｅＶ程度）との間に位置する仕事関数（４．２ｅＶ程度）を有する炭化タンタル（ＴａＣｘ）を用いて説明したが、Ｎ型シリコン電極１０９ｂの仕事関数（４．１ｅＶ程度）よりも仕事関数が低くても、Ｎ型シリコン電極１０９ｂとの間のショットキーバリアの高さを０．４ｅＶ未満にすることができる材料（例えば、仕事関数が３．９ｅＶの材料）であればよい。例えば、上層金属電極１０８ｂの構成材料として、上記の炭化タンタル（ＴａＣｘ）以外にも、窒化タンタルマグネシウム（ＴａＭｇＮ）、チタン（Ｔｉ）、窒化チタンマグネシウム（ＴｉＭｇＮ）、チタンアルミニウム（ＴｉＡｌ）、窒化チタンアルミニウム（ＴｉＡｌＮ）、タングステンシリサイド（ＷＳｉ）、アルミニウム（Ａｌ）、タンタル（Ｔａ）、銀（Ａｇ）、モリブデン（Ｍｏ）、ランタン（Ｌａ）、ハフニウム（Ｈｆ）、ジルコニウム（Ｚｒ）又はマンガン（Ｍｎ）等を用いることができる。
On the other hand, in the case of an N-type FET, it is effective to use a material having a work function smaller than that of the lower layer metal electrode 107b as the upper layer metal electrode 108b. In particular, the height of the Schottky barrier between the upper metal electrode 108b and the N-type silicon electrode 109b is preferably less than 0.4 eV from the viewpoint of reducing the interface resistance. In the present embodiment, as the upper metal electrode 108b, the work function (4) located between the work function (about 4.5 eV) of the lower metal electrode 107b and the work function (about 4.1 eV) of the N-type silicon electrode 109b. The tantalum carbide (TaCx) having about 0.2 eV) has been described. However, even if the work function is lower than the work function (about 4.1 eV) of the N-type silicon electrode 109b, Any material that can make the height of the Schottky barrier less than 0.4 eV (for example, a material having a work function of 3.9 eV) may be used. For example, in addition to the tantalum carbide (TaCx) described above, tantalum magnesium nitride (TaMgN), titanium (Ti), titanium magnesium nitride (TiMgN), titanium aluminum (TiAl), and titanium aluminum nitride as the constituent material of the upper metal electrode 108b (TiAlN), tungsten silicide (WSi), aluminum (Al), tantalum (Ta), silver (Ag), molybdenum (Mo), lanthanum (La), hafnium (Hf), zirconium (Zr), manganese (Mn), etc. Can be used.
上層金属電極１０８ａ、１０８ｂの好ましい膜厚は、以下の通りである。これらの下限の膜厚は、上層金属電極１０８ａ、１０８ｂとその上にそれぞれ形成されるＰ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂとの界面に形成されるショットキーバリアの高さが、上層金属電極１０８ａ、１０８ｂの下に形成される下層金属電極１０７ａ、１０７ｂによる影響を受けない程度に厚いことが必要であり、１．５ｎｍ以上であることが望ましい。
The preferable film thickness of the upper metal electrodes 108a and 108b is as follows. These lower limit film thicknesses are such that the height of the Schottky barrier formed at the interface between the upper metal electrodes 108a and 108b and the P-type silicon electrode 109a and the N-type silicon electrode 109b formed thereon, respectively, It must be thick enough not to be affected by the lower layer metal electrodes 107a and 107b formed under the electrodes 108a and 108b, and preferably 1.5 nm or more.
一方、上層金属電極１０８ａ、１０８ｂの上限の膜厚は、ゲート加工時の難易度を向上させない程度に薄いことが望ましく、１５ｎｍ以下であることが望ましい。すなわち、上層金属電極１０８ａ、１０８ｂの膜厚は、１．５ｎｍ以上且つ１５ｎｍ以下であることが望ましい。
On the other hand, the upper limit metal thickness of the upper metal electrodes 108a and 108b is desirably thin enough not to improve the difficulty in gate processing, and is desirably 15 nm or less. That is, it is desirable that the film thickness of the upper metal electrodes 108a and 108b is 1.5 nm or more and 15 nm or less.
また、各下層金属電極１０７ａ、１０７ｂの構成材料は、窒化タンタル（ＴａＮ）に限定されない。本発明は、上述したように、下層金属電極１０７ａ、１０７ｂとその上のＰ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂとをそれぞれ接触させた場合に生じるショットキーバリアの高さを小さくして、界面抵抗の低減を図るために、両者の界面に上層金属電極１０８ａ、１０８ｂを設ける構成を特徴とする。従って、Ｐ型ＦＥＴの場合は、下層金属電極１０７ａを構成する金属又は金属化合物の仕事関数がＰ型シリコン電極１０９ａを構成するＰ型ポリシリコンの仕事関数よりも小さいという関係を有する材料を下層金属電極１０７ａに用いる場合に、本発明が有効となる。同様に、Ｎ型ＦＥＴの場合は、下層金属電極１０７ｂを構成する金属又は金属化合物の仕事関数がＮ型シリコン電極１０９ｂを構成するＮ型ポリシリコンの仕事関数よりも大きいという関係を有する材料を下層金属電極１０７ｂに用いる場合に、本発明が有効となる。特に、下層金属電極１０７ａ、１０７ｂとその上の各シリコン電極１０９ａ、１０９ｂとのそれぞれの構成材料による仕事関数の差、すなわちショットキーバリアの高さが０．４ｅＶ以上生じる場合に、本発明はより効果的である。
Further, the constituent material of each lower layer metal electrode 107a, 107b is not limited to tantalum nitride (TaN). As described above, the present invention reduces the height of the Schottky barrier generated when the lower metal electrodes 107a and 107b are brought into contact with the P-type silicon electrode 109a and the N-type silicon electrode 109b, respectively, In order to reduce the interface resistance, the upper metal electrodes 108a and 108b are provided at the interface between them. Therefore, in the case of a P-type FET, a material having a relationship that the work function of the metal or metal compound constituting the lower layer metal electrode 107a is smaller than the work function of P type polysilicon constituting the P type silicon electrode 109a is used as the lower layer metal. The present invention is effective when used for the electrode 107a. Similarly, in the case of an N-type FET, a material having a relationship that the work function of the metal or metal compound constituting the lower metal electrode 107b is larger than the work function of the N-type polysilicon constituting the N-type silicon electrode 109b is used as the lower layer. The present invention is effective when used for the metal electrode 107b. In particular, when the difference in work function between the lower layer metal electrodes 107a and 107b and the respective silicon electrodes 109a and 109b thereon, that is, the height of the Schottky barrier is 0.4 eV or more, the present invention is more effective. It is effective.
また、各下層金属電極１０７ａ、１０７ｂの膜厚は、これらの上に形成される上層金属電極１０８ａ、１０８ｂによるしきい値電圧（Ｖｔ）変動等の特性変動を抑制するため、１．５ｎｍ以上であることが望ましい。
In addition, the thickness of each lower layer metal electrode 107a, 107b is 1.5 nm or more in order to suppress characteristic variation such as threshold voltage (Vt) variation due to upper layer metal electrodes 108a, 108b formed thereon. It is desirable to be.
さらに、下層金属電極１０７ａ、１０７ｂは、上記のように単層である必要はなく、積層構造を有していてもよい。この場合、積層構造における最上層の金属材料がＰ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂとの界面抵抗を決めるため、最上層の金属材料とシリコン電極との間のショットキーバリアの高さを低減する材料からなる上層金属電極１０８ａ、１０８ｂを選択すればよい。
Furthermore, the lower layer metal electrodes 107a and 107b do not have to be a single layer as described above, and may have a laminated structure. In this case, since the uppermost metal material in the stacked structure determines the interface resistance between the P-type silicon electrode 109a and the N-type silicon electrode 109b, the height of the Schottky barrier between the uppermost metal material and the silicon electrode is set. The upper metal electrodes 108a and 108b made of a material to be reduced may be selected.
なお、図１に示すように、ゲート絶縁膜１０６ａ、１０６ｂの上に形成される下層金属電極１０７ａ、１０７ｂは、同一の材料で構成されることが望ましい。
As shown in FIG. 1, it is desirable that the lower metal electrodes 107a and 107b formed on the gate insulating films 106a and 106b are made of the same material.
また、Ｐ型シリコン電極１０９ａの下部及びＮ型シリコン電極１０９ｂの下部における各不純物濃度は、上記の例に限定されない。シリコンと金属との界面抵抗の値は、ショットキーバリアの高さと不純物濃度との組み合わせによって決定される。従って、ショットキーバリアの高さを小さくすることができれば、不純物濃度は小さくてもよい。逆に、ショットキーバリアの高さを十分に小さくすることができなければ、不純物濃度を可能な限り高くすることが望ましい。特に、Ｐ型シリコン電極１０９ａの下部及びＮ型シリコン電極１０９ｂの下部における不純物濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上且つ２×１０２０ａｔｏｍｓ／ｃｍ３以下である場合に、本発明は効果的である。
The impurity concentrations at the lower part of the P-type silicon electrode 109a and the lower part of the N-type silicon electrode 109b are not limited to the above example. The value of the interface resistance between silicon and metal is determined by the combination of the height of the Schottky barrier and the impurity concentration. Therefore, the impurity concentration may be small if the height of the Schottky barrier can be reduced. Conversely, if the height of the Schottky barrier cannot be made sufficiently small, it is desirable to increase the impurity concentration as much as possible. In particular, the present invention is effective when the impurity concentration in the lower part of the P-type silicon electrode 109a and the lower part of the N-type silicon electrode 109b is 1 × 10 19 atoms / cm 3 or more and 2 × 10 20 atoms / cm 3 or less. It is.
また、Ｐ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂには、ボロン（Ｂ）等の不純物の固溶限界を向上できる、ゲルマニウム（Ｇｅ）を含むポリシリコン、すなわちポリシリコンゲルマニウムを用いることができる。
Further, for the P-type silicon electrode 109a and the N-type silicon electrode 109b, polysilicon containing germanium (Ge) that can improve the solid solution limit of impurities such as boron (B), that is, polysilicon germanium can be used.
なお、図１に示したように、Ｐ型ＦＥＴには、ゲート電極１１３ａに上層金属電極１０８ａを設け、Ｎ型ＦＥＴには、ゲート電極１１３ｂに上層金属電極１０８ｂを設けたが、これら上層金属電極１０８ａ、１０８ｂは必ずしも双方のＦＥＴに設ける必要はない。例えば、下層金属電極１０７ａ、１０７ｂとして、仕事関数が４．９ｅＶ程度であるタングステン（Ｗ）等の、仕事関数が比較的に大きい材料を用いた場合は、Ｐ型ＦＥＴにおける下層金属電極１０７ａとＰ型シリコン電極１０９ａとによって形成されるショットキーバリアの高さは０．２ｅＶ程度と小さくなる。このため、Ｐ型ＦＥＴに対しては、上層金属電極１０８ａは必ずしも設ける必要はない。すなわち、Ｐ型ＦＥＴにおいては、下層金属電極１０７ａを構成する金属又は金属化合物とＰ型シリコン電極１０９ａを構成するＰ型ポリシリコンとの間のショットキーバリアの高さが０．４ｅＶ未満であれば、上層金属電極１０８ａを設ける必要はない。
As shown in FIG. 1, the P-type FET is provided with the upper metal electrode 108a on the gate electrode 113a, and the N-type FET is provided with the upper metal electrode 108b on the gate electrode 113b. 108a and 108b are not necessarily provided in both FETs. For example, when a material having a relatively large work function such as tungsten (W) having a work function of about 4.9 eV is used as the lower layer metal electrodes 107a and 107b, the lower layer metal electrodes 107a and P in the P-type FET are used. The height of the Schottky barrier formed by the type silicon electrode 109a is as small as about 0.2 eV. Therefore, the upper metal electrode 108a is not necessarily provided for the P-type FET. That is, in the P-type FET, if the height of the Schottky barrier between the metal or metal compound constituting the lower metal electrode 107a and the P-type polysilicon constituting the P-type silicon electrode 109a is less than 0.4 eV. It is not necessary to provide the upper metal electrode 108a.
一方、Ｎ型ＦＥＴの場合は、下層金属電極１０７ｂにタングステン（Ｗ）を用いると、ショットキーバリアの高さが０．８ｅＶ（＝４．９ｅＶ－４．１ｅＶ）程度と非常に大きくなる。このため、Ｎ型ＦＥＴにおいては、ゲート電極１１３ｂに上層金属電極１０８ｂを設けることにより、下層金属電極１０７ｂとＮ型シリコン電極１０９ｂとの界面抵抗を効果的に低減することができるようになる。
On the other hand, in the case of an N-type FET, if tungsten (W) is used for the lower layer metal electrode 107b, the height of the Schottky barrier becomes as large as about 0.8 eV (= 4.9 eV-4.1 eV). For this reason, in the N-type FET, by providing the upper metal electrode 108b on the gate electrode 113b, the interface resistance between the lower metal electrode 107b and the N-type silicon electrode 109b can be effectively reduced.
同様に、仕事関数が４．１ｅＶ程度であるアルミニウム（Ａｌ）等の、仕事関数が比較的に小さい材料を下層金属電極１０７ａ、１０７ｂに用いる場合は、Ｐ型ＦＥＴにのみ上層金属電極１０８ａを設けることにより、効果的に界面抵抗を低減することが可能となる。すなわち、Ｎ型ＦＥＴにおいては、下層金属電極１０７ｂを構成する金属又は金属化合物とＮ型シリコン電極１０９ｂを構成するＮ型ポリシリコンとの間のショットキーバリアの高さが０．４ｅＶ未満であれば、上層金属電極１０８ｂを設ける必要はない。
Similarly, when a material having a relatively small work function such as aluminum (Al) having a work function of about 4.1 eV is used for the lower layer metal electrodes 107a and 107b, the upper layer metal electrode 108a is provided only for the P-type FET. As a result, the interface resistance can be effectively reduced. That is, in the N-type FET, if the height of the Schottky barrier between the metal or metal compound constituting the lower metal electrode 107b and the N-type polysilicon constituting the N-type silicon electrode 109b is less than 0.4 eV. It is not necessary to provide the upper metal electrode 108b.
（製造方法）
以下、一実施形態に係る半導体装置の製造方法について図３～図６を参照しながら説明する。 (Production method)
A method for manufacturing a semiconductor device according to an embodiment will be described below with reference to FIGS.
以下、一実施形態に係る半導体装置の製造方法について図３～図６を参照しながら説明する。 (Production method)
A method for manufacturing a semiconductor device according to an embodiment will be described below with reference to FIGS.
まず、図３（ａ）に示すように、シャロウトレンチ分離（Shallow Trench Isolation：ＳＴＩ）法等により、ボロン（Ｂ）等のＰ型の不純物を含むシリコン（Ｓｉ）からなる半導体基板１００の上部に、Ｐ型ＦＥＴ領域１０とＮ型ＦＥＴ領域２０とを区画する素子分離領域１０２を選択的に形成する。続いて、Ｐ型ＦＥＴ領域１０とＮ型ＦＥＴ領域２０とに、それぞれＮウェル領域１０１ａ及びＰウェル領域１０１ｂを形成する。その後、しきい値電圧調整用の不純物をＮウェル領域１０１ａ及びＰウェル領域１０１ｂにそれぞれドープすることにより、Ｐ型ＦＥＴ及びＮ型ＦＥＴにそれぞれ適した、不純物濃度がいずれも１×１０１７ａｔｏｍｓ／ｃｍ３程度のＮ型活性領域１０３ａ及びＰ型活性領域１０３ｂを素子分離領域１０２によって囲まれた領域内に形成する。
First, as shown in FIG. 3A, a shallow trench isolation (STI) method or the like is used to form an upper portion of a semiconductor substrate 100 made of silicon (Si) containing P-type impurities such as boron (B). The element isolation region 102 that partitions the P-type FET region 10 and the N-type FET region 20 is selectively formed. Subsequently, an N well region 101a and a P well region 101b are formed in the P type FET region 10 and the N type FET region 20, respectively. Thereafter, an impurity for adjusting the threshold voltage is doped into the N well region 101a and the P well region 101b, respectively, so that the impurity concentration suitable for the P type FET and the N type FET is 1 × 10 17 atoms / An N-type active region 103 a and a P-type active region 103 b of about cm 3 are formed in a region surrounded by the element isolation region 102.
次に、図３（ｂ）に示すように、各活性領域１０３ａ、１０３ｂの上に、ゲート絶縁膜形成用の、膜厚が１ｎｍのシリコン酸化膜１０４と、膜厚が２ｎｍのハフニウム酸化膜１０５とを順次堆積する。ここで、シリコン酸化膜１０４の形成には、例えば熱酸化法を用いることができ、ハフニウム酸化膜１０５の形成には、例えば化学気相堆積（Chemical Vapor Deposition：ＣＶＤ）法を用いることができる。続いて、ハフニウム酸化膜１０５の上に下層金属電極形成用の膜厚が５ｎｍのタンタル窒化（ＴａＮ）膜１０７を堆積する。続いて、タンタル窒化膜１０７の上に、後工程でハードマスクとして用いる、膜厚が３ｎｍのシリコン膜２０１を堆積する。
Next, as shown in FIG. 3B, a silicon oxide film 104 with a thickness of 1 nm and a hafnium oxide film 105 with a thickness of 2 nm for forming a gate insulating film are formed on the active regions 103a and 103b. Are sequentially deposited. Here, for example, a thermal oxidation method can be used to form the silicon oxide film 104, and a chemical vapor deposition (CVD) method can be used to form the hafnium oxide film 105, for example. Subsequently, a tantalum nitride (TaN) film 107 having a thickness of 5 nm for forming a lower metal electrode is deposited on the hafnium oxide film 105. Subsequently, on the tantalum nitride film 107, a silicon film 201 having a thickness of 3 nm, which is used as a hard mask in a later process, is deposited.
次に、図３（ｃ）に示すように、リソグラフィ法により、半導体基板１００の上にＮ型ＦＥＴ領域２０に開口パターンを有する第１のレジストパターン２０２を形成する。その後、第１のレジストパターン２０２をマスクとして、Ｎ型ＦＥＴ領域２０に形成されたシリコン膜２０１を除去する。具体的には、水酸化テトラメチルアンモニウム（Tetra Methyl Ammonium Hydroxide：ＴＭＡＨ）溶液により、シリコン膜２０１を除去する。これにより、Ｎ型ＦＥＴ領域２０において、シリコン膜２０１からタンタル窒化膜１０７を露出する。その後、第１のレジストパターン２０２を除去する。
Next, as shown in FIG. 3C, a first resist pattern 202 having an opening pattern in the N-type FET region 20 is formed on the semiconductor substrate 100 by lithography. Thereafter, the silicon film 201 formed in the N-type FET region 20 is removed using the first resist pattern 202 as a mask. Specifically, the silicon film 201 is removed with a tetramethylammonium hydroxide (Tetra Methyl Ammonium Hydroxide: TMAH) solution. As a result, the tantalum nitride film 107 is exposed from the silicon film 201 in the N-type FET region 20. Thereafter, the first resist pattern 202 is removed.
次に、図４（ａ）に示すように、半導体基板１００の上の全面に、すなわち、Ｐ型ＦＥＴ領域１０においてはシリコン膜２０１の上に、Ｎ型ＦＥＴ領域２０においてはタンタル窒化膜１０７の上に、Ｎ型ＦＥＴの上層金属電極となる、膜厚が２ｎｍのタンタル炭化（ＴａＣｘ）膜１０８Ｂと、後工程でハードマスクとして用いる膜厚が３ｎｍのシリコン膜２０３を順次堆積する。
Next, as shown in FIG. 4A, on the entire surface of the semiconductor substrate 100, that is, on the silicon film 201 in the P-type FET region 10 and on the tantalum nitride film 107 in the N-type FET region 20. A tantalum carbide (TaCx) film 108B having a film thickness of 2 nm and a silicon film 203 having a film thickness of 3 nm to be used as a hard mask in the subsequent process are sequentially deposited on the upper metal electrode of the N-type FET.
次に、図４（ｂ）に示すように、リソグラフィ法により、半導体基板１００の上に、Ｐ型ＦＥＴ領域１０に開口パターンを有する第２のレジストパターン２０４を形成する。その後、第２のレジストパターン２０４をマスクとして、Ｐ型ＦＥＴ領域１０に形成されたシリコン膜２０３、タンタル炭化膜１０８Ｂ及びシリコン膜２０１を順次除去する。具体的には、ＴＭＡＨ溶液によりシリコン膜２０３を除去し、続いて、アンモニア水過酸化水素水混合液（AmmoniahydrogenPeroxide Mixture：ＡＰＭ）によりタンタル炭化膜１０８Ｂを除去する。その後、ＴＭＡＨ溶液によりシリコン膜２０１を除去する。これにより、Ｐ型ＦＥＴ領域１０において、シリコン膜２０３及びタンタル炭化膜１０８Ｂからタンタル窒化膜１０７を露出する。ここで、第２のレジストパターン２０４に有機系のレジスト材料を用いると、ＡＰＭ処理中に除去されてしまうため、無機系のレジスト材料を用いることが望ましい。
Next, as shown in FIG. 4B, a second resist pattern 204 having an opening pattern in the P-type FET region 10 is formed on the semiconductor substrate 100 by lithography. Thereafter, the silicon film 203, the tantalum carbide film 108B, and the silicon film 201 formed in the P-type FET region 10 are sequentially removed using the second resist pattern 204 as a mask. Specifically, the silicon film 203 is removed with a TMAH solution, and then the tantalum carbide film 108B is removed with an ammonia water hydrogen peroxide solution mixture (APM). Thereafter, the silicon film 201 is removed with a TMAH solution. As a result, the tantalum nitride film 107 is exposed from the silicon film 203 and the tantalum carbide film 108B in the P-type FET region 10. Here, if an organic resist material is used for the second resist pattern 204, it is removed during the APM treatment, and therefore it is desirable to use an inorganic resist material.
次に、図４（ｃ）に示すように、第２のレジストパターン２０４を除去した後、半導体基板１００の上の全面に、すなわち、Ｐ型ＦＥＴ領域１０においてはタンタル窒化膜１０７の上に、Ｎ型ＦＥＴ領域２０においてはシリコン膜２０３の上に、Ｐ型ＦＥＴの上層金属電極となる、膜厚が２ｎｍのタンタル炭窒化酸化（ＴａＣＮＯ）膜１０８Ａを堆積する。
Next, as shown in FIG. 4C, after the second resist pattern 204 is removed, the entire surface of the semiconductor substrate 100, that is, the tantalum nitride film 107 in the P-type FET region 10 is formed. In the N-type FET region 20, a tantalum carbon oxynitride (TaCNO) film 108A having a film thickness of 2 nm is deposited on the silicon film 203 to serve as the upper metal electrode of the P-type FET.
次に、図５（ａ）に示すように、リソグラフィ法により、半導体基板１００の上に、Ｎ型ＦＥＴ領域２０に開口パターンを有する第３のレジストパターン２０５を形成する。その後、第３のレジストパターン２０５をマスクとして、Ｎ型ＦＥＴ領域２０に形成された、タンタル炭窒化酸化膜１０８Ａ及びシリコン膜２０３を順次除去する。具体的には、ＡＰＭによりタンタル炭窒化酸化膜１０８Ａを除去し、続いて、ＴＭＡＨ溶液によりシリコン膜２０３を除去する。これにより、Ｎ型ＦＥＴ領域２０において、タンタル炭窒化酸化膜１０８Ａ及びシリコン膜２０３からタンタル炭化膜１０８Ｂを露出する。ここで、第３のレジストパターン２０５に有機系のレジスト材料を用いると、ＡＰＭ処理中に除去されてしまうため、無機系のレジスト材料を用いることが望ましい。
Next, as shown in FIG. 5A, a third resist pattern 205 having an opening pattern in the N-type FET region 20 is formed on the semiconductor substrate 100 by lithography. Thereafter, using the third resist pattern 205 as a mask, the tantalum carbonitride oxide film 108A and the silicon film 203 formed in the N-type FET region 20 are sequentially removed. Specifically, the tantalum carbonitride oxide film 108A is removed by APM, and then the silicon film 203 is removed by a TMAH solution. As a result, in the N-type FET region 20, the tantalum carbide film 108B is exposed from the tantalum carbonitride oxide film 108A and the silicon film 203. Here, when an organic resist material is used for the third resist pattern 205, it is removed during the APM treatment, and therefore it is desirable to use an inorganic resist material.
次に、図５（ｂ）に示すように、第３のレジストパターン２０５を除去した後、半導体基板１００の上の全面に、すなわち、Ｐ型ＦＥＴ領域１０においてはタンタル炭窒化酸化膜１０８Ａの上に、Ｎ型ＦＥＴ領域２０においてはタンタル炭化膜１０８Ｂの上に、シリコン電極形成用であって、膜厚が１００ｎｍで不純物がドープされていないポリシリコン膜１０９を堆積する。なお、ポリシリコン膜１０９には、アンドープのポリシリコン膜を用いたが、ポリシリコンゲルマニウム膜を用いてもよい。
Next, as shown in FIG. 5B, after the third resist pattern 205 is removed, the entire surface of the semiconductor substrate 100, that is, in the P-type FET region 10, over the tantalum carbonitride oxide film 108A. In addition, in the N-type FET region 20, a polysilicon film 109 for forming a silicon electrode and having a film thickness of 100 nm and not doped with impurities is deposited on the tantalum carbide film 108B. Note that although an undoped polysilicon film is used as the polysilicon film 109, a polysilicon germanium film may be used.
次に、図５（ｃ）に示すように、Ｎ型ＦＥＴ領域２０を第４のレジストパターン（図示せず）でマスクして、ポリシリコン膜１０９のＰ型ＦＥＴ領域１０にボロン（Ｂ）を選択的にイオン注入することにより、Ｐ型ＦＥＴ領域１０のポリシリコン膜１０９をＰ型ポリシリコン膜１０９Ａとする。ここでのボロンのイオン注入は、加速エネルギーを３ｋｅＶとし、ドーズ量を４×１０1５ａｔｏｍｓ／ｃｍ２とする条件（注入深さＲｐ＋ΔＲｐ＝２５ｎｍ）により行う。続いて、第４のレジストパターンを除去した後、Ｐ型ＦＥＴ領域１０を第５のレジストパターン（図示せず）でマスクして、ポリシリコン膜１０９のＮ型ＦＥＴ領域２０にリン（Ｐ）を選択的にイオン注入することにより、Ｎ型ＦＥＴ領域２０のポリシリコン膜１０９をＮ型ポリシリコン膜１０９Ｂとする。ここでのリンのイオン注入は、加速エネルギーを８ｋｅＶとし、ドーズ量を４×１０１５ａｔｏｍｓ／ｃｍ２とする条件（注入深さＲｐ＋ΔＲｐ＝２５ｎｍ）により行う。その後、第５のレジストパターンを除去し、イオン注入によりドープされたＰ型ポリシリコン膜１０９Ａ及びＮ型ポリシリコン膜１０９Ｂに対して、アモルファス領域と結晶欠陥とを回復（結晶化）する、温度が７５０℃の窒素雰囲気で３０秒間のアニールを行う。なお、Ｐ型ポリシリコン膜１０９ＡとＮ型ポリシリコン膜１０９Ｂとの形成順序は特に問われない。
Next, as shown in FIG. 5C, the N-type FET region 20 is masked with a fourth resist pattern (not shown), and boron (B) is added to the P-type FET region 10 of the polysilicon film 109. By selectively implanting ions, the polysilicon film 109 in the P-type FET region 10 is changed to a P-type polysilicon film 109A. The ion implantation of boron here is performed under the conditions (implantation depth Rp + ΔRp = 25 nm) where the acceleration energy is 3 keV and the dose is 4 × 10 15 atoms / cm 2 . Subsequently, after removing the fourth resist pattern, the P-type FET region 10 is masked with a fifth resist pattern (not shown), and phosphorus (P) is added to the N-type FET region 20 of the polysilicon film 109. By selectively implanting ions, the polysilicon film 109 in the N-type FET region 20 is changed to an N-type polysilicon film 109B. Here, the ion implantation of phosphorus is performed under the conditions (implantation depth Rp + ΔRp = 25 nm) with an acceleration energy of 8 keV and a dose of 4 × 10 15 atoms / cm 2 . Thereafter, the fifth resist pattern is removed, and the amorphous region and crystal defects are recovered (crystallized) from the P-type polysilicon film 109A and the N-type polysilicon film 109B doped by ion implantation. Annealing is performed in a nitrogen atmosphere at 750 ° C. for 30 seconds. The order of forming the P-type polysilicon film 109A and the N-type polysilicon film 109B is not particularly limited.
次に、図６（ａ）に示すように、ドープされたＰ型ポリシリコン膜１０９Ａ及びＮ型ポリシリコン膜１０９Ｂの上に、各ゲート電極形成用の第６のレジストパターン（図示せず）を形成し、形成した第６のレジストパターンをマスクとして、Ｐ型ＦＥＴ領域１０においては、Ｐ型ポリシリコン膜１０９Ａ、タンタル炭窒化酸化膜１０８Ａ、タンタル窒化膜１０７、ハフニウム酸化膜１０５及びシリコン酸化膜１０４に対してドライエッチングを行って順次パターニングする。同様に、第６のレジストパターンをマスクとして、Ｎ型ＦＥＴ領域２０においては、Ｎ型ポリシリコン膜１０９Ｂ、タンタル炭化膜１０８Ｂ、タンタル窒化膜１０７、ハフニウム酸化膜１０５及びシリコン酸化膜１０４に対してドライエッチングを行って順次パターニングする。ここで、エッチングガスには、例えば塩素（Ｃｌ２）と臭化水素（ＨＢｒ）との混合ガスを用いることができる。
Next, as shown in FIG. 6A, a sixth resist pattern (not shown) for forming each gate electrode is formed on the doped P-type polysilicon film 109A and N-type polysilicon film 109B. Using the formed sixth resist pattern as a mask, in the P-type FET region 10, the P-type polysilicon film 109A, the tantalum carbonitride oxide film 108A, the tantalum nitride film 107, the hafnium oxide film 105, and the silicon oxide film 104 Then, dry etching is performed for patterning sequentially. Similarly, in the N-type FET region 20 using the sixth resist pattern as a mask, the N-type polysilicon film 109B, the tantalum carbide film 108B, the tantalum nitride film 107, the hafnium oxide film 105, and the silicon oxide film 104 are dry. Etching is performed to sequentially pattern. Here, as the etching gas, for example, a mixed gas of chlorine (Cl 2 ) and hydrogen bromide (HBr) can be used.
これにより、Ｐ型ＦＥＴ領域１０には、パターニングされたシリコン酸化膜１０４から下地絶縁膜１０４ａが形成され、パターニングされたハフニウム酸化膜１０５から高誘電率絶縁膜１０５ａが形成されて、下地絶縁膜１０４ａ及び高誘電率絶縁膜１０５ａからなるゲート絶縁膜１０６ａが形成される。また、パターニングされたタンタル窒化膜１０７から下層金属電極１０７ａが形成され、パターニングされたタンタル炭窒化酸化膜１０８Ａから上層金属電極１０８ａが形成される。また、パターニングされたＰ型ポリシリコン膜１０９ＡからＰ型シリコン電極１０９ａが形成されて、ゲート電極１１３ａを得る。
As a result, a base insulating film 104a is formed from the patterned silicon oxide film 104 in the P-type FET region 10, and a high dielectric constant insulating film 105a is formed from the patterned hafnium oxide film 105, thereby forming the base insulating film 104a. Then, a gate insulating film 106a made of the high dielectric constant insulating film 105a is formed. A lower metal electrode 107a is formed from the patterned tantalum nitride film 107, and an upper metal electrode 108a is formed from the patterned tantalum carbonitride oxide film 108A. Further, a P-type silicon electrode 109a is formed from the patterned P-type polysilicon film 109A to obtain a gate electrode 113a.
同様に、Ｎ型ＦＥＴ領域２０には、パターニングされたシリコン酸化膜１０４から下地絶縁膜１０４ｂが形成され、パターニングされたハフニウム酸化膜１０５から高誘電率絶縁膜１０５ｂが形成されて、下地絶縁膜１０４ｂ及び高誘電率絶縁膜１０５ｂからなるゲート絶縁膜１０６ｂが形成される。また、パターニングされたタンタル窒化膜１０７から下層金属電極１０７ｂが形成され、パターニングされたタンタル炭化膜１０８Ｂから上層金属電極１０８ｂが形成される。また、パターニングされたＮ型ポリシリコン膜１０９ＢからＮ型シリコン電極１０９ｂが形成され、ゲート電極１１３ｂを得る。なお、各ゲート電極１１３ａ、１１３ｂのゲート長寸法は、上述したように４０ｎｍとしている。
Similarly, in the N-type FET region 20, a base insulating film 104b is formed from the patterned silicon oxide film 104, and a high dielectric constant insulating film 105b is formed from the patterned hafnium oxide film 105 to form the base insulating film 104b. Then, a gate insulating film 106b made of the high dielectric constant insulating film 105b is formed. Further, the lower metal electrode 107b is formed from the patterned tantalum nitride film 107, and the upper metal electrode 108b is formed from the patterned tantalum carbide film 108B. Further, an N-type silicon electrode 109b is formed from the patterned N-type polysilicon film 109B to obtain a gate electrode 113b. The gate length of each gate electrode 113a, 113b is 40 nm as described above.
次に、図６（ｂ）に示すように、第６のレジストパターンを除去し、その後、Ｎ型ＦＥＴ領域２０をマスクする第７のレジストパターン（図示せず）を形成する。続いて、形成した第７のレジストパターン及びゲート電極１１３ａをマスクとして、Ｐ型ＦＥＴ領域１０におけるＮ型活性領域１０３ａに、二フッ化ボロン（ＢＦ２）をイオン注入する。これにより、Ｎ型活性領域１０３ａの上部であって、ゲート電極１１３ａの両側方の領域にＰ型エクステンション注入領域１１１Ａをそれぞれ形成する。ここで、二フッ化ボロンのイオン注入は、加速エネルギーを２ｋｅＶとし、ドーズ量を１×１０１５ａｔｏｍｓ／ｃｍ２とする条件（注入深さＲｐ＋ΔＲｐ＝４ｎｍ）で行う。
Next, as shown in FIG. 6B, the sixth resist pattern is removed, and then a seventh resist pattern (not shown) for masking the N-type FET region 20 is formed. Subsequently, boron difluoride (BF 2 ) is ion-implanted into the N-type active region 103a in the P-type FET region 10 using the formed seventh resist pattern and the gate electrode 113a as a mask. As a result, P-type extension implantation regions 111A are formed in regions on both sides of the gate electrode 113a on the N-type active region 103a. Here, boron difluoride ion implantation is performed under the conditions (the implantation depth Rp + ΔRp = 4 nm) in which the acceleration energy is 2 keV and the dose is 1 × 10 15 atoms / cm 2 .
続いて、第７のレジストパターンを除去し、その後、Ｐ型ＦＥＴ領域１０をマスクする第８のレジストパターン（図示せず）を形成する。続いて、形成した第８のレジストパターン及びゲート電極１１３ｂをマスクとして、Ｎ型ＦＥＴ領域２０における活性領域１０３ｂに、砒素（Ａｓ）をイオン注入する。これにより、Ｐ型活性領域１０３ｂの上部であって、ゲート電極１１３ｂの両側方の領域にＮ型エクステンション注入領域１１１Ｂをそれぞれ形成する。ここで、砒素のイオン注入は、加速エネルギーを２ｋｅＶとし、ドーズ量を１×１０１５ａｔｏｍｓ／ｃｍ２とする条件（注入深さＲｐ＋ΔＲｐ＝７ｎｍ）で行う。なお、Ｐ型ＦＥＴ領域１０におけるＰ型エクステンション注入領域１１１Ａの形成と、Ｎ型ＦＥＴ領域２０におけるＮ型エクステンション注入領域１１１Ｂの形成との順序は特に問われない。
Subsequently, the seventh resist pattern is removed, and then an eighth resist pattern (not shown) that masks the P-type FET region 10 is formed. Subsequently, arsenic (As) is ion-implanted into the active region 103b in the N-type FET region 20 using the formed eighth resist pattern and the gate electrode 113b as a mask. As a result, N-type extension implantation regions 111B are formed in regions on both sides of the gate electrode 113b on the P-type active region 103b. Here, the arsenic ion implantation is performed under the condition that the acceleration energy is 2 keV and the dose is 1 × 10 15 atoms / cm 2 (implantation depth Rp + ΔRp = 7 nm). The order of the formation of the P-type extension implantation region 111A in the P-type FET region 10 and the formation of the N-type extension implantation region 111B in the N-type FET region 20 are not particularly limited.
また、短チャネル特性の改善を図るために、Ｐ型エクステンション注入の前又は後に、Ｐ型ＦＥＴ領域１０にＮ型ポケット注入を行ってもよい。Ｎ型ポケット注入の条件は、例えば、砒素を加速エネルギーが３０ｋｅＶ、ドーズ量が３×１０１３ａｔｏｍｓ／ｃｍ２で、チルト角が１５°及びツイスト角が０°の４回転注入の条件下（注入深さＲｐ＋ΔＲｐ＝３０ｎｍ）で行う。同様に、Ｎ型エクステンション注入の前又は後に、Ｎ型ＦＥＴ領域２０にＰ型ポケット注入を行ってもよい。Ｐ型ポケット注入の条件は、例えば、ボロンを加速エネルギーが５ｋｅＶ、ドーズ量が３×１０１３ａｔｏｍｓ／ｃｍ２で、チルト角が１５°及びツイスト角が０°の４回転注入の条件下（注入深さＲｐ＋ΔＲｐ＝３０ｎｍ）で行う。その後、第８のレジストパターンを除去する。
In order to improve the short channel characteristics, N-type pocket implantation may be performed in the P-type FET region 10 before or after the P-type extension implantation. The conditions for the N-type pocket implantation are, for example, four-rotation implantation conditions in which arsenic has an acceleration energy of 30 keV, a dose of 3 × 10 13 atoms / cm 2 , a tilt angle of 15 °, and a twist angle of 0 ° (implantation). Depth Rp + ΔRp = 30 nm). Similarly, P-type pocket implantation may be performed in the N-type FET region 20 before or after the N-type extension implantation. The conditions for P-type pocket implantation are, for example, boron (acceleration energy of 5 keV, dose amount of 3 × 10 13 atoms / cm 2 , tilt angle of 15 ° and twist angle of 0 °, four-rotation implantation (implantation). Depth Rp + ΔRp = 30 nm). Thereafter, the eighth resist pattern is removed.
次に、図６（ｃ）に示すように、ＣＶＤ法により、各ゲート電極１１３ａ、１１３ｂを含む半導体基板１００の上に、膜厚が４０ｎｍ程度のシリコン窒化膜を形成する。その後、形成したシリコン窒化膜をドライエッチングにより全面的にエッチバックをすることにより、各ゲート電極１１３ａ、１１３ｂの側面上に幅が４０ｎｍ程度のシリコン窒化膜からなるサイドウォールスペーサ１１０ａ、１１０ｂをそれぞれ形成する。続いて、Ｎ型ＦＥＴ領域２０を覆う第９のレジストパターン（図示せず）を形成し、形成した第９のレジストパターンとゲート電極１１３ａ及びサイドウォールスペーサ１１０ａとをマスクとして、Ｐ型ＦＥＴ領域１０のＮ型活性領域１０３ａにボロンをイオン注入する。これにより、Ｎ型活性領域１０３ａにおけるゲート電極１１３ａの側方でＰ型エクステンション注入領域１１１Ａと接続されるＰ型のソース／ドレイン注入領域を形成する。ここで、ボロンのイオン注入は、加速エネルギーが３ｋｅＶで、ドーズ量が４×１０１５ａｔｏｍｓ／ｃｍ２の条件で行う。
Next, as shown in FIG. 6C, a silicon nitride film having a thickness of about 40 nm is formed on the semiconductor substrate 100 including the gate electrodes 113a and 113b by the CVD method. Thereafter, the formed silicon nitride film is etched back entirely by dry etching, thereby forming side wall spacers 110a and 110b made of a silicon nitride film having a width of about 40 nm on the side surfaces of the gate electrodes 113a and 113b, respectively. To do. Subsequently, a ninth resist pattern (not shown) that covers the N-type FET region 20 is formed, and the P-type FET region 10 is formed using the formed ninth resist pattern, the gate electrode 113a, and the sidewall spacer 110a as a mask. Boron ions are implanted into the N-type active region 103a. As a result, a P-type source / drain implantation region connected to the P-type extension implantation region 111A is formed on the side of the gate electrode 113a in the N-type active region 103a. Here, boron ion implantation is performed under the conditions of an acceleration energy of 3 keV and a dose of 4 × 10 15 atoms / cm 2 .
続いて、第９のレジストパターンを除去した後、Ｐ型ＦＥＴ領域１０を覆う第１０のレジストパターン（図示せず）を形成し、形成した第１０のレジストパターンとゲート電極１１３ｂ及びサイドウォールスペーサ１１０ｂとをマスクとして、Ｎ型ＦＥＴ領域２０のＰ型活性領域１０３ｂにリンをイオン注入する。これにより、Ｐ型活性領域１０３ｂにおけるゲート電極１１３ｂの側方でＮ型エクステンション注入領域１１１Ｂと接続されるＮ型のソース／ドレイン注入領域を形成する。ここで、リンのイオン注入は、加速エネルギーが８ｋｅＶで、ドーズ量が４×１０１５ａｔｏｍｓ／ｃｍ２の条件で行う。なお、Ｐ型ソース／ドレイン注入領域とＮ型ソース／ドレイン注入領域との形成順序は、特に問われない。
Subsequently, after removing the ninth resist pattern, a tenth resist pattern (not shown) covering the P-type FET region 10 is formed, and the formed tenth resist pattern, the gate electrode 113b, and the sidewall spacer 110b are formed. As a mask, phosphorus is ion-implanted into the P-type active region 103b of the N-type FET region 20. Thus, an N-type source / drain implantation region connected to the N-type extension implantation region 111B is formed on the side of the gate electrode 113b in the P-type active region 103b. Here, phosphorus ion implantation is performed under the conditions of an acceleration energy of 8 keV and a dose of 4 × 10 15 atoms / cm 2 . The order of forming the P-type source / drain implantation region and the N-type source / drain implantation region is not particularly limited.
続いて、第１０のレジストパターンを除去した後、温度が１０００℃のスパイクアニールを行うことにより、イオン注入により導入された不純物を活性化する。この活性化アニールにより、Ｐ型エクステンション注入領域１１１Ａのボロンが拡散して、Ｐ型エクステンション領域１１１ａが形成される。同時に、Ｎ型エクステンション注入領域１１１Ｂの砒素が拡散して、Ｎ型エクステンション領域１１１ｂが形成される。さらに、Ｐ型のソース／ドレイン注入領域のボロン、及びＮ型のソース／ドレイン注入領域のリンが拡散して、それぞれ、Ｐ型ソース／ドレイン領域１１２ａ及びＮ型ソース／ドレイン領域１１２ｂが形成される。なお、Ｐ型エクステンション領域１１１ａ、Ｎ型エクステンション領域１１１ｂ、Ｐ型ソース／ドレイン領域１１２ａ及びＮ型ソース／ドレイン領域１１２ｂにおける活性化アニール後の接合深さは、それぞれ２０ｎｍ及び８０ｎｍ程度である。
Subsequently, after removing the tenth resist pattern, spike annealing at a temperature of 1000 ° C. is performed to activate impurities introduced by ion implantation. By this activation annealing, boron in the P-type extension implantation region 111A is diffused to form a P-type extension region 111a. At the same time, arsenic in the N-type extension implantation region 111B is diffused to form the N-type extension region 111b. Further, boron in the P-type source / drain implantation region and phosphorus in the N-type source / drain implantation region are diffused to form a P-type source / drain region 112a and an N-type source / drain region 112b, respectively. . The junction depths after activation annealing in the P-type extension region 111a, the N-type extension region 111b, the P-type source / drain region 112a, and the N-type source / drain region 112b are about 20 nm and 80 nm, respectively.
このように、本実施形態に係る半導体装置の方法は、図６（ａ）に示したように、下層金属電極１０７ａ、１０７ｂとその上に形成されるＰ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂとの間に、それぞれ上層金属電極１０８ａ、１０８ｂを形成する工程を有していることを特徴とする。これにより、各下層金属電極１０７ａ、１０７ｂとその上のＰ型シリコン電極１０９ａ及びＮ型シリコン電極１０９ｂとをそれぞれ接触させた場合に形成される、ショットキーバリアの高さを低減することができる。その結果、各ゲート電極１１３ａ、１１３ｂにおける界面抵抗の低減、及びそれによる半導体集積回路の交流特性の劣化を抑制することが可能となる。
As described above, as shown in FIG. 6A, the method of the semiconductor device according to the present embodiment includes the lower metal electrodes 107a and 107b and the P-type silicon electrode 109a and the N-type silicon electrode 109b formed thereon. And a step of forming upper metal electrodes 108a and 108b, respectively. Thereby, the height of the Schottky barrier formed when the lower metal electrodes 107a and 107b are brought into contact with the P-type silicon electrode 109a and the N-type silicon electrode 109b thereon can be reduced. As a result, it is possible to reduce the interface resistance in each of the gate electrodes 113a and 113b and to suppress the deterioration of the alternating current characteristics of the semiconductor integrated circuit.
なお、上層金属電極１０８ａ、１０８ｂの形成方法は、特に限定しないが、膜厚のばらつきを低減するために、原子層堆積（Atomic Layer Deposition：ＡＬＤ）法によって形成することが望ましい。
Note that the method of forming the upper metal electrodes 108a and 108b is not particularly limited, but it is desirable to form the upper metal electrodes 108a and 108b by an atomic layer deposition (ALD) method in order to reduce variations in film thickness.
また、Ｐ型ＦＥＴにおいて、上層金属電極１０８ａとして、炭窒化酸化タンタル（ＴａＣＮＯ）を用いたが、炭窒化酸化タンタル（ＴａＣＮＯ）に限られず、上述したように、下層金属電極１０７ａよりも仕事関数が大きい材料を選択すればよい。また、Ｎ型ＦＥＴにおいては、上層金属電極１０８ｂとして、炭化タンタル（ＴａＣｘ）を用いたが、炭化タンタル（ＴａＣｘ）に限られず、上述したように、下層金属電極１０７ｂよりも仕事関数が小さい材料を選択すればよい。
In the P-type FET, tantalum carbonitride oxide (TaCNO) is used as the upper metal electrode 108a, but is not limited to tantalum carbonitride oxide (TaCNO), and as described above, the work function is higher than that of the lower metal electrode 107a. Choose a larger material. In the N-type FET, tantalum carbide (TaCx) is used as the upper metal electrode 108b, but is not limited to tantalum carbide (TaCx). As described above, a material having a work function smaller than that of the lower metal electrode 107b is used. Just choose.
また、本実施形態においては、Ｐ型ＦＥＴ及びＮ型ＦＥＴの両方に、界面抵抗を低減する上層金属電極１０８ａ、１０８ｂを形成しているが、いずれか一方のＦＥＴにのみ上層金属電極を形成してもよい。すなわち、下層金属電極とその上のシリコン電極との間に生じるショットキーバリアの高さが小さく、両者の界面抵抗の値が問題とならない程度に小さい場合は、界面抵抗の値が小さいＦＥＴには上層金属電極を設ける必要はない。
In this embodiment, the upper metal electrodes 108a and 108b for reducing the interface resistance are formed on both the P-type FET and the N-type FET. However, the upper metal electrode is formed only on one of the FETs. May be. That is, if the height of the Schottky barrier generated between the lower layer metal electrode and the silicon electrode on it is small and the interface resistance between the two is small enough not to cause a problem, an FET with a small interface resistance There is no need to provide an upper metal electrode.
本発明に係る半導体装置及びその製造方法は、金属電極と該金属電極の上に形成されたシリコン電極とを有するゲート電極を備えた電界効果型トランジスタを実現する際に、金属電極とシリコン電極との界面に生じる界面抵抗を低減することができ、良好な交流特性を要求される半導体集積回路装置等に有効である。
When a semiconductor device and a manufacturing method thereof according to the present invention realize a field effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, the metal electrode, the silicon electrode, This is effective for a semiconductor integrated circuit device or the like that requires good AC characteristics.
１０ Ｐ型ＦＥＴ領域
２０ Ｎ型ＦＥＴ領域
１００ 半導体基板
１０１ａ Ｎウェル領域
１０１ｂ Ｐウェル領域
１０２ 素子分離領域
１０３ａ Ｎ型活性領域
１０３ｂ Ｐ型活性領域
１０４ａ 下地絶縁膜
１０４ｂ 下地絶縁膜
１０４ シリコン酸化膜
１０５ａ 高誘電率絶縁膜
１０５ｂ 高誘電率絶縁膜
１０５ ハフニウム酸化膜
１０６ａ ゲート絶縁膜
１０６ｂ ゲート絶縁膜
１０７ａ 下層金属電極
１０７ｂ 下層金属電極
１０７ タンタル窒化膜
１０８ａ 上層金属電極
１０８Ａ タンタル炭窒化酸化（ＴａＣＮＯ）膜
１０８ｂ 上層金属電極
１０８Ｂ タンタル炭化（ＴａＣｘ）膜
１０９ａ Ｐ型シリコン電極
１０９ｂ Ｎ型シリコン電極
１０９Ａ Ｐ型ポリシリコン膜
１０９Ｂ Ｎ型ポリシリコン膜
１１０ａ サイドウォールスペーサ
１１０ｂ サイドウォールスペーサ
１１１ａ Ｐ型エクステンション領域
１１１Ａ Ｐ型エクステンション注入領域
１１１ｂ Ｎ型エクステンション領域
１１１Ｂ Ｎ型エクステンション注入領域
１１２ａ Ｐ型ソース／ドレイン領域
１１２ｂ Ｎ型ソース／ドレイン領域
１１３ａ ゲート電極
１１３ｂ ゲート電極
２０１ シリコン膜
２０２ 第１のレジストパターン
２０３ シリコン膜
２０４ 第２のレジストパターン
２０５ 第３のレジストパターン 10 P-type FET region 20 N-type FET region 100 Semiconductor substrate 101a N-well region 101b P-well region 102 Element isolation region 103a N-type active region 103b P-type active region 104a Underlying insulating film 104b Underlying insulating film 104 Silicon oxide film 105a High dielectric Insulating film 105b High dielectric constant insulating film 105 Hafnium oxide film 106a Gate insulating film 106b Gate insulating film 107a Lower metal electrode 107b Lower metal electrode 107 Tantalum nitride film 108a Upper metal electrode 108A Tantalum carbonitride oxide (TaCNO) film 108b Upper metal electrode 108B Tantalum carbonized (TaCx) film 109a P-type silicon electrode 109b N-type silicon electrode 109A P-type polysilicon film 109B N-type polysilicon film 110a Side wall spacer 110b Side wall Pacer 111a P-type extension region 111A P-type extension implantation region 111b N-type extension region 111B N-type extension implantation region 112a P-type source / drain region 112b N-type source / drain region 113a Gate electrode 113b Gate electrode 201 Silicon film 202 First Resist pattern 203 Silicon film 204 Second resist pattern 205 Third resist pattern
２０ Ｎ型ＦＥＴ領域
１００ 半導体基板
１０１ａ Ｎウェル領域
１０１ｂ Ｐウェル領域
１０２ 素子分離領域
１０３ａ Ｎ型活性領域
１０３ｂ Ｐ型活性領域
１０４ａ 下地絶縁膜
１０４ｂ 下地絶縁膜
１０４ シリコン酸化膜
１０５ａ 高誘電率絶縁膜
１０５ｂ 高誘電率絶縁膜
１０５ ハフニウム酸化膜
１０６ａ ゲート絶縁膜
１０６ｂ ゲート絶縁膜
１０７ａ 下層金属電極
１０７ｂ 下層金属電極
１０７ タンタル窒化膜
１０８ａ 上層金属電極
１０８Ａ タンタル炭窒化酸化（ＴａＣＮＯ）膜
１０８ｂ 上層金属電極
１０８Ｂ タンタル炭化（ＴａＣｘ）膜
１０９ａ Ｐ型シリコン電極
１０９ｂ Ｎ型シリコン電極
１０９Ａ Ｐ型ポリシリコン膜
１０９Ｂ Ｎ型ポリシリコン膜
１１０ａ サイドウォールスペーサ
１１０ｂ サイドウォールスペーサ
１１１ａ Ｐ型エクステンション領域
１１１Ａ Ｐ型エクステンション注入領域
１１１ｂ Ｎ型エクステンション領域
１１１Ｂ Ｎ型エクステンション注入領域
１１２ａ Ｐ型ソース／ドレイン領域
１１２ｂ Ｎ型ソース／ドレイン領域
１１３ａ ゲート電極
１１３ｂ ゲート電極
２０１ シリコン膜
２０２ 第１のレジストパターン
２０３ シリコン膜
２０４ 第２のレジストパターン
２０５ 第３のレジストパターン 10 P-type FET region 20 N-
Claims (18)
- 半導体基板における第１の活性領域に形成された第１導電型の第１の電界効果型トランジスタを備え、
前記第１の電界効果型トランジスタは、
前記第１の活性領域の上に形成された第１のゲート絶縁膜と、
前記第１のゲート絶縁膜の上に形成された第１のゲート電極とを有し、
前記第１のゲート電極は、前記第１のゲート絶縁膜の上に形成された第１の下層金属電極と、該第１の下層金属電極の上に形成された第１の上層金属電極と、該第１の上層金属電極の上に形成された第１のシリコン電極とを有し、
前記第１の上層金属電極を構成する金属又は金属化合物は、前記第１の上層金属電極を構成する金属又は金属化合物と前記第１のシリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、前記第１の下層金属電極を構成する金属又は金属化合物と前記第１のシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している半導体装置。 A first field effect transistor of a first conductivity type formed in a first active region of a semiconductor substrate;
The first field effect transistor includes:
A first gate insulating film formed on the first active region;
A first gate electrode formed on the first gate insulating film;
The first gate electrode includes a first lower metal electrode formed on the first gate insulating film, a first upper metal electrode formed on the first lower metal electrode, A first silicon electrode formed on the first upper metal electrode,
The metal or metal compound constituting the first upper metal electrode is formed between the metal or metal compound constituting the first upper metal electrode and silicon constituting the first silicon electrode. The Schottky barrier height of the second shot formed when the metal or metal compound constituting the first lower metal electrode and the silicon constituting the first silicon electrode are in direct contact with each other. A semiconductor device having a work function smaller than the height of a key barrier. - 請求項１において、
前記第１のショットキーバリアの高さは、０．４ｅＶ未満である半導体装置。 In claim 1,
The semiconductor device wherein the height of the first Schottky barrier is less than 0.4 eV. - 請求項１又は２において、
前記第２のショットキーバリアの高さは、０．４ｅＶ以上である半導体装置。 In claim 1 or 2,
A semiconductor device wherein the height of the second Schottky barrier is 0.4 eV or more. - 請求項１～３のうちいずれか１項において、
前記第１の上層金属電極の膜厚は、１．５ｎｍ以上且つ１５ｎｍ以下である半導体装置。 In any one of claims 1 to 3,
The first upper metal electrode has a thickness of 1.5 nm or more and 15 nm or less. - 請求項１～４のうちいずれか１項において、
前記第１の電界効果型トランジスタは、Ｎ型トランジスタであり、
前記第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、前記第１の下層金属電極を構成する金属又は金属化合物の仕事関数よりも小さい半導体装置。 In any one of claims 1 to 4,
The first field effect transistor is an N-type transistor,
A semiconductor device in which a work function of a metal or a metal compound constituting the first upper metal electrode is smaller than a work function of a metal or a metal compound constituting the first lower metal electrode. - 請求項１～５のうちいずれか１項において、
前記第１のシリコン電極は、Ｎ型シリコンからなり、
前記第１の上層金属電極は、炭化タンタル、窒化タンタルマグネシウム、チタン、窒化チタンマグネシウム、チタンアルミニウム、窒化チタンアルミニウム、タングステンシリサイド、アルミニウム、タンタル、銀、モリブデン、ランタン、ハフニウム、ジルコニウム又はマンガンからなる半導体装置。 In any one of claims 1 to 5,
The first silicon electrode is made of N-type silicon,
The first upper metal electrode is a semiconductor made of tantalum carbide, tantalum magnesium nitride, titanium, magnesium magnesium nitride, titanium aluminum, titanium aluminum nitride, tungsten silicide, aluminum, tantalum, silver, molybdenum, lanthanum, hafnium, zirconium, or manganese. apparatus. - 請求項１～４のうちいずれか１項において、
前記第１の電界効果型トランジスタは、Ｐ型トランジスタであり、
前記第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、前記第１の下層金属電極を構成する金属又は金属化合物の仕事関数よりも大きい半導体装置。 In any one of claims 1 to 4,
The first field effect transistor is a P-type transistor,
A semiconductor device in which a work function of a metal or a metal compound constituting the first upper metal electrode is larger than a work function of a metal or a metal compound constituting the first lower metal electrode. - 請求項１～４、７のうちいずれか１項において、
前記第１のシリコン電極は、Ｐ型シリコンからなり、
前記第１の上層金属電極は、炭窒化酸化タンタル、炭窒化タンタル、窒化チタン、タングステン白金シリサイド、炭化酸化タンタル、白金シリサイド、窒化タングステン、ニッケルシリサイド、窒化モリブデン、白金、ニッケル、パラジウム、金又はタングステンからなる半導体装置。 In any one of claims 1 to 4 and 7,
The first silicon electrode is made of P-type silicon,
The first upper metal electrode includes tantalum carbonitride oxide, tantalum carbonitride, titanium nitride, tungsten platinum silicide, tantalum carbide oxide, platinum silicide, tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold, or tungsten. A semiconductor device comprising: - 請求項１～６のうちいずれか１項において、
前記半導体基板における第２の活性領域に形成された第２導電型の第２の電界効果型トランジスタをさらに備え、
前記第２の電界効果型トランジスタは、
前記第２の活性領域の上に形成された第２のゲート絶縁膜と、
前記第２のゲート絶縁膜の上に形成された第２のゲート電極とを有し、
前記第２のゲート電極は、前記第２のゲート絶縁膜の上に形成された第２の下層金属電極と、該第２の下層金属電極の上に形成された第２の上層金属電極と、該第２の上層金属電極の上に形成された第２のシリコン電極とを有し、
前記第２の上層金属電極を構成する金属又は金属化合物は、前記第２の上層金属電極を構成する金属又は金属化合物と前記第２のシリコン電極を構成するシリコンとの間に形成される第３のショットキーバリアの高さが、前記第２の下層金属電極を構成する金属又は金属化合物と前記第２のシリコン電極を構成するシリコンとを直接に接触させた場合に形成される第４のショットキーバリアの高さよりも小さくなる仕事関数を有している半導体装置。 In any one of claims 1 to 6,
A second field-effect transistor of a second conductivity type formed in a second active region of the semiconductor substrate;
The second field effect transistor is:
A second gate insulating film formed on the second active region;
A second gate electrode formed on the second gate insulating film,
The second gate electrode includes a second lower metal electrode formed on the second gate insulating film, a second upper metal electrode formed on the second lower metal electrode, A second silicon electrode formed on the second upper metal electrode,
The metal or metal compound constituting the second upper metal electrode is a third metal formed between the metal or metal compound constituting the second upper metal electrode and silicon constituting the second silicon electrode. A fourth shot formed when the metal or metal compound constituting the second lower metal electrode and the silicon constituting the second silicon electrode are in direct contact with each other. A semiconductor device having a work function smaller than the height of a key barrier. - 請求項９において、
前記第３のショットキーバリアの高さは、０．４ｅＶ未満である半導体装置。 In claim 9,
The height of the third Schottky barrier is a semiconductor device less than 0.4 eV. - 請求項９又は１０において、
前記第４のショットキーバリアの高さは、０．４ｅＶ以上である半導体装置。 In claim 9 or 10,
The height of the fourth Schottky barrier is a semiconductor device of 0.4 eV or more. - 請求項９～１１のうちいずれか１項において、
前記第２の上層金属電極の膜厚は、１．５ｎｍ以上且つ１５ｎｍ以下である半導体装置。 In any one of claims 9 to 11,
The semiconductor device wherein the thickness of the second upper metal electrode is not less than 1.5 nm and not more than 15 nm. - 請求項９～１２のうちいずれか１項において、
前記第２の電界効果型トランジスタは、Ｐ型トランジスタであり、
前記第２の上層金属電極を構成する金属又は金属化合物の仕事関数は、前記第２の下層金属電極を構成する金属又は金属化合物の仕事関数よりも大きい半導体装置。 In any one of claims 9 to 12,
The second field effect transistor is a P-type transistor,
A semiconductor device in which a work function of a metal or a metal compound constituting the second upper metal electrode is larger than a work function of a metal or a metal compound constituting the second lower metal electrode. - 請求項９～１３のうちいずれか１項において、
前記第２のシリコン電極は、Ｐ型シリコンからなり、
前記第２の上層金属電極は、炭窒化酸化タンタル、炭窒化タンタル、窒化チタン、タングステン白金シリサイド、炭化酸化タンタル、白金シリサイド、窒化タングステン、ニッケルシリサイド、窒化モリブデン、白金、ニッケル、パラジウム、金又はタングステンからなる半導体装置。 In any one of claims 9 to 13,
The second silicon electrode is made of P-type silicon,
The second upper metal electrode is tantalum carbonitride oxide, tantalum carbonitride, titanium nitride, tungsten platinum silicide, tantalum carbide oxide, platinum silicide, tungsten nitride, nickel silicide, molybdenum nitride, platinum, nickel, palladium, gold or tungsten. A semiconductor device comprising: - 請求項９～１４のうちいずれか１項において、
前記第１の下層金属電極と前記第２の下層金属電極とは、同一の金属材料からなる半導体装置。 In any one of claims 9 to 14,
The first lower metal electrode and the second lower metal electrode are semiconductor devices made of the same metal material. - 請求項１～８のうちいずれか１項において、
前記半導体基板における第２の活性領域に形成された第２導電型の第２の電界効果型トランジスタをさらに備え、
前記第２の電界効果型トランジスタは、
前記第２の活性領域の上に形成された第２のゲート絶縁膜と、
前記第２のゲート絶縁膜の上に形成された第２のゲート電極とを有し、
前記第２のゲート電極は、前記第２のゲート絶縁膜の上に形成された第２の下層金属電極と、該第２の下層金属電極の上に接して形成された第２のシリコン電極とを有し、
前記第１の下層金属電極と前記第２の下層金属電極とは、同一の金属材料からなり、
前記第２の下層金属電極を構成する金属又は金属化合物と前記第２のシリコン電極を構成するシリコンとの間に形成される第５のショットキーバリアの高さは、０．４ｅＶ未満である半導体装置。 In any one of claims 1 to 8,
A second field-effect transistor of a second conductivity type formed in a second active region of the semiconductor substrate;
The second field effect transistor is:
A second gate insulating film formed on the second active region;
A second gate electrode formed on the second gate insulating film,
The second gate electrode includes a second lower metal electrode formed on the second gate insulating film, a second silicon electrode formed on and in contact with the second lower metal electrode, Have
The first lower metal electrode and the second lower metal electrode are made of the same metal material,
The height of the fifth Schottky barrier formed between the metal or metal compound constituting the second lower layer metal electrode and the silicon constituting the second silicon electrode is less than 0.4 eV apparatus. - 請求項１～１６のうちいずれか１項において、
前記第１の上層金属電極を構成する金属又は金属化合物の仕事関数は、前記第１の下層金属電極を構成する金属又は金属化合物の仕事関数と前記第１のシリコン電極を構成するシリコンの仕事関数との間に位置する半導体装置。 In any one of claims 1 to 16,
The work function of the metal or metal compound constituting the first upper layer metal electrode is the work function of the metal or metal compound constituting the first lower layer metal electrode and the work function of silicon constituting the first silicon electrode. Semiconductor device located between. - 半導体基板における第１の活性領域の上にゲート絶縁膜を形成する工程（ａ）と、
前記ゲート絶縁膜の上にゲート電極を形成する工程（ｂ）とを備え、
前記ゲート電極は、前記ゲート絶縁膜の上に形成された下層金属電極と、該下層金属電極の上に形成された上層金属電極と、該上層金属電極の上に形成されたシリコン電極とを有し、
前記上層金属電極を構成する金属又は金属化合物は、前記上層金属電極を構成する金属又は金属化合物と前記シリコン電極を構成するシリコンとの間に形成される第１のショットキーバリアの高さが、前記下層金属電極を構成する金属又は金属化合物と前記シリコン電極を構成するシリコンとを直接に接触させた場合に形成される第２のショットキーバリアの高さよりも小さくなる仕事関数を有している半導体装置の製造方法。 Forming a gate insulating film on the first active region in the semiconductor substrate;
And (b) forming a gate electrode on the gate insulating film,
The gate electrode includes a lower metal electrode formed on the gate insulating film, an upper metal electrode formed on the lower metal electrode, and a silicon electrode formed on the upper metal electrode. And
The metal or metal compound constituting the upper metal electrode has a height of a first Schottky barrier formed between the metal or metal compound constituting the upper metal electrode and silicon constituting the silicon electrode. It has a work function smaller than the height of the second Schottky barrier formed when the metal or metal compound constituting the lower metal electrode and the silicon constituting the silicon electrode are brought into direct contact with each other. A method for manufacturing a semiconductor device.
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