JP2006024587A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which a stable silicide film having low resistance can be formed. <P>SOLUTION: The method of manufacturing semiconductor device includes a step of forming a gate insulating film 5 on a semiconductor substrate 1, a step of forming a silicon film 7 on the gate insulating film 5, and a step of forming a source and a drain each composed of the gate electrode 11p of a p-channel MIS transistor Qp and a high-concentration n-type semiconductor region 15 by injecting BF<SB>2</SB>ions and B ions into the surfaces of the silicon film 7 and semiconductor substrate 1. The method also includes a step of forming a first cobalt silicide film above the gate electrode 11p and a second cobalt silicide film above the source and the drain. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a MIS (Metal Insulator Semiconductor) transistor in which cobalt silicide is formed.

Conventionally, in the step of forming the source / drain of the MIS transistor on the main surface of the semiconductor substrate (silicon substrate), ion implantation of arsenic (As) or phosphorus (P), which is an n-type impurity, is performed on the n-channel MIS transistor. Is used. Further, boron (B) or boron fluoride (BF ₂ ) ion implantation is used for the p-channel MIS transistor. The depth (concentration) of implanted ions from the surface of the semiconductor substrate depends on the ion implantation energy, the dose, and the annealing temperature after ion implantation.

In recent semiconductor devices that require miniaturization and high speed, the salicide process for MIS transistors is common. In the salicide process, the source / drain of the MIS transistor and the upper part of the gate electrode made of silicon are silicided in a self-aligned manner, the parasitic resistance of the element is reduced, and miniaturization and high-speed operation can be supported. For example, in Japanese translations of PCT publication No. 2003-530690, B ions and BF ₂ ions are implanted in a step of forming a p ⁺ region (high concentration p-type semiconductor region) having a low ohmic phase of titanium silicide obtained by siliciding titanium. There is a description of forming a source / drain (see Patent Document 1).
Special table 2003-530690 gazette

In the formation of titanium silicide, fluorine (F) ions contained in BF ₂ ions used for controlling the work function of the source / drain formation and the silicon gate electrode inhibit the formation of titanium silicide. For this reason, there is a problem that a stable low ohmic phase silicide film cannot be formed when the fluorine injection amount is large. Note that Japanese Patent Publication No. 2003-530690 discloses an injection means that combines BF ₂ ions and B ions as means for reducing the fluorine injection amount.

  On the other hand, with the miniaturization of semiconductor devices, there is a problem that the sheet resistance sharply increases (thin line effect) as the line width decreases and the parasitic resistance (wiring resistance) increases. It is possible that an effect has occurred.

  An object of the present invention is to provide a technique for forming a stable low-resistance silicide film, particularly a cobalt silicide film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The present invention includes (a) a step of forming a gate insulating film on a semiconductor substrate, (b) a step of forming a silicon film on the gate insulating film, (c) using the photolithography technique, the silicon film and Patterning the gate insulating film; (d) implanting BF ₂ ions and B ions into the surface of the patterned silicon film and the semiconductor substrate; and performing an activation process to form a gate electrode of a p-channel MIS transistor And (e) forming a cobalt film on the semiconductor substrate on which the gate electrode and the source / drain are formed, and (f) heat-treating the semiconductor substrate to form the gate. Forming a first cobalt silicide film on the electrode and forming a second cobalt silicide film on the source / drain; ) And it has a step of removing the cobalt film which has not reacted.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By forming cobalt silicide, which has a finer line effect than titanium silicide, even if the amount of fluorine injection is increased at the time of silicide formation, fluorine does not hinder the conversion to a low ohmic phase, so stable low resistance The silicide film can be formed.

  Further, the gate capacitance and threshold voltage of the MIS transistor can be controlled to desired values.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  A manufacturing process of the semiconductor device according to the present embodiment will be described with reference to the drawings. 1 to 9 are cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, a CMIS device.

  As shown in FIG. 1, for example, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared, and an element isolation region 2 is formed on the main surface of the semiconductor substrate 1. Form. The element isolation region 2 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.

  Next, the p-type well 3 is formed in the region for forming the n-channel type MIS transistor of the semiconductor substrate 1, and the n-type well 4 is formed in the region for forming the p-channel type MIS transistor. The p-type well 3 is ion-implanted with a p-type impurity such as boron (B), and the n-type well 4 is ion-implanted with an n-type impurity such as phosphorus (P) or arsenic (As). It is formed by performing heat treatment (annealing treatment) at about 0 ° C. and diffusing p-type impurities and n-type impurities.

Next, a shallow region (not shown) of the surface of the p-type well 3 that forms the channel region of the n-channel type MIS transistor, and a shallow region of the surface of the n-type well 4 that forms the channel region of the p-channel type MIS transistor In order to adjust the threshold voltage V _th of the n-channel MIS transistor and the p-channel MIS transistor (not shown), for example, boron (B) is used as a p-type impurity, and arsenic (As) is used as an n-type impurity. To perform ion implantation. The MIS transistor can be classified into an enhancement type and a depletion type, and the ion type closer to the conductivity type of the MIS transistor is ion-implanted as the depletion type is obtained.

Next, a gate insulating film 5 is formed on the surfaces of the p-type well 3 and the n-type well 4. The gate insulating film 5 is made of a silicon oxide film having a thickness of about 1.4 to 2.0 nm, for example, and can be formed by, for example, a thermal oxidation method. Note that when an insulating film having a high dielectric constant, such as a hafnium silicate (HfSiO _x ) film, is used as the gate insulating film 5, the equivalent oxide thickness (EOT) can be suppressed.

  Next, as shown in FIG. 2, a silicon film 7 having a thickness of, for example, about 120 to 200 nm is formed on the semiconductor substrate 1 by using a CVD (Chemical Vapor Deposition) method or the like. The silicon film 7 is made of, for example, a polycrystalline silicon (polysilicon) film or an amorphous silicon (amorphous silicon) film.

Next, pre-doping (Fermi level control) is performed only on the silicon film 7 serving as the gate electrode of the n-channel MIS transistor. In a general manufacturing process of a semiconductor device, an n-type impurity is formed in a region (silicon film 7 on the p-type well 3) in which a gate electrode of an n-channel MIS transistor is formed on the silicon film 7 by using a photolithography technique. In addition to ion implantation (for example, phosphorus), p-type impurity (for example, boron) ions are implanted into a region where the gate electrode of the p-channel MIS transistor is formed (silicon film 7 on the n-type well 4). Doping. However, in this embodiment, when p-type impurities are ion-implanted into the formation region of the high-concentration semiconductor region (source / drain), BF ₂ ions and B ions are simultaneously implanted into the gate electrode of the p-channel MIS transistor. Therefore, ion implantation of n-type impurities or the like is performed only on the silicon film 7 in the region where the gate electrode of the n-channel MIS transistor is formed.

That is, as shown in FIG. 3, after a resist film 18 is formed on a p-channel MIS transistor region by using a photolithography technique, ions containing F (for example, on the silicon film 7 in the n-channel MIS transistor region) , F ions alone or BF ₂ ions) and n-type impurity ions (for example, As or P) are combined to perform ion implantation.

  In this way, by performing ion implantation by combining F ions alone or ions containing F and n-type impurity ions during pre-doping (Fermi level control) to the gate electrode of the n-channel type MIS transistor, n-type impurity ions are implanted. The threshold value of the MIS transistor and the capacitance value of the n-type gate capacitor can be controlled.

In the present embodiment, after the silicon film 7 is formed on the semiconductor substrate 1, the silicon film 7 that becomes the gate electrode of the n-channel MIS transistor is pre-doped, but the high concentration, which is a later process, is performed. You may perform simultaneously with the ion implantation at the time of formation of a semiconductor region. That is, after patterning the silicon film 7, when an n-type impurity is ion-implanted into a region where a high concentration semiconductor region (source / drain) is formed, the gate electrode of the n-channel MIS transistor simultaneously contains ions containing F (for example, , F ions alone or BF ₂ ions) and n-type impurity ions can be implanted.

  Next, as shown in FIG. 4, the silicon film 7 is patterned (patterned, processed, selectively removed) by using a photolithography technique, a dry etching technique, or the like. For example, patterning can be performed using reactive ion etching (RIE). A pseudo gate electrode 11 is formed by the patterned silicon film 7. The gate electrode 11 becomes a gate electrode of the MIS transistor through a silicidation step (salicide step) described later.

  Next, as shown in FIG. 5, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode 11 of the p-type well 3 using photolithography technology. (A pair of) low-concentration n-type semiconductor regions 12 are formed in alignment with the gate electrode 11 of the p-type well 3, and p-type impurities such as boron (B) are formed in regions on both sides of the gate electrode 11 of the n-type well 4. By ion implantation, (a pair of) low-concentration p-type semiconductor regions 13 are formed in alignment with the gate electrode 11 of the n-type well 4. Subsequently, a heat treatment (annealing process) is performed at 950 ° C. for about 1 minute to activate the n-type impurity in the low-concentration n-type semiconductor region 12 and the p-type impurity in the low-concentration p-type semiconductor region 13. The low-concentration n-type semiconductor region 12 and the low-concentration p-type semiconductor region 13 are formed for forming an LDD (Lightly Doped Drain) region, that is, a source / drain extension region.

  Next, sidewalls (sidewall spacers, sidewall insulating films) 14 made of an insulator such as silicon nitride are formed on the sidewalls of the gate electrode 11. The sidewall 14 can be formed, for example, by depositing a silicon nitride film on the semiconductor substrate 1 and performing anisotropic dry etching on the silicon nitride film. The sidewalls 14 can also be formed from a silicon oxide film or a stacked film of a silicon oxide film and a silicon nitride film. This sidewall 14 suppresses silicidation on the side of the gate electrode 11 in a silicidation process described later, and prevents a short circuit with the semiconductor region (source / drain).

  After the formation of the sidewalls 14, (a pair of) high-concentration n-type semiconductor regions 15 (source / drain) are formed in regions on both sides of the gate electrode 11 and the sidewalls 14 of the p-type well 3 using photolithography technology. For example, an n-type impurity such as phosphorus or arsenic is ion-implanted to align with the sidewall 14 of the gate electrode 11 of the p-type well 3.

  Next, as shown in FIG. 6, after a resist film 17 is formed on the n-channel MIS transistor region by using a photolithography technique, (a pair of) high-concentration p-type semiconductor regions 16 (source / drain) are formed. The n-type well 4 is formed in alignment with the sidewalls 14 of the gate electrode 11 of the n-type well 4 by ion-implanting p-type impurities into regions on both sides of the gate electrode 11 and the sidewalls 14 of the n-type well 4.

The ion implantation into the regions (high-concentration p-type semiconductor region 16) on both sides of the gate electrode 11 and the side wall 14 of the n-type well 4 is first performed by BF ₂ boron fluoride capable of making the silicon film 7 amorphous. For example, at a concentration (dose amount) of about 5 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² , and then B (boron) ions are about 1.5 × 10 ^{15 to} 2.5 × 10 ¹⁵ cm ⁻² . The concentration (dose amount) is used. Ion implantation energy of BF ₂ ions and B ions, n-type concentration peak in the depth direction of the BF ₂ ions and B ions from the surface of the gate electrode 11 and the high-concentration p-type semiconductor region 16 of the well 4 is substantially equal to or, Alternatively, it is preferable to set the concentration peak of B ions to be smaller than the concentration peak of BF ₂ ions. For example, when the ion implantation energy of BF ₂ is about 20 to 30 keV, the ion implantation energy of B is about 4 to 7 keV.

In this way, when BF ₂ ions and B ions are successively implanted, the concentration of F (fluorine) ions implanted into the gate electrode of the p-channel MIS transistor is changed by changing the implantation ratio of the two ion species. Changes, and the electric insulating film capacitance value (gate capacitance value) changes. In the range of the above-described ion implantation conditions, the gate capacitance value that can be controlled by F ion implantation can be changed within a range of about 20 to 25%.

Therefore, the gate capacitance value (capacitance of the gate oxide film) of the p-channel type MIS transistor Qp is adjusted by adjusting the ratio of the implantation concentration of BF ₂ ions and B ions while keeping the total implantation amount of BF ₂ ions and B ions constant. Value) can be changed, and as a result, the threshold value of the p-channel MIS transistor Qp can be set to a desired value.

Further, by reducing the amount of F ions implanted into the gate insulating film, an increase in the diffusion coefficient of B ions can be suppressed. Therefore, the concentration peaks of BF ₂ ions and B ions in the depth direction from the surface of the gate electrode 11 of the n-type well 4 are substantially the same, or the concentration peaks of B ions are smaller than the concentration peaks of BF ₂ ions. Although set, B ion leakage to the channel region can be further suppressed. Therefore, since the decrease in carrier mobility can be prevented by suppressing B ion leakage, the driving current of the MIS transistor can be improved.

  Similarly, by reducing the amount of F ions implanted, B ion leakage into the channel region can be suppressed, and manufacturing variations in the threshold voltage of the MIS transistor due to nonuniform B ion leakage can be reduced. .

Next, after ion implantation, heat treatment (annealing) is performed at, for example, about 1000 ° C. in an inert gas (eg, N ₂ , Ar) atmosphere in order to activate the introduced impurities. When the silicon film 7 is an amorphous silicon film, the silicon film 7 made of an amorphous silicon film can become a polysilicon film by this heat treatment or the like. The high concentration n-type semiconductor region 15 has a higher impurity concentration than the low concentration n-type semiconductor region 12, and the high concentration p-type semiconductor region 16 has a higher impurity concentration than the low concentration p-type semiconductor region 13. As a result, an n-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the n-channel MIS transistor is formed by the low-concentration n-type semiconductor region 12 and the high-concentration n-type semiconductor region 15, and the p-channel MIS. A p-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the transistor is formed by the low-concentration p-type semiconductor region 13 and the high-concentration p-type semiconductor region 16.

  Next, as shown in FIG. 7, a cobalt (Co) film 21 is formed on the semiconductor substrate 1 including the silicon film 7, the high concentration n-type semiconductor region 15, and the high concentration p-type semiconductor region 16. For example, a cobalt film with a film thickness of about 6 to 10 nm can be formed using a sputtering method or the like. By forming a cobalt silicide film obtained by siliciding a cobalt (Co) film, heat resistance is superior to a nickel silicide film made of Ni (nickel), and a fine wire is made compared to a titanium silicide film made of Ti (titanium). The effect of the effect can be reduced.

  Next, as shown in FIG. 8, by performing heat treatment (first heat treatment, annealing treatment), the cobalt film 21, the silicon film 7 under the cobalt film 21, the high concentration n-type semiconductor region 15, and the high concentration p By reacting with the type semiconductor region 16, cobalt silicide films 22a, 22b, and 22c are formed. That is, by the heat treatment, the upper part of the silicon film 7 and the cobalt film 21 react to form a cobalt silicide film 22a, and the upper part of the high-concentration n-type semiconductor region 15 made of the silicon region into which the impurity is introduced and the cobalt film 21 are formed. A cobalt silicide film 22b is formed on the upper portion of the high-concentration n-type semiconductor region 15 by reaction, and the upper portion of the high-concentration p-type semiconductor region 16 made of a silicon region doped with impurities reacts with the cobalt film 21 to react with the high-concentration p. A cobalt silicide film 22 c is formed on the upper portion of the type semiconductor region 16.

  After silicidation by the first heat treatment (process for forming the cobalt silicide films 22a, 22b, and 22c), the unreacted cobalt film 21 is removed by, for example, wet etching. FIG. 8 shows a state where the unreacted cobalt film 21 is removed.

  Next, since the cobalt silicide films 22a, 22b, and 22c formed by the first heat treatment have a relatively high resistance, the heat resistance (second heat treatment and annealing treatment) is performed at a higher temperature than the first heat treatment, thereby reducing the low resistance. The cobalt silicide films 22a, 22b, and 22c are formed.

  By such a salicide process (salicide process), the cobalt silicide films 22a, 22b, and 22c are formed. In the present embodiment, the metal element constituting the cobalt silicide film 22a, the metal element constituting the cobalt silicide film 22b, and the metal element constituting the cobalt silicide film 22c are the same, and the metal constituting the cobalt film 21 is the same. Corresponds to the element.

Specifically, the case where a cobalt (Co) film is used in the salicide process will be described. For example, a first heat treatment (annealing process) is performed at a temperature of about 470 to 500 ° C. for about 30 seconds, and the cobalt silicide film 22a. , 22b, 22c are formed. Next, the unreacted cobalt film is removed by, for example, a solution containing hydrogen peroxide. Thereafter, for example, the cobalt silicide films 22a, 22b, and 22c subjected to the second heat treatment (annealing process) for about 60 seconds at a temperature of about 700 to 850 ° C. change the composition of CoSi so that CoSi has a lower resistance than CoSi. ₂

  In this way, the n-channel MIS transistor Qn is formed in the p-type well 3, and the p-channel MIS transistor Qp is formed in the n-type well 4. The gate electrode 11n of the n-channel MIS transistor Qn is formed of the silicon film 7 and a cobalt silicide film 22a formed by the reaction of the silicon film 7 and the cobalt film 21, and the gate electrode 11p of the p-channel MIS transistor Qp is The silicon film 7 and the cobalt silicide film 22a formed by the reaction between the silicon film 7 and the cobalt film 21 are formed. By forming the cobalt silicide film 22a having a low resistance (low resistivity) on the silicon film 7 constituting the gate electrodes 11n and 11p, the resistance of the gate electrodes 11n and 11p can be reduced.

  Further, a cobalt silicide film 22b is formed on the high concentration n-type semiconductor region 15 for the source or drain of the n-channel type MIS transistor Qn, and the high-concentration p-type semiconductor region for the source or drain of the p-channel type MIS transistor Qp. Since the cobalt silicide film 22c is formed on the upper portion of 16, diffusion resistance and contact resistance of the high-concentration n-type semiconductor region 15 and p-type semiconductor region 16 are reduced (source / drain resistance is reduced). be able to.

  Next, as shown in FIG. 9, an insulating film 31 is formed on the semiconductor substrate 1. That is, the insulating film 31 is formed on the semiconductor substrate 1 including the cobalt silicide films 22a, 22b, and 22c so as to cover the gate electrodes 11n and 11p. The insulating film 31 is made of, for example, a laminated film of a silicon nitride film and a relatively thick silicon oxide film thereon. The insulating film 31 can function as an interlayer insulating film. After the formation of the insulating film 31, planarization treatment of the upper surface of the insulating film 31 by CMP (Chemical Mechanical Polishing) method or the like can be performed as necessary.

  Next, the insulating film 31 is dry-etched using a photoresist pattern (not shown) formed on the insulating film 31 by photolithography as an etching mask, so that the high-concentration n-type semiconductor region 15 (source / drain) ), A contact hole (opening) 32 is formed in the high concentration p-type semiconductor region 16 (source / drain) or the upper portion of the gate electrodes 11n and 11p. At the bottom of the contact hole 32, a part of the main surface of the semiconductor substrate 1, for example, a part of the high-concentration n-type semiconductor region 15 (cobalt silicide film 22b on the surface thereof) and a surface of the high-concentration p-type semiconductor region 16 (on the surface). Part of the cobalt silicide film 22c) or part of the gate electrodes 11n and 11p (cobalt silicide film 22a) is exposed. In the cross-sectional view of FIG. 9, a part of the high-concentration n-type semiconductor region 15 (cobalt silicide film 22b on the surface thereof) and one of the high-concentration p-type semiconductor region 16 (cobalt silicide film 22c on the surface thereof). Are exposed at the bottom of the contact hole 32, but in a region (cross section) not shown, the contact hole 32 is also formed on the gate electrodes 11n, 11p, and the gate electrodes 11n, 11p (cobalt silicide film 22a). Is exposed at the bottom of the contact hole 32.

  Next, a plug 33 made of tungsten (W) or the like is formed in the contact hole 32. For example, the plug 33 is formed by forming a barrier film (for example, titanium nitride film) 33a on the insulating film 31 including the inside of the contact hole 32, and then contacting the tungsten film on the barrier film 33a by a CVD (Chemical Vapor Deposition) method or the like. It can be formed by filling the hole 32 and removing the unnecessary tungsten film and barrier film 33a on the insulating film 31 by a CMP method or an etch back method.

  Next, a wiring (first wiring layer) 34 is formed on the insulating film 31 in which the plug 33 is embedded. For example, a titanium film 34a, a titanium nitride film 34b, an aluminum film 34c, a titanium film 34d, and a titanium nitride film 34e are sequentially formed by a sputtering method or the like, and are patterned by using a photolithography method, a dry etching method, or the like. Can be formed. The aluminum film 34c is a conductor film mainly composed of aluminum such as aluminum (Al) alone or an aluminum alloy. The wiring 34 is connected via a plug 33 to the high-concentration n-type semiconductor region 15 for the source or drain of the n-channel MIS transistor Qn, the high-concentration p-type semiconductor region 16 for the source or drain of the p-channel MIS transistor Qp, n It is electrically connected to the gate electrode 11n of the channel type MIS transistor Qn or the gate electrode 11p of the p channel type MIS transistor Qp. The wiring 34 is not limited to the aluminum wiring as described above and can be variously changed. For example, the wiring 34 can be a tungsten wiring or a copper wiring (for example, a buried copper wiring formed by a damascene method). Thereafter, an interlayer insulating film, an upper wiring layer, and the like are further formed, but the description thereof is omitted here. The buried copper wiring formed by the damascene method can be used after the second layer wiring.

  The semiconductor device (CMIS device) of the present embodiment manufactured as described above includes MIS transistors such as an n-channel MIS transistor Qn and a p-channel MIS transistor Qp formed on the main surface of the semiconductor substrate 1. The gate electrodes 11n and 11p of these MIS transistors have a silicon film 7 formed on the gate insulating film 5 and a cobalt silicide film 22a formed on the silicon film 7. Cobalt silicide films 22b and 22c are formed on the high-concentration n-type semiconductor region 15 and the high-concentration p-type semiconductor region 16 as the source or drain of these MIS transistors. Therefore, since the cobalt silicide film is formed, the fine line effect can be prevented and the parasitic resistance (wiring resistance) of the gate electrode and the source / drain can be prevented as compared with the titanium silicide film in which titanium is used as the metal material of the silicide film. ) Can be prevented from increasing. Further, since the resistance of the gate electrodes 11n and 11p can be reduced by forming the cobalt silicide film 22a on the silicon film 7, the thickness of the silicon film 7 can be reduced. Moreover, since an increase in parasitic resistance can be prevented, the performance of the CMIS device (semiconductor device) can be improved.

  In the present embodiment, the cobalt silicide films 22a of the gate electrodes 11n and 11p are formed on the high-concentration n-type semiconductor region 15 and the high-concentration p-type semiconductor region 16 for the source or drain. Since it can be formed by the same process as the process to be performed (salicide process), the number of manufacturing processes can be reduced. For this reason, the manufacturing cost of the semiconductor device can also be reduced. Further, since the cobalt silicide film 22a can be formed on the silicon film 7 of the gate electrodes 11n and 11p using the salicide process, the manufacturing process of the semiconductor device is not complicated, and it is not necessary to introduce a new semiconductor manufacturing apparatus. . For this reason, the semiconductor device can be easily introduced into the production line.

  Moreover, since the drive current of the p-channel MIS transistor can be improved (increased), the performance of the CMIS device (semiconductor device) can be improved. Further, since the manufacturing variation of the threshold voltage of the p-channel type MIS transistor can be reduced, the manufacturing yield of the CMIS device (semiconductor device) can be improved.

Further, as shown in the present embodiment, by performing ion implantation on the gate electrode of the n-channel MIS transistor by combining F ions alone or ions containing F and n-type impurity ions, n-type is performed. It was possible to control the threshold value of the MIS transistor and the capacitance value of the gate capacitor. Further, the threshold value of the n-type MIS transistor and the capacitance value of the gate capacitor can be controlled by changing the implantation ratio of BF ₂ ions and B ions with respect to the gate electrode of the p-channel type MIS transistor. It was. Therefore, for example, a region where a MIS transistor is formed is selected by using a photolithography technique, and a semiconductor device including a MIS transistor (gate capacitor) having a gate capacitance of two levels or more and a threshold value of the MIS transistor is formed. You can also

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to semiconductor device manufacturing technology.

It is principal part sectional drawing in the manufacturing process of the semiconductor device in embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8;

Explanation of symbols

1 semiconductor substrate 2 element isolation region 3 p-type well 4 n-type well 5 gate insulating film 7 silicon film 7a silicon film 11 gate electrode 11n gate electrode 11p gate electrode 12 low-concentration n-type semiconductor region 13 low-concentration p-type semiconductor region 14 side Wall 15 High-concentration n-type semiconductor region 16 High-concentration p-type semiconductor region 17 Resist film 18 Resist film 21 Cobalt film 22a Cobalt silicide film 22b Cobalt silicide film 22c Cobalt silicide film 31 Insulating film 32 Contact hole 33 Plug 33a Barrier film 34 Wiring 34a Titanium film 34b Titanium nitride film 34c Aluminum film 34d Titanium film 34e Titanium nitride film Qn n-channel type MIS transistor Qp p-channel type MIS transistor

Claims (6)

A method of manufacturing a semiconductor device comprising the following steps:
(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) patterning the silicon film and the gate insulating film using a photolithography technique;
(D) A step of implanting BF ₂ ions and B ions into the surfaces of the patterned silicon film and the semiconductor substrate and then performing an activation process to form the gate electrode and the source / drain of the p-channel type MIS transistor ,
(E) forming a cobalt film on the semiconductor substrate on which the gate electrode and the source / drain are formed;
(F) heat-treating the semiconductor substrate, forming a first cobalt silicide film on the gate electrode, and forming a second cobalt silicide film on the source / drain;
(G) The process of removing the cobalt film which did not react. A method of manufacturing a semiconductor device including a CMIS device comprising a p-channel MIS transistor and an n-channel MIS transistor, comprising:
(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) Implanting n-type impurity ions into the silicon film in the n-channel MIS transistor region using photolithography technology;
(D) patterning the silicon film and the gate insulating film using a photolithography technique and an etching technique;
(E) BF ₂ ions and B ions are implanted into the surfaces of the patterned silicon film and semiconductor substrate in the p-channel MIS transistor region, and the patterned silicon film and semiconductor substrate in the n-channel MIS transistor region N-type impurity ions are implanted into the surface of the first and second electrodes, and an activation process is performed, and the first gate electrode and the first source / drain of the p-channel MIS transistor, the second gate electrode of the n-channel MIS transistor, Forming a second source / drain;
(F) forming a cobalt film on the semiconductor substrate on which the first gate electrode and the first source / drain and the second gate electrode and the second source / drain are formed;
(G) heat-treating the semiconductor substrate to form a first cobalt silicide film on the first gate electrode and the second gate electrode; and forming a second cobalt electrode on the first source / drain and the second source / drain. Forming a cobalt silicide film;
(H) The process of removing the cobalt film which did not react. A method of manufacturing a semiconductor device comprising the following steps:
(A) forming a gate insulating film on the semiconductor substrate;
(B) forming a silicon film on the gate insulating film;
(C) patterning the silicon film and the gate insulating film using a photolithography technique;
(D) Implanting F-containing ions and n-type impurity ions on the surfaces of the patterned silicon film and the semiconductor substrate, and then performing an activation process to form the gate electrode and source / drain of the n-channel MIS transistor. Forming step,
(E) forming a cobalt film on the semiconductor substrate on which the gate electrode and the source / drain are formed;
(F) heat-treating the semiconductor substrate, forming a first cobalt silicide film on the gate electrode, and forming a second cobalt silicide film on the source / drain;
(G) The process of removing the cobalt film which did not react. A method of manufacturing a semiconductor device according to claim 2,
In at least one of the steps (c) and (e), instead of implanting the n-type impurity ions, an ion containing F and an n-type impurity ion are implanted. A method of manufacturing a semiconductor device according to claim 1, 2, 3, or 4,
The heat treatment includes a first heat treatment and a second heat treatment, wherein the first heat treatment is 470 ° C. to 500 ° C., and the second heat treatment is 700 ° C. to 850 ° C. Production method. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method of manufacturing a semiconductor device, wherein the gate insulating film has a thickness equivalent to silicon oxide of 3.0 nm or less.

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