WO2010067483A1

WO2010067483A1 - Thin film transistor and method for manufacturing the thin film transistor

Info

Publication number: WO2010067483A1
Application number: PCT/JP2009/003499
Authority: WO
Inventors: 岡部達; 博彦錦
Original assignee: シャープ株式会社
Priority date: 2008-12-11
Filing date: 2009-07-24
Publication date: 2010-06-17

Abstract

Disclosed is a thin film transistor (TFT) (5a) comprising a substrate (10), a gate electrode (11) provided on the substrate (10), a gate insulating film (12) provided so as to cover the gate electrode (11), and a semiconductor layer (13) provided on the gate insulating film (12). The semiconductor layer (13) comprises a first silicon layer (13a) that has a channel part (C) provided so as to overlap with the gate electrode (11), and a source electrode (14a) and a drain electrode (14b) that are provided away from each other on the semiconductor layer (13) so as to expose the channel part (C). The semiconductor layer (13) further comprises an impurity-doped second silicon layer (13b) provided between the first silicon layer (13a) and the source and drain electrodes (14a, 14b). The first silicon layer (13a) has a low-concentration region (Ra) having a hydrogen content of not more than 3 atomic%.

Description

Thin film transistor and manufacturing method thereof

The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a bottom gate (inverse stagger) type thin film transistor and a manufacturing method thereof.

Thin film transistors (hereinafter referred to as TFTs) are widely used as switching elements for active matrix liquid crystal display panels and organic EL (electroluminescence) display panels.

FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.

As shown in FIG. 10, the TFT 105 corresponds to the gate electrode 111 provided on the glass substrate 110, the gate insulating film 112 provided so as to cover the gate electrode 111, and the gate electrode 111 on the gate insulating film 112. The semiconductor layer 113 provided in an island shape at a position where the source electrode 114a and the drain electrode 114b are provided so as to be separated from each other on the semiconductor layer 113. Here, for example, as shown in FIG. 10, the semiconductor layer 113 includes a lower intrinsic amorphous silicon layer 113a and an upper n ⁺ amorphous silicon layer 113b doped with phosphorus, and includes a source electrode 114a and a drain electrode. Intrinsic amorphous silicon layer 113a exposed from 114b constitutes channel portion C.

In making the TFT105, after forming the source electrode 114a and drain electrode 114b, the ^{n +} amorphous silicon film constituting the ^{n +} amorphous silicon layer 113b by performing channel etching for removing by dry etching, the channel section C is formed. Here, since the n ⁺ amorphous silicon film constituting the n ⁺ amorphous silicon layer 113b and the intrinsic amorphous silicon film constituting the intrinsic amorphous silicon layer 113a have similar film qualities, in the channel etching, It is difficult to increase the selectivity between the n ⁺ amorphous silicon film and the intrinsic amorphous silicon film. Also, in recent years, substrates constituting liquid crystal display panels and organic EL display panels, that is, substrates for forming TFTs are becoming larger and larger. For example, a TFT is formed on a large glass substrate having a side of 1500 mm or more. When forming the n ⁺ amorphous silicon film on the substrate, the variation in the film thickness, and the variation in the etching amount when removing a part of the n ⁺ amorphous silicon film by dry etching, The variation of the film thickness of the n ⁺ amorphous silicon layer becomes about ± 20% within the substrate surface. Therefore, in the manufacture of the conventional TFT, it is necessary to form an intrinsic amorphous silicon film that should be formed as thin as about 300 mm, so that it can be as thick as nearly 3000 mm. There is a problem in that the on-characteristics of the TFT are also lowered due to the silicon layer becoming a resistance component.

Therefore, for example, in Patent Document 1, a gate electrode, a gate insulating film, an operating semiconductor layer, an n-type impurity semiconductor layer, and a conductor layer are formed on a glass substrate, and the conductor layer and the n-type impurity semiconductor layer are etched. Then, in the method of manufacturing a liquid crystal display device having a TFT in which the upper layer of the operating semiconductor layer on the gate electrode is exposed to form a source electrode and a drain electrode, the conductor layer and the n-type impurity semiconductor layer are etched. And forming a residual layer on the glass substrate that is etched simultaneously. According to this, it is described that a liquid crystal display device having a channel etch type TFT having stable characteristics can be manufactured by reliably detecting the end point of channel etching.

JP 2002-151694 A

Here, in the manufacturing method disclosed in Patent Document 1, since the gate insulating film is exposed when the dummy residual film is removed, the n-type impurity semiconductor layer (n ⁺ amorphous silicon film) is used as the film thickness of the residual layer. Although it can be etched by the amount of time, it is not different from the method of determining the end point of channel etching by time, so as described above, the film thickness in the substrate surface at the time of forming the n ⁺ amorphous silicon film and at the time of dry etching In view of the variation of the above, it is difficult to reliably form TFTs having stable characteristics. Therefore, in the manufacture of TFT, in order to eliminate the root cause that the absolute end point of channel etching is not determined, the selection ratio at the time of dry etching of the intrinsic amorphous silicon film and the n ⁺ amorphous silicon film, that is, the semiconductor layer is formed. Therefore, it is desired to increase the selectivity during etching of the first silicon layer and the second silicon layer.

The present invention has been made in view of such a point, and an object of the present invention is to make the selectivity ratio of the first silicon layer and the second silicon layer constituting the semiconductor layer as high as possible. It is in.

In order to achieve the above object, according to the present invention, the first silicon layer has a low concentration region having a hydrogen content of 3 atomic% or less.

Specifically, a thin film transistor according to the present invention includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a channel provided on the gate insulating film so as to overlap the gate electrode. A semiconductor layer having a first silicon layer with a portion disposed thereon, and a source electrode and a drain electrode provided on the semiconductor layer and spaced apart from each other so that the channel portion is exposed, the semiconductor layer comprising: A thin film transistor having a second silicon layer doped with an impurity between the first silicon layer and the source and drain electrodes, wherein the first silicon layer has a low concentration of hydrogen content of 3 atomic% or less It has the area | region.

According to the above configuration, since the hydrogen content is 3 atomic% or less in the low concentration region of the first silicon layer, the hydrogen content (for example, about 10 atomic%) of the first silicon layer of the conventional thin film transistor. Is also low. Here, as shown in Table 1 below, the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n ⁺ amorphous silicon film formed by simply CVD. Obtained. According to this, for example, by suppressing the hydrogen content of at least a part (low concentration region) of the first silicon layer to 3 atomic% or less by laser annealing, the first silicon layer and the first silicon layer constituting the semiconductor layer are suppressed. It becomes possible to increase the selectivity during etching of the two silicon layers as much as possible.

In addition, instead of dry etching using hydrogen gas as a main component, each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method. Therefore, it is possible to increase the selectivity as in dry etching using hydrogen gas as a main component, so that it is not necessary to increase the thickness of an intrinsic amorphous silicon film as a sacrificial layer in the conventional manner. There is an advantage that tact time can be shortened and material cost can be reduced.

The low concentration region may be disposed on the entire first silicon layer.

According to the above configuration, since the low concentration region is disposed on the entire first silicon layer, formation of the second silicon layer exposed from the source electrode and the drain electrode is formed in order to form the second silicon layer and the channel portion. Even if the layer is removed by dry etching, the removal of the first silicon layer below the layer is specifically suppressed.

The film thickness of the first silicon layer may be 200 mm or more and 800 mm or less.

According to the above configuration, since the thickness of the first silicon layer is 200 mm or more and 800 mm or less, the first silicon layer has an appropriate film thickness to function as an intrinsic semiconductor layer. It becomes possible to improve.

The first silicon layer is disposed in the channel portion so as to correspond to the source electrode and the drain electrode on the outside of the low concentration region and the low concentration region, and has a higher hydrogen content than the low concentration region. And may have a region.

According to the above configuration, the low concentration region with a relatively low hydrogen content has a relatively high crystallinity, and the high concentration region with a relatively high hydrogen content has a relatively low crystallinity. The high-concentration region becomes a buffer region for relaxing the electric field between the low-concentration region and the source and drain electrodes, and the off-state current of the thin film transistor can be reduced.

The first silicon layer may have crystallinity.

According to the above configuration, since the first silicon layer has crystallinity, the mobility of the first silicon layer is increased to, for example, about 1 cm ² / Vs to 500 cm ² / Vs, and the first silicon layer In addition to the switching element provided in each pixel of the liquid crystal display panel or the organic EL display panel, a high-functional circuit such as a gate driver or a source driver can be configured.

The thin film transistor manufacturing method according to the present invention includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a gate insulating film provided on the gate insulating film so as to overlap the gate electrode. A semiconductor layer having a first silicon layer in which a channel portion is disposed, and a source electrode and a drain electrode provided on the semiconductor layer and spaced apart from each other so that the channel portion is exposed. A method of manufacturing a thin film transistor having a second silicon layer doped with an impurity between the first silicon layer and the source electrode and the drain electrode, wherein the first silicon film to be the first silicon layer is formed A low concentration region forming step for forming a low concentration region having a hydrogen content of 3 atomic% or less, and a substrate on which the low concentration region is formed, A semiconductor layer forming etching step of removing a part of the semiconductor layer forming layer to be the semiconductor layer by performing dry etching using an elementary gas or wet etching using an etchant containing hydrogen peroxide and fluorine. It is characterized by providing.

According to the above method, in the low concentration region forming step, the low concentration region having a hydrogen content of 3 atomic% or less is formed in the first silicon film to be the first silicon layer. The hydrogen content (for example, about 10 atomic%) of the first silicon layer of the thin film transistor is lower. Here, as shown in Table 1 below, the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n ⁺ amorphous silicon film formed by simply CVD. Obtained. According to this, in the low concentration region forming step, for example, the hydrogen content of at least a part (low concentration region) of the first silicon film is suppressed to 3 atomic% or less by laser annealing, and further, semiconductor layer formation etching is performed. By performing dry etching using hydrogen gas as a main component in the process, removal of the low-concentration region of the first silicon film is suppressed when removing a part of the semiconductor layer forming layer that becomes the semiconductor layer. It becomes possible to make the selection ratio of the first silicon layer and the second silicon layer constituting the semiconductor layer as high as possible.

In addition, instead of dry etching using hydrogen gas as a main component, each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method. Therefore, since it becomes possible to increase the selection ratio similarly to dry etching using hydrogen gas as a main component, it is not necessary to increase the thickness of the intrinsic amorphous silicon film as a sacrificial layer in advance as in the prior art, There is an advantage that production tact time can be shortened and material cost can be reduced.

In the low concentration region forming step, the low concentration region may be formed by irradiating the first silicon film with laser light.

According to the above method, since the low concentration region is formed by irradiating the first silicon film with the laser beam, the crystallinity of the low concentration region of the first silicon film can be improved. A high-performance thin film transistor having a mobility of about 1 cm ² / Vs to 500 cm ² / Vs can be manufactured.

In the low-concentration region forming step, the low-concentration region is formed in at least a region to be the channel portion of the first silicon film, and the second silicon layer is formed on the first silicon film in which the low-concentration region is formed. A source / drain formation step of forming the source electrode and the drain electrode after forming the second silicon layer formation layer, and the second silicon exposed from the source electrode and the drain electrode in the semiconductor layer formation etching step. The channel portion may be formed by removing the layer forming layer.

According to the above method, in the low concentration region forming step, the low concentration region is formed in at least the region to be the channel portion of the first silicon film, and in the source / drain forming step, the second silicon layer forming layer is formed in the low concentration region. After stacking, a source electrode and a drain electrode are formed thereon, and the second silicon layer formation layer exposed from the source electrode and the drain electrode is removed in the semiconductor layer formation etching step. To be manufactured.

In the low concentration region forming step, the low concentration region is formed in the first silicon layer forming layer that is the first silicon layer exposed from the source electrode and the drain electrode, and in the semiconductor layer forming etching step, the low concentration region is formed. By removing a part of the first silicon layer forming layer disposed outside the region, the channel portion is disposed corresponding to the source electrode and the drain electrode and has a higher hydrogen content than the low concentration region. A concentration region may be formed.

According to the above method, the low concentration region is formed in the first silicon layer forming layer exposed from the source electrode and the drain electrode in the low concentration region forming step, and is disposed outside the low concentration region in the semiconductor layer forming etching step. A part of the first silicon layer forming layer to be removed is removed to form a high concentration region in the channel portion. Here, the low concentration region having a relatively low hydrogen content has a relatively high crystallinity, and the high concentration region having a relatively high hydrogen content has a relatively low crystallinity. Becomes a buffer region for relaxing the electric field between the low concentration region and the source and drain electrodes, and a thin film transistor with reduced off-current is specifically manufactured.

The wavelength of the laser beam may be 248 nm or more and 355 nm or less.

According to the above method, since the wavelength of the laser beam applied to the first silicon film is not less than 248 nm and not more than 355 nm, even if the first silicon film is formed thin, the laser beam is transmitted through the first silicon film. Is suppressed, and a high-performance thin film transistor can be manufactured without damaging the gate electrode and the gate insulating film.

The substrate may be a rectangular glass substrate having a short side of 1500 mm or more.

According to the above method, since the substrate is a large glass substrate, the effects of the present invention are effectively exhibited.

According to the present invention, since the first silicon layer has a low concentration region with a hydrogen content of 3 atomic% or less, the etching selectivity of the first silicon layer and the second silicon layer constituting the semiconductor layer Can be made as high as possible.

FIG. 1 is a cross-sectional view of a TFT 5a according to the first embodiment. FIG. 2 is a flowchart for manufacturing the TFT 5a. FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step according to the first embodiment. FIG. 4 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the first embodiment. FIG. 5 is a cross-sectional view of the TFT 5b according to the second embodiment. FIG. 6 is a flowchart for manufacturing the TFT 5b. FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process according to the second embodiment. FIG. 8 is a cross-sectional view of the substrate in the low concentration region forming step according to the second embodiment. FIG. 9 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the second embodiment. FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 4 show a first embodiment of a thin film transistor (TFT) and a method for manufacturing the same according to the present invention. Specifically, FIG. 1 is a cross-sectional view of the TFT 5a of this embodiment.

As shown in FIG. 1, the TFT 5 a corresponds to the gate electrode 11 provided on the insulating substrate 10, the gate insulating film 12 provided so as to cover the gate electrode 11, and the gate electrode 11 on the gate insulating film 12. The semiconductor layer 13 is provided in an island shape at a position where the source electrode 14 a and the drain electrode 14 b are provided so as to be separated from each other on the semiconductor layer 13.

As shown in FIG. 1, the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13a provided as a first silicon layer and an upper phosphorus-doped n ⁺ amorphous silicon layer 13b provided as a second silicon layer. The intrinsic amorphous silicon layer 13a exposed from the source electrode 14a and the drain electrode 14b constitutes the channel portion C.

The entire intrinsic amorphous silicon layer 13a is a low concentration region Ra having a hydrogen content of 3 atomic% or less.

The TFT 5a having the above-described configuration is provided as a switching element connected to each pixel electrode of an active matrix substrate in which a plurality of pixel electrodes are arranged in a matrix, for example, and the active matrix substrate is opposed to the opposing one. A liquid crystal display panel is constituted with a substrate and a liquid crystal layer sealed between the two substrates.

Next, a manufacturing method of the TFT 5a of this embodiment will be described with reference to FIGS.

As shown in the flowchart of FIG. 2, the manufacturing method of the TFT 5a of this embodiment includes a gate electrode formation step, a GI / i-Si layer formation step, a low concentration region formation step, an n ⁺ -Si film formation step, an n ⁺ A Si layer forming step, a source / drain forming step, a semiconductor layer forming etching step, and a resist stripping step; Here, FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step of the present embodiment, and FIG. 4 is a cross-sectional view of the substrate in the semiconductor layer forming etching step of the present embodiment.

<Gate electrode formation step (St11)>
First, a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate (for example, 0.7 mm × 1500 mm × 1800 mm) by a sputtering method to a thickness of 3000 mm. Film is formed to the extent.

Subsequently, a photosensitive resin film is applied to the entire substrate on which the first metal film has been formed by spin coating, and then patterned to form a first resist pattern.

Further, after removing the first metal film exposed from the first resist pattern by dry etching, the first resist pattern is peeled off to form the gate electrode 11.

<GI / i-Si layer forming step (St12)>
First, a gate insulating film is formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm on the entire substrate on which the gate electrode 11 has been formed in the gate electrode formation step by a CVD (Chemical Vapor Deposition) method. 12 is formed.

Subsequently, an intrinsic amorphous silicon film is formed as a first silicon film with a thickness of about 200 to 800 mm on the entire substrate on which the gate insulating film 12 is formed by a CVD method. Here, since the intrinsic amorphous silicon film formed by the CVD method is generally formed by introducing silane gas or hydrogen gas into the reaction chamber, the hydrogen content is 10 atomic% or more.

Then, a second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film has been formed by spin coating, followed by patterning.

Further, after removing the intrinsic amorphous silicon film exposed from the second resist pattern by dry etching, the second resist pattern is peeled off to form an intrinsic amorphous silicon layer (13a).

<Low concentration region forming step (St13)>
As shown in FIG. 3, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer (13a) formed in the GI / i-Si layer forming process. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra. Here, in this embodiment, laser annealing is exemplified as a method for forming the low concentration region Ra, but lamp annealing, oven annealing, or the like may be used. For example, the ratio of H ₂ gas flow rate / SiH ₄ gas flow rate may be set. The CVD conditions may be set so that the film is formed at a temperature of 20 or more and the hydrogen content is lowered.

<N ⁺ -Si film formation step (St14)>
An n ⁺ amorphous silicon film doped with phosphorus as a second silicon film is formed to a thickness of about 500 mm on the entire substrate on which the low concentration region Ra has been formed in the low concentration region forming step by the CVD method. Here, since the n ⁺ amorphous silicon film is formed by introducing hydrogen gas as in the case of the intrinsic amorphous silicon film described above, the hydrogen content is 10 atomic% or more.

<N ⁺ -Si layer forming step (St15)>
First, a third resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the n ⁺ amorphous silicon film has been formed in the n ⁺ -Si film forming process by spin coating, followed by patterning. Form.

Subsequently, after removing the n ⁺ amorphous silicon film exposed from the third resist pattern by dry etching, the third resist pattern is peeled off to form a second silicon layer forming layer (semiconductor layer forming layer). , N ⁺ amorphous silicon layer forming layer 13ba is formed (see FIG. 4). Here, the n ⁺ amorphous silicon film can be easily formed by reactive dry etching using a fluorine-based gas such as sulfur hexafluoride gas or carbon tetrafluoride gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas. (See Table 1).

<Source / Drain Formation Step (St16)>
First, a second metal film such as an aluminum film, a copper film, or a titanium film is sputtered to a thickness of about 3000 mm on the entire substrate on which the n ⁺ amorphous silicon layer forming layer 13ba has been formed in the n ⁺ -Si layer forming step. The film is formed by

Subsequently, a photosensitive resin film is applied to the entire substrate on which the second metal film has been formed by spin coating, and then patterned to form a fourth resist pattern.

Further, the second metal film exposed from the fourth resist pattern is removed by dry etching to form the source electrode 14a and the drain electrode 14b (see FIG. 4).

<Semiconductor layer formation etching step (St17)>
As shown in FIG. 4, the n ⁺ amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is subjected to reactive ion etching or plasma using hydrogen gas as a main component. By removing with hydrogen radicals or hydrogen ions generated by dry etching such as etching, the n ⁺ amorphous silicon layer 13b is formed. Here, in the dry etching using hydrogen gas, the intrinsic amorphous silicon layer 13a having a hydrogen content of 3 atomic% or less is hardly removed by the generated hydrogen radicals or hydrogen ions because the hydrogen content is small. In the n ⁺ amorphous silicon layer forming layer 13ba whose amount is 10 atomic% or more, it is easily removed by the generated hydrogen radicals or hydrogen ions, and therefore between the intrinsic amorphous silicon layer 13a and the n ⁺ amorphous silicon layer forming layer 13ba. High selectivity can be realized.

Further, instead of the dry etching with hydrogen gas, the n ⁺ amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is oxidized as shown in FIG. Wet etching may be performed with an etchant containing hydrogen and fluorine and using a fluorine compound as a main component. Here, the fluorine compound is known to etch silicon, but the n ⁺ amorphous silicon layer having a high hydrogen content has a higher etching rate than the intrinsic amorphous silicon layer 13a having a low hydrogen content. In addition, it is not necessary to increase the thickness of the intrinsic amorphous silicon layer 13a. Further, since the fluorine compound can etch titanium metal, the source / drain formation step (St16) can be performed at the same time when a single layer or a multilayer wiring is used for the source / drain metal. There is an advantage that can be reduced.

<Resist stripping step (St18)>
The fourth resist pattern is peeled off from the substrate on which the n ⁺ amorphous silicon layer 13b is formed in the semiconductor layer formation etching step.

As described above, the TFT 5a of this embodiment can be manufactured.

As described above, according to the TFT 5a of this embodiment and the manufacturing method thereof, the low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer 13a in the low concentration region forming step. In the low concentration region Ra, the hydrogen content (for example, about 10 atomic%) of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower. Here, as shown in Table 1 above, the inventors of the present invention, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, as compared with an intrinsic amorphous silicon film or an n ⁺ amorphous silicon film formed simply by a CVD method. As shown in Table 2, for example, an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method. than or n ⁺ amorphous silicon film, peroxide And etch rate in wet etching to obtain a unique finding that slow using an etchant containing fluorine. According to this, in the low concentration region formation step, the hydrogen content of the intrinsic amorphous silicon layer 13a (low concentration region Ra) is suppressed to 3 atomic% or less by laser annealing, and in the semiconductor layer formation etching step, When the n ⁺ amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b is removed by performing dry etching using a gas or wet etching using an etchant containing hydrogen peroxide and fluorine, an intrinsic property is obtained. Since removal of the amorphous silicon layer 13a (low concentration region Ra) is suppressed, the intrinsic amorphous silicon layer 13a and the n ⁺ amorphous silicon layer 13b (n ⁺ amorphous silicon layer forming layer 13ba) constituting the semiconductor layer 13 are etched. Selectivity It can be increased retroactively.

Further, according to the TFT 5a of the present embodiment, since the film thickness of the intrinsic amorphous silicon layer 13a is not less than 200 mm and not more than 800 mm, the intrinsic amorphous silicon layer 13a has an appropriate film thickness to function as an intrinsic semiconductor layer. ON characteristics and productivity can be improved.

Further, according to the TFT5a of this embodiment, since the intrinsic amorphous silicon layer 13a has crystallinity, the mobility of the intrinsic amorphous silicon layer 13a is, for ^example, as high as ^{1cm 2 / Vs ~ 100cm 2 /} Vs Thus, the semiconductor layer 13 including the intrinsic amorphous silicon layer 13a can constitute not only a TFT provided in each pixel of a liquid crystal display panel or an organic EL display panel, but also a high function circuit such as a gate driver or a source driver.

In addition, according to the manufacturing method of the TFT 5a of the present embodiment, the wavelength of the laser light L applied to the intrinsic amorphous silicon layer 13a is not less than 248 nm and not more than 355 nm. Therefore, even if the intrinsic amorphous silicon layer 13a is formed thin. The transmission of the laser light L in the intrinsic amorphous silicon layer 13a is suppressed, and a high-performance TFT can be manufactured without damaging the gate electrode 11 and the gate insulating film 12.

<< Embodiment 2 of the Invention >>
FIG. 5 is a cross-sectional view of the TFT 5b of the second embodiment. In the following embodiments, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

Like the TFT 5a of the first embodiment, the TFT 5b includes a gate electrode 11 provided on the insulating substrate 10, a gate insulating film 12 provided so as to cover the gate electrode 11, and a gate, as shown in FIG. A semiconductor layer 13 provided in an island shape at a position corresponding to the gate electrode 11 on the insulating film 12, and a source electrode 14 c and a drain electrode 14 d provided on the semiconductor layer 13 so as to be separated from each other are provided.

As shown in FIG. 5, the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13c provided as a first silicon layer, and an upper phosphorus ⁺ doped n ⁺ amorphous silicon layer 13d provided as a second silicon layer. The intrinsic amorphous silicon layer 13c exposed from the source electrode 14c, the drain electrode 14d, and the n ⁺ amorphous silicon layer 13d constitutes the channel portion C.

The channel portion C of the intrinsic amorphous silicon layer 13c is disposed corresponding to the source electrode 14c and the drain electrode 14d on the outer side of the low concentration region Ra having a hydrogen content of 3 atomic% or less and the low hydrogen concentration. Has a high concentration region Rb of about 10 atomic%.

Next, a manufacturing method of the TFT 5b of this embodiment will be described with reference to FIGS.

The manufacturing method of the TFT 5b of this embodiment includes a TFT pattern forming step, a low concentration region forming step, and a hydrogen gas etching step (semiconductor layer forming etching step) as shown in the flowchart of FIG. Here, FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process of the present embodiment, FIG. 8 is a cross-sectional view of the substrate in the low-concentration region forming process of the present embodiment, and FIG. It is sectional drawing of the board | substrate in the hydrogen gas etching process of embodiment.

<TFT pattern forming step (St21)>
First, for example, a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate with a thickness of about 3000 mm by a sputtering method.

Thereafter, a gate insulating film 12 is formed on the entire substrate on which the gate electrode 11 has been formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm by a CVD (Chemical Vapor Deposition) method.

Subsequently, an intrinsic amorphous silicon film having a thickness of about 2000 mm is formed as a first silicon film on the entire substrate on which the gate insulating film 12 is formed by CVD, and then phosphorus is doped as the second silicon film. ⁺ Amorphous silicon film is formed with a thickness of about 500 mm.

A second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film and the n ⁺ amorphous silicon film are sequentially formed by spin coating, followed by patterning.

Further, after removing the intrinsic amorphous silicon film and the n ⁺ amorphous silicon film exposed from the second resist pattern by dry etching, the second resist pattern is peeled off to form a semiconductor layer forming layer.

Thereafter, a second metal film such as an aluminum film, a copper film, or a titanium film is formed by sputtering on the entire substrate on which the semiconductor layer forming layer has been formed by sputtering.

Subsequently, a photosensitive resin film is applied to the entire substrate on which the second metal film is formed by spin coating, and then patterned to form a third resist pattern.

Further, the second metal film exposed from the third resist pattern is removed by dry etching to form the source electrode 14c and the drain electrode 14d (see FIG. 7).

Thereafter, the upper layer portion of the n ⁺ amorphous silicon layer forming layer exposed from the source electrode 14c and the drain electrode 14d and the intrinsic amorphous silicon layer forming layer disposed below the n ⁺ amorphous silicon layer forming layer is made of fluorine such as sulfur hexafluoride gas or carbon tetrafluoride gas. The TFT pattern 15 is formed as shown in FIG. 7 by removing by reactive dry etching using a system gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas.

<Low concentration region forming step (St22)>
As shown in FIG. 8, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer forming layer 13ca of the TFT pattern 15 formed in the TFT pattern forming step. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra. Here, since the source electrode 14c and the drain electrode 14d are made of a highly reflective material such as an aluminum film or a silver film, the laser beam L is applied to the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d. Not irradiated. Therefore, the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d is not laser-annealed, so that the high concentration region Rb is formed outside the low concentration region Ra.

<Hydrogen gas etching process (St23)>
In the substrate on which the low concentration region Ra is formed in the low concentration region formation step, the n ⁺ amorphous silicon layer formation layer 13da exposed from the source electrode 14a and the drain electrode 14b and the intrinsic amorphous silicon layer formation layer 13ca disposed below the n ⁺ amorphous silicon layer formation layer 13ca For example, as shown in FIG. 9, a hydrogen plasma P generated by ionic dry etching using hydrogen gas as a main component is used for the upper layer portion by utilizing an isotropic high-density plasma etching apparatus using a coil or the like. Thus, the intrinsic amorphous silicon layer 13c and the n ⁺ amorphous silicon layer 13d are formed by removing. Here, in the ionic dry etching using hydrogen gas, the intrinsic amorphous silicon layer formation layer 13ca has a low hydrogen concentration of 3 atomic% or less, but the low concentration region Ra has low ionicity and is hardly removed. The high concentration region Rb having a hydrogen content of about 10 atomic% and the n ⁺ amorphous silicon layer forming layer 13ba having a hydrogen content of about 10 atomic% have high ionicity and are easily removed. As shown in FIG. 9, the amorphous silicon layer forming layer 13ca and the n ⁺ amorphous silicon layer da are removed by about 1 μm to the side.

As described above, the TFT 5b of this embodiment can be manufactured.

As described above, according to the TFT 5b and the manufacturing method thereof of the present embodiment, the hydrogen content in the intrinsic amorphous silicon layer forming layer 13ca to be the intrinsic amorphous silicon layer 13c is 3 atomic% or less in the low concentration region forming step. Since the low concentration region Ra is formed, the hydrogen concentration (for example, about 10 atomic%) of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower in the low concentration region Ra. Here, as in the first embodiment, for example, an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method. In the low-concentration region forming process, the unique knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component compared to an intrinsic amorphous silicon film or an n ⁺ amorphous silicon film. For example, a low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer forming layer 13ca exposed from the source electrode 14c and the drain electrode 14d by laser annealing. Dry etch using By removing a part of the semiconductor layer forming layer that becomes the semiconductor layer by forming the high concentration region Rb in the channel portion C, the low concentration region Ra of the intrinsic amorphous silicon layer forming layer 13ca is removed. Is suppressed, and the high concentration region Rb and the n ⁺ amorphous silicon layer formation layer da of the intrinsic amorphous silicon layer formation layer 13ca disposed outside the low concentration region Ra are removed, so that the intrinsic amorphous silicon layer constituting the semiconductor layer 13c is removed. The selection ratio during dry etching of 13c (intrinsic amorphous silicon layer forming layer 13ca) and n ⁺ amorphous silicon layer 13d (n ⁺ amorphous silicon layer forming layer 13da) can be made as high as possible.

Further, according to the TFT 5b and the manufacturing method thereof of the present embodiment, in the intrinsic amorphous silicon layer 13c, the low concentration region Ra having a relatively low hydrogen content has a relatively high crystallinity and a relatively high hydrogen content. Since the high concentration region Rb is relatively low in crystallinity, the high concentration region Rb becomes a buffer region for relaxing the electric field between the low concentration region Ra and the source electrode 14c and drain electrode 14d. The off current can be reduced.

In addition, according to the TFT 5b and the manufacturing method thereof of the present embodiment, the defect portion in the silicon generated after irradiation with the laser beam L can be terminated by hydrogen plasma, so that the TFT characteristics (mobility and off-current) are improved. Can be made.

In St23 of this embodiment, dry etching using hydrogen gas is performed, but wet etching using an etchant containing hydrogen peroxide and fluorine may be performed.

In each of the above embodiments, an n-channel TFT in which the second silicon layer is doped with phosphorus is exemplified, but the present invention is also applicable to a p-channel TFT in which the second silicon layer is doped with boron. Can do.

As described above, since the characteristics of the TFT can be improved, the present invention is useful for, for example, an active matrix liquid crystal display panel and an organic EL display panel.

C channel portion L laser beam P hydrogen plasma Ra low concentration region Rb high concentration region 5a, 5b TFT
DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 Gate electrode 12 Gate insulating film 13

Semiconductor layer

13a, 13c Intrinsic amorphous silicon layer (1st silicon layer, 1st silicon film)
13b, 13dn ⁺ amorphous silicon layer (second silicon layer)
13ba n ⁺ amorphous silicon layer formation layer (second silicon layer formation layer, semiconductor layer formation layer)
13ca Intrinsic amorphous silicon layer formation layer (first silicon layer formation layer, semiconductor layer formation layer)
13 dan ⁺ amorphous silicon layer forming layer (second silicon layer forming layer, semiconductor layer forming layer)
14a,

14c Source electrode

14b, 14d Drain electrode

Claims

A gate electrode provided on the substrate;
A gate insulating film provided to cover the gate electrode;
A semiconductor layer having a first silicon layer provided on the gate insulating film and having a channel portion disposed so as to overlap the gate electrode;
A source electrode and a drain electrode, which are provided on the semiconductor layer and spaced apart from each other so as to expose the channel portion;
The semiconductor layer is a thin film transistor having a second silicon layer doped with impurities between the first silicon layer and the source and drain electrodes,
The thin film transistor according to claim 1, wherein the first silicon layer has a low concentration region having a hydrogen content of 3 atomic% or less.
The thin film transistor according to claim 1,
The thin film transistor according to claim 1, wherein the low concentration region is disposed on the entire first silicon layer.
The thin film transistor according to claim 2,
The thin film transistor, wherein the first silicon layer has a thickness of 200 to 800 mm.
The thin film transistor according to claim 1,
The first silicon layer is disposed in the channel portion so as to correspond to the source electrode and the drain electrode on the outside of the low concentration region and the low concentration region, and has a higher hydrogen content than the low concentration region. A thin film transistor having a region.
The thin film transistor according to any one of claims 1 to 4,
The thin film transistor, wherein the first silicon layer has crystallinity.
A gate electrode provided on the substrate;
A gate insulating film provided to cover the gate electrode;
A semiconductor layer having a first silicon layer provided on the gate insulating film and having a channel portion disposed so as to overlap the gate electrode;
A source electrode and a drain electrode, which are provided on the semiconductor layer and spaced apart from each other so as to expose the channel portion;
A method of manufacturing a thin film transistor, wherein the semiconductor layer has a second silicon layer doped with impurities between the first silicon layer and the source and drain electrodes,
A low concentration region forming step of forming a low concentration region having a hydrogen content of 3 atomic% or less in the first silicon film to be the first silicon layer;
A semiconductor layer forming layer which becomes the semiconductor layer by performing dry etching using hydrogen gas or wet etching using an etchant containing hydrogen peroxide and fluorine on the substrate on which the low concentration region is formed A method for producing a thin film transistor, comprising: a semiconductor layer forming etching step for removing a part of the semiconductor layer.
In the manufacturing method of the thin-film transistor according to claim 6,
In the low concentration region forming step, the low concentration region is formed by irradiating the first silicon film with a laser beam.
In the manufacturing method of the thin-film transistor described in Claim 6 or 7,
In the low-concentration region forming step, the low-concentration region is formed in a region that becomes at least the channel portion of the first silicon film,
A source drain forming step of forming the source electrode and the drain electrode after forming a second silicon layer forming layer to be the second silicon layer on the first silicon film in which the low concentration region is formed;
In the semiconductor layer formation etching step, the channel portion is formed by removing the second silicon layer formation layer exposed from the source electrode and the drain electrode.
In the manufacturing method of the thin-film transistor described in Claim 6 or 7,
In the low-concentration region forming step, the low-concentration region is formed in a first silicon layer forming layer that becomes the first silicon layer exposed from the source electrode and the drain electrode,
In the semiconductor layer formation etching step, by removing a part of the first silicon layer formation layer disposed outside the low concentration region, the channel portion is disposed corresponding to the source electrode and the drain electrode. A method for manufacturing a thin film transistor, wherein a high concentration region having a higher hydrogen content than a low concentration region is formed.
In the manufacturing method of the thin-film transistor described in Claim 7,
The method of manufacturing a thin film transistor, wherein the laser beam has a wavelength of 248 nm to 355 nm.
In the manufacturing method of the thin-film transistor as described in any one of Claims 6 thru | or 10,
The method of manufacturing a thin film transistor, wherein the substrate is a rectangular glass substrate having a short side of 1500 mm or more.