TWI609496B - Thin film transistor and manufacturing method thereof - Google Patents

Description

Thin film transistor and manufacturing method thereof

The invention relates to a thin film transistor and a manufacturing method thereof, in particular to a thin film transistor having two patterned semiconductor layers with different resistance values and a manufacturing method thereof.

In recent years, the application of various flat panel displays has developed rapidly, and various household items such as televisions, mobile phones, steam locomotives, and even refrigerators can be seen to be combined with flat-panel displays. In the flat panel display technology, a thin film transistor (TFT) is a widely used semiconductor component, such as a liquid crystal display (LCD), an organic light emitting diode (OLED). ) Display and flat panel displays such as electronic paper (E-paper). Thin film electro-crystal systems are utilized to provide switching of voltage or current such that display pixels in various displays can exhibit bright, dark, and grayscale display effects.

At present, thin film transistors used in the display industry can be distinguished according to the semiconductor layer materials used, including amorphous silicon TFTs (a-Si TFTs), polysilicon TFTs, and oxide semiconductors. Metal oxide semiconductor TFT. Compared with polycrystalline germanium thin film transistors, oxide semiconductor thin film transistors have the advantages of high electron mobility and simplified process, so they are considered to have the opportunity to replace the current mainstream amorphous germanium thin film transistors. However, in the bottom gate type thin film transistor, since the back channel in the semiconductor layer is closer to the drain, when a voltage is applied to the drain, an additional carrier is generated in the area of the back channel, and The threshold voltage of the thin film transistor is changed, thereby reducing the controllability of the front channel in the semiconductor layer near the gate, making the difficulty of controlling the thin film transistor rise.

One of the main objects of the present invention is to provide a thin film transistor and a method of fabricating the same, by providing two layers of patterned semiconductor layers having different resistance values to avoid the problem of threshold voltage change.

To achieve the above objective, an embodiment of the present invention provides a thin film transistor including a substrate, a gate, a drain, a source, a gate insulating layer, a first patterned semiconductor layer, and a first Two patterned semiconductor layers. The gate is disposed on the substrate, and the gate insulating layer is disposed on the gate. The first patterned semiconductor layer and the second patterned semiconductor layer are disposed on the gate insulating layer, wherein the gate is disposed between the substrate and the first patterned semiconductor layer, and the first patterned semiconductor layer is disposed on the second patterned semiconductor The layer is between the gate insulating layer and the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer. The drain and the source are disposed on the first patterned semiconductor layer and electrically connected to the first patterned semiconductor layer.

In order to achieve the above object, an embodiment of the present invention provides a method of fabricating a thin film transistor, which comprises the following steps. Forming a gate on a substrate, forming a gate insulating layer on the gate, and then sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer, wherein the first semiconductor layer is disposed on the first semiconductor layer Between the second semiconductor layer and the gate insulating layer. Then, a patterned insulating layer is formed on the second semiconductor layer, and then the patterned insulating layer is used as an etch mask, and a second etching process is performed on the second semiconductor layer to form a second patterned semiconductor layer. Then, the first semiconductor layer is patterned to form a first patterned semiconductor layer, wherein the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer, and a drain is formed on the patterned insulating layer. a source, wherein the drain and the source are electrically connected to the first patterned semiconductor layer.

In order to achieve the above object, another embodiment of the present invention provides a method of fabricating a thin film transistor, which comprises the following steps. Forming a gate on a substrate, forming a gate insulating layer on the gate, and sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer, wherein the first semiconductor layer is disposed on the gate Between the second semiconductor layer and the gate insulating layer. Then, the first semiconductor layer and the second semiconductor layer are patterned to form a first patterned semiconductor layer and a second pre-patterned semiconductor layer, and then a patterned interlayer dielectric layer is formed on the second pre-patterned semiconductor layer. The patterned interlayer dielectric layer has a first contact hole and a second contact hole. Then, the patterned interlayer dielectric layer is used as an etch mask, and the second pre-patterned semiconductor layer is subjected to an etching process to form a second patterned semiconductor layer, and the second patterned semiconductor layer has a third contact hole. And a fourth contact hole, wherein the first contact hole is in communication with the third contact hole, the second contact hole is in communication with the fourth contact hole, and an area of the first patterned semiconductor layer is larger than an area of the second patterned semiconductor layer . Then, a drain and a source are formed on the patterned interlayer dielectric layer, and the drain and the source are filled in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to be electrically connected The first patterned semiconductor layer.

The present invention will be further understood by those skilled in the art, and the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The effect that you want to achieve.

Please refer to FIG. 1, which is a partial cross-sectional view showing a first embodiment of a thin film transistor of the present invention. The thin film electro-crystal system of this embodiment is exemplified by a thin film transistor which can be applied to a display panel, but is not limited thereto. As shown in FIG. 1, the thin film transistor 1 of the present embodiment includes a substrate 100, a gate 102, a drain 104, a source 106, a gate insulating layer 108, a first patterned semiconductor layer 110, and a second patterned semiconductor. Layer 112 and patterned insulating layer 114. The gate 102 is disposed on the substrate 100, and the gate insulating layer 108 is disposed on the gate 102 and completely covers the gate 102. The substrate 100 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate, or a substrate formed of other suitable materials. The substrate 100 of the present embodiment is exemplified by a glass substrate. The gate 102 is disposed between the substrate 100 and the first patterned semiconductor layer 110, and thus the thin film transistor 1 is a bottom gate type thin film transistor. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 are disposed on the gate insulating layer 108 , wherein the first patterned semiconductor layer 110 is disposed between the second patterned semiconductor layer 112 and the gate insulating layer 108 . The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 overlap with a portion of the gate 102 in a vertical projection direction Z, wherein the vertical projection direction Z refers to a direction perpendicular to the surface of the substrate 100. The area of the first patterned semiconductor layer 110 is larger than the area of the second patterned semiconductor layer 112, and thus the second patterned semiconductor layer 112 exposes both ends of the first patterned semiconductor layer 110. In this embodiment, the first patterned semiconductor layer 110 is indium tin zinc oxide (ITZO), and the second patterned semiconductor layer 112 is indium gallium zinc oxide (IGZO), wherein the etching rate of the aluminum oxide to indium gallium zinc oxide Faster, and the indium tin zinc oxide is resistant to the aluminum etchant, so the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have a high selective etching ratio for the aluminum etchant when using an aluminum etchant pair When the second patterned semiconductor layer 112 is etched, the first patterned semiconductor layer 110 is not affected by the aluminum etching solution, or is limited by the aluminum etching liquid, so that it can be fabricated by using an aluminum etching night for the etching process. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different patterns are formed. Further, the resistance value of the indium tin zinc oxide of the first patterned semiconductor layer 110 is lower than the resistance value of the indium gallium zinc oxide of the second patterned semiconductor layer 112. In other words, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 of the present embodiment have a lower resistance value than the second patterned semiconductor layer 112 except that the second patterned semiconductor layer 112 has a high selective etching ratio. resistance.

In addition, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 of the present embodiment are not limited to indium tin zinc oxide and indium gallium zinc oxide. For example, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 may respectively include indium tin zinc oxide, indium gallium zinc oxide or other kinds of metal oxide semiconductors, and the first patterned semiconductor layer 110 and the first The material selection of the second patterned semiconductor layer 112 may be such that the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have a high selective etching ratio, and the first patterned semiconductor layer 110 has a lower resistance value. The condition of the resistance value of the second semiconductor layer 112 may be patterned. In other variations, when the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 comprise the same kind of metal oxide semiconductor material, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 may be Each has a different crystal structure such as a crystalline metal oxide semiconductor layer and an amorphous metal oxide semiconductor layer. For example, the first patterned semiconductor layer 110 may be crystalline indium tin zinc and the second patterned semiconductor layer 112 is amorphous indium tin zinc, but not limited thereto.

In this embodiment, the patterned insulating layer 114 is disposed on the second patterned semiconductor layer 112, wherein the patterned insulating layer 114 and the second patterned semiconductor layer 112 have substantially the same area and pattern, and the patterned insulating layer The area of the 114 and second patterned semiconductor layer 112 is smaller than the area of the first patterned semiconductor layer 110. In other words, the patterned insulating layer 114 and the second patterned semiconductor layer 112 cover only a portion of the first patterned semiconductor layer 110 and expose both ends of the first patterned semiconductor layer 100. In addition, the drain 104 and the source 106 are disposed on the first patterned semiconductor layer 110 and electrically connected to the first patterned semiconductor layer 110, and the drain 104 and the source 106 are electrically isolated from each other. In detail, the drain 104 and the source 106 respectively cover and directly contact the top surface and the sidewall of the two ends of the first patterned semiconductor layer 110, and the drain 104 and the source 106 are further extended and disposed on the patterned insulating layer 114. Since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114, the drain 104 and the source 106 are not in contact with the top surface of the second patterned semiconductor layer 112. By designing that the area of the patterned insulating layer 114 and the second patterned semiconductor layer 112 is smaller than the area of the first patterned semiconductor layer 110, the drain 104 and the source 106 can directly be patterned with a first resistance having a lower resistance value. The semiconductor layer 110 is in direct contact, so the drain 104 and the source 106 of the present embodiment may have a lower contact resistance. Since the first patterned semiconductor layer 110 is closer to the gate 102, the first patterned semiconductor layer 110 can be regarded as a front channel of the thin film transistor 1, and the second patterned semiconductor layer 112 can be regarded as a back channel. In addition, since the second patterned semiconductor layer 112 has a higher resistance value, the number of additional carriers generated by the back channel affected by the drain 104 can be reduced to reduce the magnitude of the change in the threshold voltage of the thin film transistor 1. On the other hand, since the first patterned semiconductor layer 110 is closer to the gate 102 and the resistance value is lower than that of the second patterned semiconductor layer 112, the carriers are mostly circulated in the first patterned semiconductor layer 110, thereby increasing the film power. Controllability of the front channel of crystal 1.

Please refer to FIG. 2 to FIG. 4 , which are schematic diagrams showing the process of the first embodiment of the method for fabricating the thin film transistor of the present invention. As shown in FIG. 2, according to the first embodiment of the present invention, a substrate 100 is first provided, a gate 102 is formed on the substrate 100, and a gate insulating layer 108 is formed on the gate 102. The gate 102 is formed by, for example, forming a metal layer (not shown) on the substrate 100, and then patterning the metal layer, for example, performing a lithography and etching process to form the gate 102 on the substrate 100. . The material of the above metal layer may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, a composite layer of the above materials or the above materials. Alloy, but not limited to this. The material of the gate insulating layer 108 may include an inorganic insulating material such as hafnium oxide, tantalum nitride, hafnium oxynitride, graphene oxide, graphene nitride, graphene oxynitride, etc., or an organic insulating material or an organic/inorganic hybrid insulating material. The material may be a single layer structure or a composite layer structure, but is not limited thereto. Next, the entire first semiconductor layer 116 and the second semiconductor layer 118 are sequentially formed on the gate insulating layer 108, wherein the first semiconductor layer 116 is disposed between the second semiconductor layer 118 and the gate insulating layer 108. In the present embodiment, the first semiconductor layer 116 is indium tin zinc oxide (ITZO), and the second semiconductor layer 118 is indium gallium zinc oxide (IGZO), but not limited thereto. The materials of the first semiconductor layer 116 and the second semiconductor layer 118 may respectively include indium tin zinc oxide, indium gallium zinc oxide or other kinds of metal oxide semiconductors, and the materials of the first semiconductor layer 116 and the second semiconductor layer 118 are selected as long as The first semiconductor layer 116 and the second semiconductor layer 118 may have a high selective etching ratio, and the resistance value of the first semiconductor layer 116 may be lower than the resistance value of the second semiconductor layer 118. In other variant embodiments, the first semiconductor layer 116 and the second semiconductor layer 118 may comprise the same kind of metal oxide semiconductor material, but each has a different crystal structure, for example, the first semiconductor layer 116 is crystalline indium tin zinc oxide. The second semiconductor layer 118 is amorphous indium tin zinc, but is not limited thereto.

Then, a patterned insulating layer 114 is formed on the second semiconductor layer 118. The method of forming the patterned insulating layer 114 includes, for example, forming an insulating layer (not shown) on the entire surface of the second semiconductor layer 118, and then defining the position of the patterned insulating layer 114 by using the photoresist 120, and then performing an etching process. (eg, a dry etch process) to create a patterned insulating layer 114. The photoresist 120 may be removed using a photoresist stripper after the patterned insulating layer 114 is formed, but is not limited thereto. The material of the patterned insulating layer 114 may include, but is not limited to, an inorganic insulating material such as cerium oxide, cerium nitride, cerium oxynitride, graphene oxide, graphene nitride, graphene oxynitride or the like. The material of the patterned insulating layer 114 may also include an organic insulating material or an organic/inorganic hybrid insulating material, and may be a single layer structure or a composite layer structure. In addition, the thickness of the patterned insulating layer 114 is exemplified by about 500 angstroms, but is not limited thereto.

As shown in FIG. 3, the patterned insulating layer 114 is then used as an etch mask, and the second etch process 128 is performed on the second semiconductor layer 118 to form the second patterned semiconductor layer 112. In the present embodiment, the first etching process is performed using the first etching liquid, and the first etching liquid is an aluminum etching liquid. Therefore, the first etching process 128 is a wet etching process, but is not limited thereto. Since the aluminum etching solution has a faster etching rate for indium gallium zinc oxide, and the indium tin zinc oxide is resistant to the aluminum etching liquid, in the first etching process 128, the second semiconductor layer 118 can be etched to form the second patterned semiconductor. Layer 112, while first semiconductor layer 116 is substantially unaffected by the first etchant. In addition, since the patterned insulating layer 114 is directly used as an etch mask in the first etching process 128, the formed second patterned semiconductor layer 112 has substantially the same pattern and area as the patterned insulating layer 114. In other words, the present embodiment defines the pattern of the second patterned semiconductor layer 112 by patterning the insulating layer 114.

As shown in FIG. 4, the first semiconductor layer 116 is then patterned to form the first patterned semiconductor layer 110. The patterning process can be, for example, a lithography and etching process. First, a photoresist layer can be coated on the entire surface, and then the photoresist layer can be exposed to the photoresist layer to define the position of the first patterned semiconductor layer 110. Developing to form a patterned photoresist 122 having a pattern of the first patterned semiconductor layer 110 to be fabricated, and then performing a second etching process 130 with a second etching solution to form the first patterned semiconductor layer 110, The second etching solution of the embodiment is oxalic acid, but is not limited thereto. In the present embodiment, the photoresist 122 is formed at the position of the second patterned semiconductor layer 112, and the photoresist 112 has a larger area than the second patterned semiconductor layer 112, and may cover the second patterned semiconductor layer 112. And patterned insulating layer 114, but not limited thereto. Thereby, the area of the first patterned semiconductor layer 110 formed by the second etching process 130 is greater than the area of the second patterned semiconductor layer 112. In addition, the photoresist 122 may be removed using a photoresist stripper after the first patterned semiconductor layer 110 is formed, but is not limited thereto.

Referring again to FIG. 1, the photoresist 122 is removed to expose both ends of the first patterned semiconductor layer 110 that is not covered by the patterned insulating layer 114 and the second patterned semiconductor layer 112. Then, a drain 104 and a source 106 are formed on the patterned insulating layer 114, wherein the drain 104 and the source 106 are also formed on the first patterned semiconductor layer 110 and respectively covered and directly in contact with the first patterned semiconductor layer The top surface and the sidewalls of the two ends of the 110 electrically connect the first patterned semiconductor layer 110 to the drain 104 and the source 106. In addition, since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114, the drain 104 and the source 106 are not in contact with the top surface of the second patterned semiconductor layer 112. The method of forming the drain 104 and the source 106 may be the same as the method of forming the gate 102, but is not limited thereto. The material of the drain 104 and the source 106 may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, and the combination of the above materials. A layer or an alloy of the above materials, but is not limited thereto. According to the embodiment, since the second patterned semiconductor layer 112 is directly formed by using the patterned insulating layer 114 as an etch mask in the first etching process 128, the fabrication of the bottom gate type thin film transistor is compared with the conventional fabrication. In this embodiment, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different patterns and areas are formed without an additional mask.

The thin film transistor of the present invention and the method of fabricating the same are not limited to the above embodiments. The other embodiments of the present invention will be further described below, and the same reference numerals will be used to refer to the same elements, and the repeated parts will not be described again.

Please refer to FIG. 5, which is a partial cross-sectional view showing a second embodiment of the thin film transistor of the present invention. As shown in FIG. 5, the thin film transistor 2 of the present embodiment is different from the first embodiment in that the thin film transistor 2 includes a patterned interlayer dielectric layer 124 disposed on the second patterned semiconductor layer 112, and The pole 104 and the source 106 are disposed on the patterned interlayer dielectric layer 124. The thickness of the patterned interlayer dielectric layer 124 of this embodiment is about 3000 angstroms, but is not limited thereto. The material of the patterned interlayer dielectric layer 124 may be an organic dielectric material or an inorganic dielectric material, and the patterned interlayer dielectric layer 124 may be a single layer structure or a composite layer structure, and the related material may be selected from the patterned insulating layer as described above. The material of 114 will not be described here. In addition, the patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2, and the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 and the first contact hole The three contact holes V3 are in communication with each other, and the second contact holes V2 are in communication with the fourth contact holes V4, and the third contact holes V3 and the fourth contact holes V4 do not cover the two portions of the top surface of the first patterned semiconductor layer 110, respectively. In addition, the source 106 is provided on the patterned interlayer dielectric layer 124, and simultaneously fills the first contact hole V1 and the third contact hole V3, and is in direct contact with a portion of the top surface of the first patterned semiconductor layer 110. The drain 104 is provided on the patterned interlayer dielectric layer 124, and simultaneously fills the second contact hole V2 and the fourth contact hole V4, and directly on the top surface of the other portion of the first patterned semiconductor layer 110. contact. Since the second patterned semiconductor layer 112 of the embodiment has a contact hole, the area of the second patterned semiconductor layer 112 is smaller than that of the first patterned semiconductor layer 110, and the drain 104 and the source are provided by the design of the embodiment. The 106 can be in direct contact with the first patterned semiconductor layer 110 having a lower resistance value, so the drain 104 and the source 106 of the present embodiment can have a lower contact resistance. On the other hand, since the thin film transistor 2 has the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different resistance values, the number of additional carriers generated by the back channel affected by the drain 104 can be reduced, The variation of the threshold voltage of the thin film transistor 2 is reduced, thereby increasing the controllability of the front channel of the thin film transistor 2. The remaining features of the thin film transistor 2 of this embodiment are substantially the same as those of the first embodiment. Reference may be made to the description of the related components and materials in FIG. 1 , and details are not described herein again.

Please refer to FIG. 6 to FIG. 8 , which are schematic diagrams showing the process of the second embodiment of the method for fabricating the thin film transistor of the present invention. As shown in FIG. 6, the second embodiment of the present invention is different from the first embodiment in that a first semiconductor layer and a second semiconductor layer are formed (for example, the first semiconductor layer 116 and the second layer shown in FIG. 2) After the semiconductor layer 118), the first semiconductor layer and the second semiconductor layer are first patterned to form the first patterned semiconductor layer 110 and the second pre-patterned semiconductor layer 126. The first patterned semiconductor layer 110 and the second pre-patterned semiconductor layer 126 may be formed, for example, by a photolithography and etching process. For example, the first semiconductor layer of the embodiment is indium tin zinc oxide, the second semiconductor layer is indium gallium zinc oxide, and the etching solution used includes oxalic acid, which can simultaneously treat the first semiconductor layer and the second semiconductor layer. Etching is performed, but not limited thereto. As shown in FIG. 7, a patterned interlayer dielectric layer 124 is formed on the second pre-patterned semiconductor layer 126, wherein the patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2. The method of forming the patterned interlayer dielectric layer 124 is, for example, forming a dielectric layer (not shown) on the entire surface, and then performing a patterning process on the dielectric layer (for example, performing a lithography and etching process) in the dielectric layer. The first contact hole V1 and the second contact hole V2 are formed, but not limited thereto.

As shown in FIG. 8, the patterned interlayer dielectric layer 124 is then used as an etch mask, and the second pre-patterned semiconductor layer 126 is etched to form a second patterned semiconductor layer 112, wherein the etch process 132 is performed. The second pre-patterned semiconductor layer 126 is patterned using an aluminum etchant. After the etching process 132, the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 is in communication with the third contact hole V3, and the second contact hole V2 and the fourth contact hole The contact holes V4 are in communication, and thus the third contact holes V3 and the fourth contact holes V4 respectively expose two portions of the top surface of the first patterned semiconductor layer 110. Since the second patterned semiconductor layer 112 of the present embodiment has the third contact hole V3 and the fourth contact hole V4, the area of the first patterned semiconductor layer 110 is larger than the area of the second patterned semiconductor layer 112. Referring to FIG. 5, a drain 104 and a source 106 are formed on the patterned interlayer dielectric layer 124. The drain 104 fills the second contact hole V2 and the fourth contact hole V4 and is electrically connected to the first pattern. The semiconductor layer 110 is filled, and the source 106 is filled in the first contact hole V1 and the third contact hole V3 and electrically connected to the first patterned semiconductor layer 110. In addition, since the top surface of the first patterned semiconductor layer 110 has two portions exposed by the third contact hole V3 and the fourth contact hole V4, the drain 104 can be via the second contact hole V2 and the fourth contact hole V4. Direct contact with a portion of the top surface of the first patterned semiconductor layer 110, and the source 106 may be in direct contact with the top surface of the other portion of the first patterned semiconductor layer 110 via the first contact hole V1 and the third contact hole V3 . According to the embodiment, since the patterned interlayer dielectric layer 124 is directly used as the etch mask in the etching process 132, an additional mask is not required as compared with the conventional method for fabricating the bottom gate type thin film transistor. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 having different areas and patterns can be formed. The other processes and conditions of the method for fabricating the thin film transistor 2 of the present embodiment and the materials of the respective elements may be substantially the same as those of the first embodiment, and are not described herein again.

In summary, the second patterned semiconductor layer of the thin film transistor disclosed in the present invention has a high resistance value, thereby reducing the number of additional carriers generated by the back channel affected by the drain to reduce the thickness of the thin film transistor. The magnitude of the change in the threshold voltage. On the other hand, since the first patterned semiconductor layer is closer to the gate and the resistance value is lower than that of the second patterned semiconductor layer, the carriers are mostly circulated in the first patterned semiconductor layer, thereby increasing the front channel of the thin film transistor. Control ability. In addition, in the method for fabricating the thin film transistor disclosed in the present invention, in the process of forming the second patterned semiconductor layer, the patterned insulating layer or the patterned interlayer dielectric layer is directly used as an etch mask, thereby forming a layer having different areas. A patterned semiconductor layer and a second patterned semiconductor layer do not require an additional mask as compared to conventional methods of fabricating a bottom gate thin film transistor. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1, 2‧‧‧ film transistor

100‧‧‧Substrate

102‧‧‧ gate

104‧‧‧汲polar

106‧‧‧ source

108‧‧‧ gate insulation

110‧‧‧First patterned semiconductor layer

112‧‧‧Second patterned semiconductor layer

114‧‧‧patterned insulation

116‧‧‧First semiconductor layer

118‧‧‧Second semiconductor layer

120, 122‧‧‧Light resistance

124‧‧‧ patterned interlayer dielectric layer

126‧‧‧Second pre-patterned semiconductor layer

128‧‧‧First etching process

130‧‧‧Second etching process

132‧‧‧ etching process

V1‧‧‧ first contact hole

V2‧‧‧Second contact hole

V3‧‧‧ third contact hole

V4‧‧‧ fourth contact hole

Z‧‧‧Vertical projection direction

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a partial cross-sectional view showing a first embodiment of a thin film transistor of the present invention. 2 to 4 are schematic views showing the process of the first embodiment of the method for fabricating a thin film transistor of the present invention. Figure 5 is a partial cross-sectional view showing a second embodiment of the thin film transistor of the present invention. 6 to 8 are schematic views showing the process of the second embodiment of the method for fabricating a thin film transistor of the present invention.

1‧‧‧film transistor

100‧‧‧Substrate

102‧‧‧ gate

104‧‧‧汲polar

106‧‧‧ source

108‧‧‧ gate insulation

110‧‧‧First patterned semiconductor layer

112‧‧‧Second patterned semiconductor layer

114‧‧‧patterned insulation

Z‧‧‧Vertical projection direction

Claims (22)

A thin film transistor includes: a substrate; a gate disposed on the substrate; a gate insulating layer disposed on the gate; a first patterned semiconductor layer and a second patterned semiconductor layer disposed thereon On the gate insulating layer, the gate is disposed between the substrate and the first patterned semiconductor layer, and the first patterned semiconductor layer is disposed between the second patterned semiconductor layer and the gate insulating layer. The area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer, and the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer a second metallized semiconductor layer is a crystalline metal oxide semiconductor layer; and a drain and a source are disposed on the first patterned semiconductor layer and patterned with the first The semiconductor layer is electrically connected. The thin film transistor of claim 1, further comprising a patterned insulating layer disposed on the second patterned semiconductor layer, wherein the patterned insulating layer and the second patterned semiconductor layer have substantially the same area. The thin film transistor of claim 2, wherein the patterned insulating layer and the second patterned semiconductor layer expose both ends of the first patterned semiconductor layer. The thin film transistor of claim 3, wherein the drain and the source are further disposed on the patterned insulating layer, and the drain and the source are in direct contact with the two ends of the first patterned semiconductor layer, respectively. a top surface, and the drain and the source are not in contact with a top surface of the second patterned semiconductor layer. The thin film transistor of claim 1, further comprising a patterned interlayer dielectric layer disposed on the second patterned semiconductor layer, wherein the patterned interlayer dielectric layer has a first contact hole and a second contact a second patterned semiconductor layer having a third contact hole and a fourth contact hole, wherein the first contact hole is in communication with the third contact hole, and the second contact hole is in communication with the fourth contact hole. And the third contact hole and the fourth contact hole do not cover the first patterned semiconductor layer. The thin film transistor of claim 5, wherein the drain and the source are disposed on the patterned interlayer dielectric layer and fill the first contact hole, the second contact hole, and the third contact hole And contacting the first patterned semiconductor layer with the fourth contact hole. The thin film transistor of claim 1, wherein a resistance value of the first patterned semiconductor layer is lower than a resistance value of the second patterned semiconductor layer. A method for fabricating a thin film transistor includes the steps of: forming a gate on a substrate; forming a gate insulating layer on the gate; forming a first semiconductor layer and a first layer on the gate insulating layer a semiconductor layer, wherein the first semiconductor layer is disposed between the second semiconductor layer and the gate insulating layer; a patterned insulating layer is formed on the second semiconductor layer; and the patterned insulating layer is used as an etch mask a cover, and performing a first etching process on the second semiconductor layer to form a second patterned semiconductor layer; forming a photoresist at a position of the second patterned semiconductor layer, and coating the second patterned semiconductor a layer and the patterned insulating layer; patterning the first semiconductor layer to form a first patterned semiconductor layer, wherein an area of the first patterned semiconductor layer is larger than an area of the second patterned semiconductor layer; and the pattern A drain and a source are formed on the insulating layer, wherein the drain is electrically connected to the source and the first patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 8, wherein the patterned insulating layer and the second patterned semiconductor layer have substantially the same area. The method of fabricating a thin film transistor according to claim 9, wherein the patterned insulating layer and the second patterned semiconductor layer expose both ends of the first patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 10, wherein the drain and the source are in direct contact with a top surface of each of the first patterned semiconductor layers, and the drain is not in contact with the source. The top surface of the second patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 8, wherein the first etching process comprises using a first etching solution, and the first etching liquid comprises an aluminum etching solution. The method of fabricating a thin film transistor according to claim 8, wherein the step of patterning the first semiconductor layer comprises a second etching process using a second etching solution, and the second etching liquid comprises oxalic acid . The method of fabricating a thin film transistor according to claim 8, wherein the first patterned semiconductor The material of the layer and the second patterned semiconductor layer respectively includes indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or other kinds of metal oxide semiconductors. The method of fabricating a thin film transistor according to claim 14, wherein a resistance value of the first patterned semiconductor layer is lower than a resistance value of the second patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 14, wherein the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer is a crystalline metal oxide semiconductor layer. The second patterned semiconductor layer is an amorphous metal oxide semiconductor layer. A method for fabricating a thin film transistor includes the steps of: forming a gate on a substrate; forming a gate insulating layer on the gate; forming a first semiconductor layer and a first layer on the gate insulating layer a semiconductor layer, wherein the first semiconductor layer is disposed between the second semiconductor layer and the gate insulating layer; the first semiconductor layer and the second semiconductor layer are patterned to form a first patterned semiconductor layer and a a second pre-patterned semiconductor layer; a patterned interlayer dielectric layer is formed on the second pre-patterned semiconductor layer, wherein the patterned interlayer dielectric layer has a first contact hole and a second contact hole; The patterned interlayer dielectric layer serves as an etch mask, and an etching process is performed on the second pre-patterned semiconductor layer to form a second patterned semiconductor layer, the second patterned semiconductor layer having a third contact hole and a fourth contact hole, wherein the first contact hole is in communication with the third contact hole, the second contact hole is in communication with the fourth contact hole, and the first patterned semiconductor The area of the layer is larger than the area of the second patterned semiconductor layer, wherein the etching process comprises patterning the second pre-patterned semiconductor layer using an aluminum etchant; and forming a drain on the patterned interlayer dielectric layer a source, the drain and the source are filled in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to electrically connect the first patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 17, wherein the third contact hole and the fourth contact hole do not cover the first patterned semiconductor layer, and the drain and the source respectively pass the first contact The hole, the second contact hole, the third contact hole and the fourth contact hole are in direct contact with the first patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 17, wherein the step of patterning the first semiconductor layer and the second semiconductor layer comprises using oxalic acid as an etchant. The method for fabricating a thin film transistor according to claim 17, wherein the materials of the first patterned semiconductor layer and the second patterned semiconductor layer respectively comprise indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or Other types of metal oxide semiconductors. The method of fabricating a thin film transistor according to claim 20, wherein a resistance value of the first patterned semiconductor layer is lower than a resistance value of the second patterned semiconductor layer. The method of fabricating a thin film transistor according to claim 20, wherein the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer is a crystalline metal oxide semiconductor layer And the second patterned semiconductor layer is an amorphous metal oxide semiconductor Body layer.