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WO2009147778A1 - Procédé de fabrication d’une plaquette liée - Google Patents

Procédé de fabrication d’une plaquette liée Download PDF

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Publication number
WO2009147778A1
WO2009147778A1 PCT/JP2009/001795 JP2009001795W WO2009147778A1 WO 2009147778 A1 WO2009147778 A1 WO 2009147778A1 JP 2009001795 W JP2009001795 W JP 2009001795W WO 2009147778 A1 WO2009147778 A1 WO 2009147778A1
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WO
WIPO (PCT)
Prior art keywords
wafer
bonding
heat treatment
peeling
bonded
Prior art date
Application number
PCT/JP2009/001795
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English (en)
Japanese (ja)
Inventor
横川功
山口進一
北村琢也
Original Assignee
信越半導体株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 信越半導体株式会社 filed Critical 信越半導体株式会社
Publication of WO2009147778A1 publication Critical patent/WO2009147778A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to the manufacture of bonded wafers using an ion implantation separation method.
  • a bonded wafer is used in which a semiconductor wafer is bonded to another wafer and then a wafer on which an element is manufactured is thinned.
  • a method for manufacturing such a bonded wafer for example, two mirror-polished silicon wafers are prepared, and an oxide film is formed on at least one of the wafers. After these wafers are bonded, heat treatment is performed at a temperature of 200 to 1200 ° C. to increase the bond strength. After that, the bonded wafer on which the semiconductor layer (thin film) is formed can be manufactured by grinding and polishing the element production side wafer (bond wafer) to a desired thickness.
  • a bond heat treatment is immediately performed at a high temperature of 1000 ° C. or higher after the bond wafer and the base wafer are bonded together at room temperature.
  • voids generated in the periphery of the wafer can be reduced by setting the time from the bonding process at room temperature to the bonding heat treatment process within one hour. Is described.
  • a method for thinning a bond wafer there is a method for manufacturing a bonded wafer using an ion implantation separation method (also called a smart cut (registered trademark) method) in addition to the above-described grinding and polishing method.
  • a high concentration ion implantation layer is formed in a wafer by implanting hydrogen ions or the like into a semiconductor wafer by ion implantation.
  • a wafer having a high concentration ion-implanted layer (bond wafer) and a wafer (base wafer) to be a support substrate are bonded together at room temperature, heat-treated at a low temperature of about 500 ° C., and the wafer is peeled off by the ion-implanted layer.
  • a bonded wafer having a thin semiconductor layer on the surface of the wafer to be the support substrate can be manufactured. Since the bonded wafer thus produced does not have sufficient bonding strength at the bonded interface as it is, bonding heat treatment is performed at a high temperature of 1000 ° C. or higher.
  • the semiconductor layer (thin film) is not transferred to the peripheral portion.
  • the width hereinafter, the width of the peripheral portion where the thin film is not transferred is referred to as the terrace width
  • the terrace width is widened and the number of chips of the finally obtained semiconductor device is reduced.
  • a wafer having a small polishing sag at the peripheral portion may be used.
  • the present invention has been made in view of the above-described problems, and it is possible to reduce a terrace width where a thin film is not transferred at the time of peeling in an ion implantation peeling method, and to perform a sticking that can cause good peeling. It aims at providing the manufacturing method of a bonded wafer.
  • the present invention provides an ion-implanted layer formed inside a wafer by ion-implanting at least one kind of gas ions of hydrogen ions and rare gas ions from the surface of the bond wafer. Bonding is performed by bonding the surface of the ion-implanted surface and the surface of the base wafer directly or through an insulating film, and then performing a peeling heat treatment to peel off the bond wafer at the ion-implanted layer to produce a bonded wafer.
  • a bonded wafer manufacturing method is provided in which the bond wafer is peeled off by the ion implantation layer by performing the peeling heat treatment after 6 hours or more after the bonding. .
  • the direction of water molecules contributing to bonding between wafers at the bonding interface is aligned and the electric bonding is efficiently performed during 6 hours or more after bonding. Therefore, the bond strength at the bonding interface between the wafers is increased.
  • the bond strength further increases, and peeling occurs in a state in which the bond strength is significantly higher than in the case where the peel heat treatment is performed immediately after bonding.
  • good peeling occurs and it becomes a high-quality peeling surface, and in particular, since the bonding strength is high even in the periphery of the wafer where the bonding strength is low and the thin film is difficult to be transferred, the thin film is transferred with good peeling.
  • the terrace width is effectively reduced. For this reason, the width of the high-quality semiconductor layer is widened and the number of chips of the finally obtained semiconductor device can be increased, so that the product yield is improved.
  • the peeling heat treatment after 12 hours or more have elapsed after the pasting.
  • the time until the peeling heat treatment is performed for 12 hours or more after bonding the orientation of more water molecules is aligned in bonding at the bonding interface, and the bonding strength is further increased.
  • the terrace width at the time is further reduced.
  • the wafer is held at room temperature until the peeling heat treatment is performed after the bonding.
  • the wafer is held at room temperature until a peeling heat treatment is performed, so that it is not necessary to perform a special process just by leaving the wafer while holding, compared to the conventional case. There is no extra cost.
  • a silicon single crystal wafer can be used as the bond wafer and the base wafer.
  • the manufacturing method of the present invention is suitable, and the terrace width after peeling can be reduced.
  • an insulating film is formed in advance on the surfaces of the bond wafer and the base wafer, and bonded together via the insulating films during the bonding. If it is the manufacturing method of the bonded wafer of this invention, since it can perform favorable peeling in a state with high bond strength, especially when bonding through insulating films with low bond strength, a good quality thin film and And the terrace width is also reduced.
  • water molecules contributing to bonding at the bonding interface are aligned by performing a heat treatment after 6 hours or more after bonding. After the bond strength is increased, the peeling heat treatment is performed.
  • This debonding heat treatment further increases the bond strength at the bonding interface, resulting in good delamination even at the wafer periphery where the bond strength was low and the thin film was difficult to transfer in the past, effectively reducing the terrace width where the thin film was not transferred. can do.
  • no special treatment is required, and a high-quality thin film can be easily obtained. For this reason, the width of a high-quality semiconductor layer is widened by a simple method, and the number of chips of a finally obtained semiconductor device can be increased, so that the product yield is improved.
  • the inventors have focused on peeling the wafer in a state in which the bonding strength at the bonding interface is as high as possible.
  • the bonding strength is not sufficiently high due to the influence of slight polishing sag, but the region is peeled off without transferring the thin film in the peeling step. Therefore, it was considered that if the bonding strength of the close contact region can be increased, the region that is peeled off in the peeling step can be reduced.
  • the bonding heat treatment performed after the bonding is set to 1000 ° C. or more, thereby bonding the bonding interface to a strong siloxane bond.
  • the heat treatment temperature when peeling the bonded wafer is as low as about 500 ° C.
  • the bonding state at the bonding interface when peeling occurs is a weak bond centered on hydrogen bonds by silanol groups and water molecules, so the bonding force at the bonding interface is defeated by the peeling force and the terrace width. Is likely to spread and cause voids and blisters. Therefore, in the ion implantation separation method, it is necessary to increase the bond strength at the bonding interface when separation occurs.
  • the bonding strength at the bonding interface depends on the bonding heat treatment temperature, and the bonding state is Phase I: ⁇ 200 ° C. SiOH: (H 2 O) 2 : (H 2 O) 2 : HOSi Phase II:> 200 ° C. SiOH: HOSi + (H 2 O) 4 Phase III:> 700 ° C Si-O-Si + H 2 O Phase IV:> 1000 ° C. SiOx It is shown that, at a temperature of 1000 ° C. or lower, bonding by water molecules affects the bonding at the bonding interface, and the lower the bonding heat treatment temperature, the larger the influence of bonding by water molecules. In the ion implantation delamination method, since the wafer is delaminated within the temperature range from the above II phase to the III phase (200 to 700 ° C.), it is necessary to effectively draw out bonds by water molecules.
  • Water molecules are electrically positive and negative, with hydrogen on the positive side and oxygen on the negative side. By attracting the positive and negative electricity, water molecules are electrically coupled to each other, contributing to the bonding of wafers at the bonding interface. In order to increase the bonding force at the bonding interface at low temperatures, the direction of water molecules, that is, the positive and negative polarities, must be neatly aligned and electrically efficiently bonded.
  • the present inventors conducted extensive investigations using the bond strength measurement by the blade method, and in order to align the water molecules to the extent that the bond strength at the bonding interface is improved, after the bonding, a peeling heat treatment is performed. It has been found that it is necessary to allow a predetermined time to elapse.
  • the blade method is a method of inserting a specified length and a blade into the bonding interface of a bonded wafer and evaluating the bonding strength of the bonding interface from the length of the bonded interface peeled off (SOI). Science, Realize, p. 300).
  • the present invention manages the time from the bonding of the wafers to the peeling heat treatment in the manufacture of bonded wafers using the ion implantation peeling method.
  • bonding is performed from the viewpoint of productivity.
  • the present invention is characterized in that the peeling heat treatment is performed after 6 hours or more after bonding.
  • the direction of water molecules that contribute to the bonding interface bonding force that is, the positive and negative polarity of water molecules is neatly aligned to increase the bonding force at the bonding interface. It is important to make it efficiently bind to.
  • the direction of water molecules at the bonding interface is often irregular, but for water molecules, alignment is smaller in energy and more stable.
  • FIG. 2A shows a state in which water molecules are randomly bonded at the bonding interface immediately after bonding
  • FIG. 2B shows the bonding interface after being held for a long time after bonding. Shows a state in which water molecules are aligned and bonded.
  • FIG. 1 is a flowchart showing an example of an embodiment of a method for producing a bonded wafer according to the present invention.
  • two silicon single crystal bare wafers are prepared as the bond wafer 10 and the base wafer 20.
  • wafers such as polished wafers (PW), epitaxial wafers, heat-treated wafers, etc.
  • PW polished wafers
  • epitaxial wafers epitaxial wafers
  • heat-treated wafers etc.
  • the wafer material is not limited to silicon, and the present invention can also be applied to compound semiconductors or quartz, metals, etc. in addition to semiconductor materials, and also to patterned wafers such as devices.
  • the insulating films 12 and 21 are formed on both the bond wafer 10 and the base wafer 20 in advance. However, the insulating films may be formed on only one of the wafers. Both may not be formed.
  • an insulating film is formed on both wafers, and bonding is conventionally performed with particularly low bonding strength, such as when bonding is performed through the insulating films. Even a wafer can be peeled off with a high bonding strength by the manufacturing method of the present invention, so that a bonded wafer having a good thin film with a reduced terrace width can be manufactured.
  • the insulating film formed at this time for example, a thermal oxide film, a CVD oxide film, or the like can be formed.
  • the insulating film formed on each wafer may be formed only on the bonding surface in addition to being formed on the entire surface of the wafer including the back surface.
  • step (b) at least one kind of gas ion of hydrogen ion or rare gas ion is ion-implanted from the surface of the insulating film 12 of the bond wafer 10 to form the ion-implanted layer 11 inside the wafer.
  • other ion implantation conditions such as implantation energy, implantation amount, and implantation temperature can be appropriately selected so that a thin film having a predetermined thickness can be obtained.
  • the insulating film 12 of the bond wafer 10 and the insulating film 21 of the base wafer 20 are adhered and bonded together.
  • the bonding strength of either or both wafers can be increased by plasma treatment.
  • RCA cleaning can be performed before bonding to remove particles and organic substances adhering to the wafer surface, so that better bonding can be performed.
  • the bonded wafer is held for 6 hours or more until a peeling heat treatment is performed.
  • the alignment of water molecules contributing to bonding at the bonding interface progresses after 6 hours or more after bonding until the heat treatment for peeling (see FIG. 2). Therefore, even if the heat treatment is performed at a relatively low temperature in the subsequent peeling heat treatment, peeling occurs in a state where the bonding strength at the bonding interface is high.
  • the bonded wafer for 12 hours or more, and more preferably for 48 hours or more until the peeling heat treatment is performed.
  • the bond strength is further increased.
  • the upper limit of the time until the heat treatment for peeling after bonding at this time the bond strength increases up to about 100 hours, but when the time exceeds 100 hours, no further increase in bond strength is observed, so that the viewpoint of productivity is increased. Therefore, the upper limit is preferably set to 100 hours.
  • Such holding time can be adjusted in accordance with the product specifications within a range in which the yield can be secured.
  • the temperature at which the wafer is held after the bonding is performed until the separation heat treatment is performed is not particularly limited as long as it is a temperature at which separation at the ion implantation layer does not occur (about 400 ° C. or less). It is preferable.
  • the wafer is held at room temperature until the peeling heat treatment is performed, no special cost is required after the bonding until the peeling heat treatment. Therefore, the manufacturing method of the present invention can be carried out easily and at low cost.
  • the peeling heat treatment is not particularly limited. For example, when a heat treatment boat made of SiC having a thermal conductivity close to that of silicon is used and the bonded wafer is heated to 500 to 600 ° C. in a nitrogen atmosphere, the heat treatment is performed. A defect layer called a cavity is formed in the ion implantation layer 11 in the bond wafer 10, and this defect layer is connected in the horizontal direction inside the bond wafer 10, whereby the bond wafer 10 is peeled off. Thereby, a part of the bond wafer 10 is transferred to the base wafer 20 to become the thin film 31, and the bonded wafer 30 is formed.
  • the bonded wafer manufactured by the manufacturing method of the present invention is subjected to the peeling heat treatment after the lapse of 6 hours or more after the bonding, so that the orientation of water molecules contributing to the bonding interface is aligned by the peeling heat treatment. Because the peeling heat treatment is performed in a state where the bonding strength is increased electrically and efficiently, the bonding strength is further increased at the temperature of the peeling heat treatment, and the bonding strength is higher than the case where the peeling heat treatment is performed immediately after the conventional bonding. Peeling occurs in the state, resulting in a good peel surface. Furthermore, particularly in the peripheral portion of the wafer where the bonding strength is low and the thin film is difficult to be transferred, the bonding strength is increased according to the present invention. Reduced.
  • the bonded wafer 30 thus manufactured is subjected to, for example, a bonding heat treatment for increasing the bonding strength at the bonding interface at 1000 ° C. or higher in an oxidizing atmosphere or a non-oxidizing atmosphere, and then the thin film 31 side is formed to a desired thickness.
  • the final bonded wafer is completed by performing polishing or sacrificial oxidation treatment to reduce the film thickness.
  • the bonded wafer manufactured by the manufacturing method of the present invention has a high-quality thin film with a reduced terrace width, the width of a high-quality semiconductor layer is widened, and the number of chips of a semiconductor device finally obtained Therefore, the product yield is improved.
  • the heat treatment was performed at 350 ° C. at which peeling does not occur in the hydrogen ion implanted layer, and then the bonding strength at the bonding interface was evaluated using a blade method.
  • the bonding strength at the bonding interface was investigated. As shown in (Retention time dependency of bonding interface bond strength), the bond strength, which was 1.0 J / m 2 immediately after bonding, improved with time and increased to 1.5 J / m 2 after 96 hours. It turned out to be high around. However, the interfacial bond strength was saturated after 96 hours, and was saturated at approximately 1.6 J / m 2 .
  • Example 2 After bonding, a peeling heat treatment was performed after 12 hours had elapsed.
  • 25 sets (50 sheets) of silicon bare wafers having a diameter of 5 inches (125 mm) were prepared as material wafers.
  • An oxide film having a thickness of 200 nm was formed on the bond wafer, and an oxide film having a thickness of 500 nm was formed on the base wafer.
  • a bond wafer is injected with hydrogen ions at an acceleration voltage of 80 keV and an injection amount of 7 ⁇ 10 16 / cm 2 , and is subjected to pre-bonding cleaning including RCA cleaning, and then bonded to the base wafer at room temperature. It was.
  • the wafer was put into a peeling heat treatment furnace after 12 hours at room temperature.
  • the peeling heat treatment was performed in a nitrogen atmosphere, the temperature was raised to 500 ° C. at 5 ° C./min, and the temperature was maintained at 500 ° C., and the bond wafer was peeled off and transferred to the base wafer with the hydrogen ion implanted layer. .
  • the widest terrace width of each wafer was 2.2 mm to 2.8 mm, and all passed the user standards specified for the terrace width of 3 mm. It was. Furthermore, the void defect rate generated after peeling was as low as 5%. From the above results, it was found that according to the manufacturing method of the present invention, peeling occurred in the hydrogen ion implanted layer with a high interface bond strength, so that the terrace width was narrowed and the product yield was improved.
  • the wafer was immediately put into the peeling heat treatment furnace (within 1 hour).
  • the peeling heat treatment was performed in a nitrogen atmosphere, the temperature was raised to 500 ° C. at 5 ° C./min, and the temperature was maintained at 500 ° C., and the bond wafer was peeled off and transferred to the base wafer with the hydrogen ion implanted layer. .
  • the widest terrace width portion of each wafer varied from 2.6 mm to 3.5 mm.
  • the terrace width is defined as 3 mm
  • defects due to the terrace width frequently occur, and the manufacturing yield deteriorates.
  • the void defect rate generated after peeling was as high as 20%. From the above results, it was found that in the comparative example, peeling occurred in the hydrogen ion implanted layer in a state where the interface bond strength was low, so that the terrace width was widened and the product yield was decreased.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

L’invention concerne un procédé de fabrication d’une plaquette liée, dans lequel des ions gazeux d’au moins un type comme des ions hydrogène et des ions de gaz rares sont implantés depuis au moins la surface d’une plaquette liée pour former ainsi une couche à implantation ionique dans la plaquette, dans lequel la surface à implantation ionique de la plaquette liée et la surface d’une plaquette de base sont collées l’une à l’autre directement ou via une couche isolante, et dans lequel un traitement thermique d’écaillage est ensuite réalisé pour écailler la plaquette liée au niveau de la couche à implantation ionique afin de fabriquer la plaquette liée.  Au bout de six heures après la liaison, le traitement thermique d’écaillage est réalisé pour écailler la plaquette liée au niveau de la couche à implantation ionique.  Par conséquent, le procédé de fabrication de la plaquette liée permet de réduire la largeur de terrassement dans laquelle une pellicule mince n’est pas transférée au moment de l’écaillage dans un procédé d'écaillage par implantation d'ions, entraînant ainsi un excellent écaillage.
PCT/JP2009/001795 2008-06-03 2009-04-20 Procédé de fabrication d’une plaquette liée WO2009147778A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008145693A JP5339785B2 (ja) 2008-06-03 2008-06-03 貼り合わせウェーハの製造方法
JP2008-145693 2008-06-03

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WO2009147778A1 true WO2009147778A1 (fr) 2009-12-10

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013055184A (ja) * 2011-09-02 2013-03-21 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
CN111652518A (zh) * 2020-06-05 2020-09-11 全芯智造技术有限公司 用于分析工艺数据的方法和设备以及计算机可读介质

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6500845B2 (ja) * 2016-06-14 2019-04-17 信越半導体株式会社 貼り合わせウェーハの製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200080A (ja) * 1996-11-15 1998-07-31 Canon Inc 半導体部材の製造方法
WO2001011667A1 (fr) * 1999-08-04 2001-02-15 Commissariat A L'energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragilisation
JP2002134375A (ja) * 2000-10-25 2002-05-10 Canon Inc 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法
JP2006210899A (ja) * 2004-12-28 2006-08-10 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200080A (ja) * 1996-11-15 1998-07-31 Canon Inc 半導体部材の製造方法
WO2001011667A1 (fr) * 1999-08-04 2001-02-15 Commissariat A L'energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragilisation
JP2002134375A (ja) * 2000-10-25 2002-05-10 Canon Inc 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法
JP2006210899A (ja) * 2004-12-28 2006-08-10 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013055184A (ja) * 2011-09-02 2013-03-21 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
CN111652518A (zh) * 2020-06-05 2020-09-11 全芯智造技术有限公司 用于分析工艺数据的方法和设备以及计算机可读介质
CN111652518B (zh) * 2020-06-05 2023-10-13 全芯智造技术有限公司 用于分析工艺数据的方法和设备以及计算机可读介质

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