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WO2007023747A1 - 半導体チップおよびその製造方法ならびに半導体装置 - Google Patents

半導体チップおよびその製造方法ならびに半導体装置 Download PDF

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Publication number
WO2007023747A1
WO2007023747A1 PCT/JP2006/316264 JP2006316264W WO2007023747A1 WO 2007023747 A1 WO2007023747 A1 WO 2007023747A1 JP 2006316264 W JP2006316264 W JP 2006316264W WO 2007023747 A1 WO2007023747 A1 WO 2007023747A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
bump
connection confirmation
semiconductor
chip
Prior art date
Application number
PCT/JP2006/316264
Other languages
English (en)
French (fr)
Inventor
Osamu Miyata
Tadahiro Morifuji
Original Assignee
Rohm Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2005241520A external-priority patent/JP4791104B2/ja
Priority claimed from JP2005241521A external-priority patent/JP4723312B2/ja
Application filed by Rohm Co., Ltd. filed Critical Rohm Co., Ltd.
Priority to US11/990,875 priority Critical patent/US8653657B2/en
Publication of WO2007023747A1 publication Critical patent/WO2007023747A1/ja

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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Definitions

  • the present invention relates to a semiconductor device having a chip-on-chip structure or a flip-chip-bonding structure, a semiconductor chip applied to the semiconductor device, and a manufacturing method thereof.
  • a chip-on-chip structure is known in which a semiconductor chip surface is bonded to a surface of another semiconductor chip. .
  • a large number of function bumps and connection confirmation bumps are provided on the surface of each semiconductor chip.
  • a large number of functional bumps are arranged in a lattice at the center, and connection confirmation bumps are arranged at four corners.
  • the functional bumps are all formed at the same height (the amount of protrusion from the surface of the semiconductor chip) using a metal material such as copper (Cu).
  • a solder bonding material that can be alloyed with the material of the functional bump is formed at the tip of each functional bump of one semiconductor chip. Electrical and mechanical connection between the semiconductor chips is achieved by connecting each functional bump of one semiconductor chip and each functional bump of the other semiconductor chip via this solder bonding material. .
  • the bump for connection confirmation is formed using the same metal material as the functional bump and at the same height as the functional bump (the protruding amount of the surface force of the semiconductor chip). Yes. Also, a solder bonding material is formed at the tip of each connection confirmation bump of one semiconductor chip. Thereby, when both semiconductor chips are bonded in parallel to each other, each connection confirmation bump of one semiconductor chip and each connection confirmation bump of the other semiconductor chip are connected via the solder bonding material. Therefore, by examining the connection state between these connection confirmation bumps, the two semiconductor chips are bonded in parallel to each other. It can be determined whether or not the force is.
  • connection state between all the connection confirmation bumps is good, it can be determined that both semiconductor chips are bonded in parallel to each other. On the other hand, if even one of the connection confirmation bumps is defective, both semiconductor chips are not joined in parallel to each other (one semiconductor chip is tilted and joined to the other semiconductor chip). Can be determined.
  • Patent Document 1 JP-A-8-153747
  • an object of the present invention is to provide a semiconductor device and a semiconductor device that can accurately determine whether or not the semiconductor chip is bonded in parallel to a solid-state device such as another semiconductor chip. It is providing the semiconductor chip used for this, and its manufacturing method.
  • a semiconductor chip of the present invention for achieving the above object is a semiconductor chip bonded to a solid state device with the surface thereof facing each other, protruding from the surface by a first protrusion amount, A functional bump for electrical connection with a solid state device and a connection confirmation for confirming the state of electrical connection by the functional bump projecting from the surface with a second projection amount smaller than the first projection amount. Including bumps.
  • connection confirmation bump is formed lower than the functional bump, if the surface of the semiconductor chip is slightly inclined with respect to the solid device, the surface of the solid device and the semiconductor chip There is a wide gap between the part where the connection confirmation bump is connected in the solid device (for example, a pad or bump arranged on the surface of the solid device) and the tip of the connection confirmation bump. Arise. Therefore, bumps for connection confirmation When the solid device is bonded via the bonding material formed on the connection confirmation bump, even if the bonding material expands, the bonding material does not reach the solid device. Connection is not achieved. Therefore, it is possible to accurately determine whether or not the semiconductor chip is bonded in parallel to the solid state device based on the connection state between the connection confirmation bump and the solid state device.
  • the semiconductor chip includes a semiconductor substrate, a surface protective film covering a surface of the semiconductor substrate, and a pad opening formed between the semiconductor substrate and the surface protective film and formed in the surface protective film. It may further include an electrode pad arranged facing the surface.
  • the functional bump is provided on the electrode pad, penetrates through the pad opening, protrudes on the surface protective film with a first protrusion amount
  • the connection confirmation bump includes the electrode pad. Bulges from the semiconductor substrate side with respect to the semiconductor substrate, penetrates through a through-hole formed in the surface protective film, and protrudes on the surface protective film with a second protrusion amount smaller than the first protrusion amount. To do.
  • a semiconductor chip having this configuration includes a step of forming a surface protective film on a surface of a semiconductor substrate, a pad opening that exposes the electrode pad disposed on the semiconductor substrate, and the surface protective film It can be manufactured by a method including a step of forming a through hole penetrating the surface protective film, and a step of forming a functional bump penetrating the pad opening and a connection confirmation bump penetrating the through hole. .
  • the semiconductor device further includes an interlayer film interposed between the semiconductor substrate and the surface protective film, and the electrode pad is disposed on the surface of the semiconductor substrate, and the connection confirmation bump includes a surface force bulge of the interlayer film. You may do it.
  • connection confirmation bumps may be raised from the surface of the semiconductor substrate.
  • a semiconductor device of the present invention has a first semiconductor chip and a second semiconductor chip that are opposed to the surface of the first semiconductor chip on the surface of the second semiconductor chip.
  • the first semiconductor chip side connection confirmation bump and the surface force of the second semiconductor chip protrude with the first protrusion amount, and the first semiconductor chip A second semiconductor chip-side functional bump connected to the top-side functional bump to achieve electrical connection between the first semiconductor chip and the second semiconductor chip, and a surface force of the second semiconductor chip Projecting with a second projecting amount smaller than the first projecting amount and connected to the first semiconductor chip side connection confirmation bump, the electrical connection between the first semiconductor chip and the second semiconductor chip 2nd semiconductor chip side connection confirmation bump for confirming the state.
  • the second semiconductor chip side connection confirmation bump is formed lower than the second semiconductor chip side functional bump, the surface of the second semiconductor chip is placed on the surface of the first semiconductor chip. If it is tilted slightly, the first semiconductor chip side connection confirmation bump and the second semiconductor chip are opposed to each other in a portion where the distance between the surface of the first semiconductor chip and the surface of the second semiconductor chip is wide. A wide gap is formed between the side connection confirmation bumps. Therefore, when these connection confirmation bumps are bonded via the bonding material formed on one of the connection confirmation bumps, even if the bonding material expands, the bonding material remains the other connection confirmation bump. Thus, the connection between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump is not achieved. Therefore, the second semiconductor chip is joined in parallel to the first semiconductor chip based on the connection state between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump. It is possible to accurately determine whether or not the force is present.
  • the first semiconductor chip side functional bump, the second semiconductor chip side functional bump, the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump are made of the same metal material. It may be formed.
  • the semiconductor device includes the first semiconductor chip side functional bump and the second semiconductor chip side functional bump, and the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection. Further comprising a connecting metal layer interposed between the confirmation bumps and alloyed with the metal material to achieve a connection therebetween.
  • the first semiconductor chip-side functional bump, the second semiconductor chip-side functional bump, the first semiconductor chip-side connection confirmation bump, and the second semiconductor chip-side connection confirmation bump are copper or gold. May be used.
  • the connecting metal The layers are the top surfaces of the first semiconductor chip-side functional bump and the first semiconductor chip-side connection confirmation bump, and Z or the second semiconductor chip-side functional bump and the second semiconductor chip-side connection confirmation bump. It may be formed of a solder bonding material provided in
  • the second semiconductor chip has a substantially rectangular shape when the surface is vertically looked down, and the second semiconductor chip-side functional bump is formed on the surface of the second semiconductor chip.
  • the second semiconductor chip side connection confirmation bumps are arranged at the center, and are arranged at each corner of the surface of the second semiconductor chip.
  • the second semiconductor chip side connection confirmation bumps are arranged at each corner of the surface of the second semiconductor chip. Therefore, when the surface of the second semiconductor chip is inclined with respect to the surface of the first semiconductor chip, at least one set of first semiconductor chip side connection confirmation bumps and second semiconductor chip side connection confirmation A wide gap is formed between the bumps. Therefore, the second semiconductor chip is joined in parallel to the first semiconductor chip based on the connection state between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump. It is possible to more accurately determine whether or not the force is applied.
  • the second semiconductor chip side connection confirmation bump is formed lower than the second semiconductor chip side functional bump, and the first semiconductor chip side connection confirmation bump is formed from the first semiconductor chip side functional bump. May be formed lower. That is, the first semiconductor chip side connection confirmation bump has a protrusion amount smaller than the protrusion amount of the surface force of the first semiconductor chip of the first semiconductor chip side functional bump, and The surface force may also protrude.
  • FIG. 1 is a schematic sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a sectional view schematically showing a configuration of a child chip.
  • FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the child chip in the order of processes.
  • FIG. 5 is a schematic cross-sectional view showing another configuration of a child chip (a configuration in which a bump for connection confirmation is raised on the surface of a semiconductor substrate).
  • FIG. 6 is a schematic cross-sectional view for explaining a modified example of the present invention (an embodiment in which the connection confirmation bump is formed lower than the functional bump in the parent chip), and (a) is a child chip.
  • the solder bonding material at the tip of the functional bump shows the state when it contacts the top surface of the functional bump of the parent chip, and (b) shows the state when the bonding between the parent chip and the child chip is completed.
  • FIG. 7 is a schematic plan view showing the configuration when the connection confirmation bump is electrically separated from the internal circuit force of the parent chip and the child chip.
  • FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • This semiconductor device has a chip-on-chip structure in which a parent chip 1 as a solid device and a child chip 2 as a semiconductor chip are overlapped and joined.
  • the parent chip 1 is formed in a substantially rectangular shape in plan view, and its surface (the surface of the surface protection film covering the active region side surface on which the device is formed on the semiconductor substrate forming the base of the parent chip 1) 3 is located above Die-bonded to the island part 5 of the lead frame 4 with the face-up attitude toward the top.
  • a substantially rectangular chip bonding area to which the child chip 2 is bonded is set at the center.
  • a plurality of functional bumps 6 are formed to protrude (protrude) in the chip bonding region.
  • bumps 7 for connection confirmation protrude from each corner in the chip bonding area.
  • the surface 3 of the parent chip 1 is provided with a plurality of external connection pads 8 at the peripheral edge surrounding the chip bonding region.
  • the external connection pad 8 is electrically connected (wire bonding) to the lead portion 10 of the lead frame 4 through the bonding wire 9.
  • the child chip 2 is formed in a substantially rectangular shape smaller than the parent chip 1 in a plan view, and the surface (surface of a surface protective film 25 described later) 11 is face-down with its face down. Bonded to the chip bonding area on the surface 3 of the chip 1.
  • functional bumps 12 connected to the functional bumps 6 of the parent chip 1 are formed so as to protrude.
  • connection confirmation bumps 13 connected to the connection confirmation bumps 7 of the parent chip 1 are formed so as to protrude from each corner of the surface 11 of the child chip 2.
  • the function bump 6 and the connection confirmation bump 7 of the parent chip 1 and the function bump 12 and the connection confirmation of the child chip 2 corresponding to these, respectively.
  • the bumps 13 are opposed to each other with their top surfaces facing each other, and are connected with a connection metal layer 14 interposed therebetween.
  • the parent chip 1 and the child chip 2 are electrically connected via the functional bumps 6 and 12 and mechanically connected in a state where a predetermined interval is maintained between them.
  • the parent chip 1 and the child chip 2 are sealed with a sealing resin 15 together with the lead frame 4 and the bonding wire 9. A part of the lead part 10 of the lead frame 4 is exposed from the sealing resin 15 and functions as an external connection part (outer lead part).
  • FIG. 2 is a cross-sectional view schematically showing the configuration of the child chip 2.
  • the child chip 2 has, for example, a multilayer wiring structure on a semiconductor substrate (for example, a silicon substrate) 21 that forms the base. Specifically, the child chip 2 is formed on the semiconductor substrate 21, the wiring layer 22 electrically connected to the device built in the semiconductor substrate 21, and the semiconductor substrate 21 and the wiring layer 22. Interlayer insulating film 23, electrode pad 24 disposed on interlayer insulating film 23 and electrically connected to wiring layer 22 through a via hole (not shown), interlayer insulating film 23 and electrode And a surface protective film 25 formed on the pad 24 and forming the outermost layer of the child chip 2.
  • a semiconductor substrate for example, a silicon substrate
  • a pad opening 26 is formed at a position facing the electrode pad 24, and the electrode pad 24 is exposed from the surface protective film 25 through the nod opening 26. Further, the surface protective film 25 is formed with a through-hole 27 penetrating the surface protective film 25 in a direction perpendicular to the surface 11 at the peripheral edge thereof.
  • the functional bumps 12 are provided on the electrode pads 24, penetrate the pad openings 26, It protrudes on the surface protective film 25 with a predetermined protrusion amount (for example, 20 m).
  • the connection confirmation bump 13 protrudes from the surface of the interlayer insulating film 23 facing the through hole 27, penetrates the through hole 27, and protrudes smaller than the protrusion amount of the functional bump 12 on the surface protective film 25. (For example, 18 m). That is, with reference to the surface 11 of the surface protective film 25, the connection confirmation bump 13 is formed to be lower by 1 to 5 / ⁇ ⁇ (preferably, 1 to 2 / ⁇ ⁇ ) than the functional bump 12.
  • the functional bumps 6 and 12 and the connection confirmation bumps 7 and 13 are all formed using the same metal material (for example, copper or gold).
  • the functional bumps 6 and the connection confirmation bumps 7 are all formed at the same height (the amount of protrusion from the surface 3 of the parent chip 1).
  • FIG. 3 is a cross-sectional view schematically showing the connection portions of the functional bumps 6 and 12 and the connection portions of the connection confirmation bumps 7 and 13.
  • solder bumps are placed on the front ends of the functional bumps 12 and the connection confirmation bumps 13 of the child chip 2. 16 is formed.
  • the solder bonding material 16 at the tip of the functional bump 12 is the function of the parent chip 1 in the process in which the parent chip 1 and the child chip 2 are joined.
  • a gap D is formed between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7 of the parent chip 1.
  • the solder bonding material 16 at the tip of all the connection confirmation bumps 13 and the top surfaces of the connection confirmation bumps 7 The gap D is an interval corresponding to the height difference between the functional bump 12 and the connection confirmation bump 13. Therefore, when heat treatment is subsequently performed, the solder bonding material 16 at the tip of the connection confirmation bump 13 melts and expands, and the solder bonding material 16 causes all of the connection confirmation bumps 7 and 13 to be connected. Connected. Then, as shown in FIG. 3 (b), the solder bonding material 16 between the functional bumps 6 and 12 facing each other and between the bumps 7 and 13 for connection confirmation becomes the connection metal layer 14, and between each of them. Good connection (conduction) is achieved.
  • the parent chip 1 when the surface 11 of the child chip 2 is inclined with respect to the surface 3 of the parent chip 1, the parent chip 1 The distance between the surface 3 of the chip 2 and the surface 11 of the child chip 2 is wide, partly narrow, and part is formed, between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7. The gap D is wide or narrow. Then, in a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide, the gap between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7 Spacing force of D Wider than the difference in height between the function bump 12 and the connection confirmation bump 13.
  • the tip of the connection confirmation bump 13 at the time of heat treatment is applied to the portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide. Even if the solder bonding material 16 expands, the solder bonding material 16 does not reach the top surface of the connection confirmation bump 7 and the connection between the connection confirmation bumps 7 and 13 cannot be achieved.
  • connection confirmation bumps 7 and 13 are connected, it can be determined that the child chip 2 is bonded in parallel to the parent chip 1, and V, If the connection between one set of bumps 7 and 13 for connection confirmation is not achieved, the child chip 2 is tilted and joined to the parent chip 1 (they are joined in parallel). Can be determined.
  • connection confirmation bump 7 of the parent chip 1 is formed at the same height as the function bump 6, and the connection confirmation bump 13 of the child chip 2 is formed at the same height as the function bump 12. Even if the child chip 2 is tilted and joined to the parent chip 1, the front end of the connection confirmation bump 13 is formed at a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide. The gap formed between the solder bonding material 16 of the part and the top surface of the connection confirmation bump 7 is small. Therefore, when the solder joint material 16 melts and expands, the solder joint material 16 reaches the top surface of the connection confirmation bump 7, and the connection between the connection confirmation bumps 7 and 13 is achieved.
  • connection confirmation bumps 13 of the child chip 2 are formed lower than the functional bumps 12, the surface 11 of the child chip 2 is formed on the surface 3 of the parent chip 1. If it is tilted slightly, the solder bonding material 16 at the tip of the connection confirmation bump 13 and the connection confirmation bump 7 of the connection confirmation bump 13 are formed in a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide. A wide gap is formed between the top surface. Therefore, the solder joint material 16 expands. However, the solder joint material 16 does not reach the top surface of the connection confirmation bump 7 and the connection between the connection confirmation bumps 7 and 13 is not achieved. Therefore, it is possible to accurately determine whether or not the child chip 2 is bonded in parallel to the parent chip 1.
  • FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the child chip 2 in the order of steps.
  • silicon nitride or silicon oxide is deposited on the entire surface of the semiconductor substrate 21 on which the wiring layer 22, the interlayer insulating film 23, and the electrode pad 24 are formed.
  • the surface protective film 25 is formed.
  • Silicon nitride or silicon oxide can be deposited by the CV D method.
  • a pad opening 26 and a through hole 27 are formed through the surface protective film 25 by photolithography.
  • a metal material is deposited in the pad opening 26 and the through hole 27 by a selective squeezing method, and the functional bump 12 and the connection confirmation bump 13 are formed. Because the height position of the bottom surface of the pad opening 26 (surface of the electrode pad 24) and the bottom surface of the through hole 27 (surface of the interlayer insulating film 23) are different, the functional bump 12 and the connection confirmation bump 13 are formed in the same process. Thus, the functional bumps 12 and the connection confirmation bumps 13 having different heights (projections) from the surface of the surface protective film 25 can be obtained without requiring any special process.
  • the functional bump 12 and the connection confirmation bump 13 are not limited to this, and may be formed separately. That is, one of the functional bump 12 and the connection confirmation bump 13 may be formed first, and the other may be formed next.
  • FIG. 5 is a schematic cross-sectional view showing another configuration of the child chip 2.
  • parts corresponding to the parts shown in FIG. 2 are denoted by the same reference numerals as in FIG.
  • only differences from the child chip 2 having the configuration shown in FIG. 2 will be described and detailed description of each part will be omitted.
  • a communication hole 28 communicating with the through hole 27 of the surface protective film 25 is formed through the interlayer insulating film 23. Then, the bump 13 for connection confirmation protrudes from the surface cover of the semiconductor substrate 21, passes through the through hole 27, and protrudes smaller than the protruding amount of the functional bump 12 on the surface protective film 25 (for example, It protrudes at 15 m). Also with this configuration, the same effect as that of the configuration shown in FIG. 2 can be achieved.
  • connection confirmation bump 13 is formed lower than the functional bump 12 in the child chip 2, as shown in FIG.
  • the bump 7 may be formed lower than the functional bump 6.
  • the connection confirmation bumps 7 and 13 are connected to the solder bonding material 16 at the tip of the functional bump 12 in the process of bonding the parent chip 1 and the child chip 2.
  • the functional bump 12 and the connection confirmation bump 13 are formed at the same height in the child chip 2, and the connection confirmation bump 7 is formed lower than the functional bump 6 in the parent chip 1.
  • the parent chip 1 and the child chip 2 are the first semiconductor chip and the second semiconductor chip, respectively, the parent chip 1 is the second semiconductor chip and the child chip 2 is the first semiconductor chip. A chip may be used.
  • connection confirmation bumps 7, 13 may be connected to the internal circuits of the parent chip 1 and the child chip 2, respectively, or the internal circuits of the parent chip 1 and the child chip 2, respectively. It may be electrically disconnected.
  • connection confirmation bumps 7 and 13 are separated from the internal circuit cover, two sets of connection confirmation bumps 7 are placed at each corner of the chip bonding area in the parent chip 1 as shown in FIG.
  • external extraction electrodes 17 electrically connected to the respective connection confirmation bumps 7 are provided outside the chip bonding region.
  • one set of connection confirmation bumps 13 is arranged at each corner, and the two sets of connection confirmation bumps 13 are electrically connected to each other.
  • connection confirmation bumps 7 and 13 are connected to each other. Subsequently, since the external extraction electrodes 17 of each set are short-circuited, the electrical resistance between them is reduced. On the other hand, when the child chip 2 is joined to the parent chip 1 at an angle, the connection of the connection confirmation bumps 7 and 13 is not achieved in the portion where the distance between the surfaces is wide, and the connection between the external extraction electrodes 17 is not achieved. Therefore, the electrical resistance between them increases. Therefore, it is possible to accurately determine whether or not the child chip 2 is bonded in parallel to the parent chip 1 based on the measurement result of the electrical resistance between the external extraction electrodes 17 of each group. Monkey.
  • the present invention is applied to a flip-chip bonding structure semiconductor device in which the surface of the semiconductor chip is bonded to face the wiring substrate (solid device). May be applied.

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Abstract

　半導体チップが他の半導体チップなどの固体装置に対して平行に接合されているか否かを正確に判定することができる、半導体装置ならびにこれに用いられる半導体チップおよびその製造方法を提供する。半導体チップは、半導体チップの表面から第１の突出量で突出し、固体装置との電気接続のための機能バンプと、半導体チップの表面から第１の突出量よりも小さい第２の突出量で突出し、機能バンプによる電気接続の状態を確認するための接続確認用バンプとを含む。

Description

明 細 書
半導体チップおよびその製造方法ならびに半導体装置
技術分野
[0001] 本発明は、チップ ·オン ·チップ構造ゃフリップ ·チップ ·ボンディング構造の半導体 装置、ならびにこの半導体装置に適用される半導体チップおよびその製造方法に関 する。
背景技術
[0002] 半導体装置の小型化および高集積ィ匕を図るための構造として、たとえば、半導体 チップの表面を他の半導体チップの表面に対向させて接合するチップ ·オン ·チップ 構造が知られている。
チップ 'オン'チップ構造の半導体装置では、各半導体チップの表面に、多数の機 能バンプおよび接続確認用バンプが設けられる。たとえば、各半導体チップの表面 において、その中央部に多数の機能バンプが格子状に配列され、 4つの角部に接続 確認用バンプが配置される。
[0003] 各半導体チップにぉ 、て、機能バンプは、銅 (Cu)などの金属材料を用いて、すべ て同じ高さ（半導体チップの表面からの突出量）に形成されている。また、一方の半 導体チップの各機能バンプの先端部には、機能バンプの材料と合金化をなし得るは んだ接合材が形成されている。このはんだ接合材を介して、一方の半導体チップの 各機能バンプと他方の半導体チップの各機能バンプとが接続されることにより、半導 体チップ間における電気的および機械的な接続が達成される。
[0004] 一方、各半導体チップにお 、て、接続確認用バンプは、機能バンプと同じ金属材 料を用いて、機能バンプと同じ高さ（半導体チップの表面力 の突出量）に形成され ている。また、一方の半導体チップの各接続確認用バンプの先端部には、はんだ接 合材が形成されている。これにより、両半導体チップが互いに平行に接合された場合 には、一方の半導体チップの各接続確認用バンプと他方の半導体チップの各接続 確認用バンプとがはんだ接合材を介して接続される。したがって、それらの接続確認 用バンプ間の接続状態を調べることにより、両半導体チップが互いに平行に接合さ れている力否かを判定することができる。すなわち、すべての接続確認用バンプ間の 接続状態が良好であれば、両半導体チップは互いに平行に接合されて 、ると判定 することができる。一方、接続確認用バンプの接続状態が 1つでも不良であれば、両 半導体チップが互いに平行に接合されていない (一方の半導体チップが他方の半導 体チップに対して傾 ヽて接合されて ヽる）と判定することができる。
特許文献 1：特開平 8— 153747号公報
発明の開示
発明が解決しょうとする課題
[0005] ところが、従来の構成では、一方の半導体チップが他方の半導体チップに対して多 少傾いた状態で接合されても、接続確認用バンプの先端部のはんだ接合材が熱処 理時に溶融して膨張することにより、両半導体チップのすべての接続確認用バンプ が接続されるという不具合を生じることがあった。この場合、一方の半導体チップが他 方の半導体チップに対して傾いて接合されているにもかかわらず、両半導体チップ が互いに平行に接合されて ヽると判断されてしまう。
[0006] そこで、本発明の目的は、半導体チップが他の半導体チップなどの固体装置に対 して平行に接合されて 、る力否かを正確に判定することができる、半導体装置ならび にこれに用いられる半導体チップおよびその製造方法を提供することである。
課題を解決するための手段
[0007] 前記の目的を達成するための本発明の半導体チップは、固体装置にその表面を 対向させた状態で接合される半導体チップであって、前記表面から第 1の突出量で 突出し、前記固体装置との電気接続のための機能バンプと、前記表面から前記第 1 の突出量よりも小さい第 2の突出量で突出し、前記機能バンプによる電気接続の状 態を確認するための接続確認用バンプとを含む。
[0008] この構成では、接続確認用バンプが機能バンプよりも低く形成されているので、半 導体チップの表面が固体装置に対して少しでも傾いていると、固体装置と半導体チ ップの表面との間隔が広い部分において、固体装置において接続確認用バンプが 接続される部分 (たとえば、固体装置の表面に配置されたパッドまたはバンプ)と接続 確認用バンプの先端部との間に広い隙間が生じる。そのため、接続確認用バンプと 固体装置とが接続確認用バンプに形成された接合材を介して接合される場合に、接 合材が膨張しても、その接合材は固体装置に届かず、接続確認用バンプと固体装置 との接続が達成されない。よって、接続確認用バンプと固体装置との接続状態に基 づいて、半導体チップが固体装置に対して平行に接合されているか否かを正確に判 定することができる。
[0009] 前記半導体チップは、半導体基板と、前記半導体基板の表面を覆う表面保護膜と 、前記半導体基板と前記表面保護膜との間に介在され、前記表面保護膜に形成さ れたパッド開口に臨んで配置された電極パッドとをさらに含んでいてもよい。この場合 、前記機能バンプは、前記電極パッド上に設けられ、前記パッド開口を貫通して、前 記表面保護膜上に第 1の突出量で突出し、前記接続確認用バンプは、前記電極パ ッドよりも前記半導体基板側から隆起し、前記表面保護膜に貫通形成された貫通孔 を貫通して、前記表面保護膜上に前記第 1の突出量よりも小さい第 2の突出量で突 出する。
[0010] この構成の半導体チップは、半導体基板の表面に表面保護膜を形成する工程と、 前記表面保護膜に、前記半導体基板上に配置されている前記電極パッドを露出さ せるパッド開口および前記表面保護膜を貫通する貫通孔を形成する工程と、前記パ ッド開口を貫通する機能バンプおよび前記貫通孔を貫通する接続確認用バンプを形 成する工程とを含む方法により製造することができる。
[0011] 前記半導体基板と前記表面保護膜との間に介在され、その表面上に前記電極パッ ドが配置される層間膜をさらに含み、前記接続確認用バンプは、前記層間膜の表面 力 隆起していてもよい。
また、前記接続確認用バンプは、前記半導体基板の表面から隆起していてもよい。 前記の目的を達成するための本発明の半導体装置は、第 1の半導体チップと第 2 の半導体チップとを前記第 1の半導体チップの表面に前記第 2の半導体チップの表 面を対向させた状態で接合した、チップ ·オン ·チップ構造を有する半導体装置であ つて、前記第 1の半導体チップの表面力 突出する第 1半導体チップ側機能バンプと 、前記第 1の半導体チップの表面力 突出する第 1半導体チップ側接続確認用バン プと、前記第 2の半導体チップの表面力 第 1の突出量で突出し、前記第 1半導体チ ップ側機能バンプに接続されて、前記第 1の半導体チップと前記第 2の半導体チップ との電気接続を達成するための第 2半導体チップ側機能バンプと、前記第 2半導体 チップの表面力 前記第 1の突出量よりも小さい第 2の突出量で突出し、前記第 1半 導体チップ側接続確認用バンプと接続されて、前記第 1の半導体チップと前記第 2の 半導体チップとの電気接続の状態を確認するための第 2半導体チップ側接続確認 用バンプとを含む。
[0012] この構成では、第 2半導体チップ側接続確認用バンプが第 2半導体チップ側機能 バンプよりも低く形成されているので、第 2の半導体チップの表面が第 1の半導体チッ プの表面に対して少しでも傾いていると、第 1の半導体チップの表面と第 2の半導体 チップの表面との間隔が広い部分において、互いに対向する第 1半導体チップ側接 続確認用バンプと第 2半導体チップ側接続確認用バンプとの間に広い隙間が生じる 。そのため、それらの接続確認用バンプが一方の接続確認用バンプに形成された接 合材を介して接合される場合に、接合材が膨張しても、その接合材は他方の接続確 認用バンプに届かず、第 1半導体チップ側接続確認用バンプと第 2半導体チップ側 接続確認用バンプとの間の接続が達成されない。よって、第 1半導体チップ側接続 確認用バンプと第 2半導体チップ側接続確認用バンプとの間の接続状態に基づいて 、第 2の半導体チップが第 1の半導体チップに対して平行に接合されている力否かを 正確に判定することができる。
[0013] 前記第 1半導体チップ側機能バンプ、前記第 2半導体チップ側機能バンプ、前記 第 1半導体チップ側接続確認用バンプおよび前記第 2半導体チップ側接続確認用 バンプは、同じ金属材料を用いて形成されてもよい。そして、前記半導体装置は、前 記第 1半導体チップ側機能バンプと前記第 2半導体チップ側機能バンプとの間、およ び前記第 1半導体チップ側接続確認用バンプと前記第 2半導体チップ側接続確認 用バンプとの間にそれぞれ介在され、前記金属材料と合金化して、それらの間の接 続を達成するための接続金属層をさらに含んで 、てもよ 、。
[0014] たとえば、前記第 1半導体チップ側機能バンプ、前記第 2半導体チップ側機能バン プ、前記第 1半導体チップ側接続確認用バンプおよび前記第 2半導体チップ側接続 確認用バンプは、銅または金を用いて形成されてもよい。この場合、前記接続金属 層は、前記第 1半導体チップ側機能バンプおよび前記第 1半導体チップ側接続確認 用バンプ、ならびに Zまたは、前記第 2半導体チップ側機能バンプおよび前記第 2半 導体チップ側接続確認用バンプの頂面に設けられた、はんだ接合材により形成され てもよい。
[0015] 前記第 2の半導体チップは、その表面を垂直に見下ろしたときの形状が略矩形状 をなしており、前記第 2半導体チップ側機能バンプは、前記第 2の半導体チップの表 面の中央部に配置され、前記第 2半導体チップ側接続確認用バンプは、前記第 2の 半導体チップの表面の各角部に配置されて 、る。
この構成によれば、第 2の半導体チップの表面の各角部に、第 2半導体チップ側接 続確認用バンプが配置されている。そのため、第 2の半導体チップの表面が第 1の半 導体チップの表面に対して傾 、て 、ると、少なくとも 1組の第 1半導体チップ側接続 確認用バンプと第 2半導体チップ側接続確認用バンプとの間に広い隙間が生じる。 よって、第 1半導体チップ側接続確認用バンプと第 2半導体チップ側接続確認用バ ンプとの間の接続状態に基づいて、第 2の半導体チップが第 1の半導体チップに対 して平行に接合されている力否かをより正確に判定することができる。
[0016] 前記第 2半導体チップ側接続確認用バンプが前記第 2半導体チップ側機能バンプ よりも低く形成されるとともに、前記第 1半導体チップ側接続確認用バンプが前記第 1 半導体チップ側機能バンプよりも低く形成されてもよい。すなわち、前記第 1半導体 チップ側接続確認用バンプは、前記第 1半導体チップ側機能バンプの前記第 1の半 導体チップの表面力 の突出量よりも小さい突出量で、前記第 1の半導体チップの表 面力も突出していてもよい。
[0017] 本発明における上述の、またはさらに他の目的、特徴および効果は、添付図面を 参照して次に述べる実施形態の説明により明らかにされる。
図面の簡単な説明
[0018] [図 1]この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図である [図 2]子チップの構成を図解的に示す断面図である。
[図 3]親チップおよび子チップ間における機能バンプの接続部分および接続確認用 バンプの接続部分の図解的な断面図であり、（a)は、子チップの機能バンプの先端 部のはんだ接合材が親チップの機能バンプの頂面に接触した時の状態を示し、 (b) は、親チップと子チップとの接合が完了した時の状態を示す。
[図 4]子チップの製造工程を工程順に示す図解的な断面図である。
[図 5]子チップの他の構成 (接続確認用バンプが半導体基板の表面力 隆起した構 成)を示す図解的な断面図である。
[図 6]この発明の変形例 (親チップにおいても、接続確認用バンプが機能バンプよりも 低く形成された態様)を説明するための図解的な断面図であり、（a)は、子チップの 機能バンプの先端部のはんだ接合材が親チップの機能バンプの頂面に接触した時 の状態を示し、（b)は、親チップと子チップとの接合が完了した時の状態を示す。
[図 7]接続確認用バンプが親チップおよび子チップの内部回路力 電気的に切り離 された場合の構成を示す図解的な平面図である。
発明を実施するための最良の形態
以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図 1は、この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図で ある。
この半導体装置は、固体装置としての親チップ 1と半導体チップとしての子チップ 2 とを重ね合わせて接合したチップ ·オン ·チップ構造を有して 、る。
親チップ 1は、平面視略矩形状に形成されており、その表面 (親チップ 1の基体をな す半導体基板におけるデバイスが形成された活性領域側表面を覆う表面保護膜の 表面） 3を上方に向けたフェイスアップ姿勢で、リードフレーム 4のアイランド部 5にダイ ボンディングされている。この親チップ 1の表面 3には、その中央部に、子チップ 2が 接合される略矩形状のチップ接合領域が設定されている。そして、チップ接合領域 内に、複数の機能バンプ 6が突出（隆起)して形成されている。また、チップ接合領域 内の各角部には、接続確認用バンプ 7が突出して形成されている。さらに、親チップ 1の表面 3には、チップ接合領域を取り囲む周縁部に、複数の外部接続用パッド 8が 設けられている。この外部接続用パッド 8は、ボンディングワイヤ 9を介して、リードフレ ーム 4のリード部 10に電気的に接続 (ワイヤボンディング）されている。 [0020] 子チップ 2は、平面視において親チップ 1よりも小さな略矩形状に形成されており、 その表面 (後述する表面保護膜 25の表面） 11を下方に向けたフェイスダウン姿勢で 、親チップ 1の表面 3のチップ接合領域に接合されている。この子チップ 2の表面 11 には、親チップ 1の機能バンプ 6とそれぞれ接続される機能バンプ 12が突出して形成 されている。また、子チップ 2の表面 11の各角部には、親チップ 1の接続確認用バン プ 7とそれぞれ接続される接続確認用バンプ 13が突出して形成されている。
[0021] 親チップ 1と子チップ 2とが接合された状態で、親チップ 1の機能バンプ 6および接 続確認用バンプ 7とこれらにそれぞれ対応する子チップ 2の機能バンプ 12および接 続確認用バンプ 13とは、互いに頂面を突き合わせて対向し、それらの間に介在され る接続金属層 14を挟んで接続されている。これにより、親チップ 1および子チップ 2は 、機能バンプ 6, 12を介して、電気的に接続され、かつ、互いの間に所定間隔を保つ た状態で機械的に接続されている。また、親チップ 1および子チップ 2は、リードフレ ーム 4およびボンディングワイヤ 9とともに、封止榭脂 15により封止されている。リード フレーム 4のリード部 10の一部は、封止榭脂 15から露出し、外部接続部（アウターリ ード部)として機能する。
[0022] 図 2は、子チップ 2の構成を図解的に示す断面図である。
子チップ 2は、たとえば、その基体をなす半導体基板 (たとえば、シリコン基板) 21上 に多層配線構造を有している。具体的には、子チップ 2は、半導体基板 21上に、半 導体基板 21に作り込まれているデバイスと電気的に接続された配線層 22と、半導体 基板 21および配線層 22上に形成された層間絶縁膜 23と、この層間絶縁膜 23上に 配置されて、配線層 22とビアホール（図示せず)を介して電気的に接続された電極パ ッド 24と、層間絶縁膜 23および電極パッド 24上に形成されて、子チップ 2の最表層 をなす表面保護膜 25とを備えて 、る。
[0023] 表面保護膜 25には、電極パッド 24と対向する位置にパッド開口 26が形成されてお り、電極パッド 24は、そのノッド開口 26を介して表面保護膜 25から露出している。ま た、表面保護膜 25には、その周縁部に、表面保護膜 25をその表面 11と直交する方 向に貫通する貫通孔 27が形成されて 、る。
そして、機能バンプ 12は、電極パッド 24上に設けられ、パッド開口 26を貫通して、 表面保護膜 25上に所定の突出量 (たとえば、 20 m)で突出している。また、接続確 認用バンプ 13は、貫通孔 27に臨む層間絶縁膜 23の表面から隆起し、貫通孔 27を 貫通して、表面保護膜 25上に機能バンプ 12の突出量よりも小さな突出量 (たとえば 、 18 m)で突出している。すなわち、表面保護膜 25の表面 11を基準として、接続 確認用バンプ 13は、機能バンプ 12よりも 1〜5 /ζ πι (好ましくは、 1〜2 /ζ πι)だけ低く 形成されている。
[0024] なお、この実施形態では、機能バンプ 6, 12および接続確認用バンプ 7, 13は、す ベて同じ金属材料 (たとえば、銅または金)を用いて形成されている。また、親チップ 1において、機能バンプ 6および接続確認用バンプ 7は、すべて同じ高さ（親チップ 1 の表面 3からの突出量）に形成されている。
図 3は、機能バンプ 6, 12の接続部分および接続確認用バンプ 7, 13の接続部分 を図解的に示す断面図である。
[0025] 図 3 (a)に示すように、親チップ 1と子チップ 2との接合前の状態において、子チップ 2の機能バンプ 12および接続確認用バンプ 13の先端部には、はんだ接合材 16が 形成されている。
機能バンプ 12と接続確認用バンプ 13との高さの違いにより、親チップ 1と子チップ 2とが接合される過程において、機能バンプ 12の先端部のはんだ接合材 16が親チッ プ 1の機能バンプ 6の頂面に接触した時点で、接続確認用バンプ 13の先端部のはん だ接合材 16と親チップ 1の接続確認用バンプ 7の頂面との間に隙間 Dが生じる。
[0026] 親チップ 1の表面 3と子チップ 2の表面 11とが互いに平行であれば、すべての接続 確認用バンプ 13の先端部のはんだ接合材 16と接続確認用バンプ 7の頂面との間の 隙間 Dは、機能バンプ 12と接続確認用バンプ 13との高さの差に相当する間隔となる 。したがって、その後に熱処理が行われると、接続確認用バンプ 13の先端部のはん だ接合材 16が溶融して膨張し、そのはんだ接合材 16により、すべての接続確認用 バンプ 7, 13間が接続される。そして、図 3 (b)に示すように、互いに対向する各機能 バンプ 6, 12間および各接続確認用バンプ 7, 13間のはんだ接合材 16が接続金属 層 14となって、それらの各間の良好な接続 (導通）が達成される。
[0027] 一方、子チップ 2の表面 11が親チップ 1の表面 3に対して傾いていると、親チップ 1 の表面 3と子チップ 2の表面 11との間隔が広 、部分と狭 、部分とが生じ、接続確認 用バンプ 13の先端部のはんだ接合材 16と接続確認用バンプ 7の頂面との間の隙間 Dに広狭が生じる。そして、親チップ 1の表面 3と子チップ 2の表面 11との間隔が広い 部分では、接続確認用バンプ 13の先端部のはんだ接合材 16と接続確認用バンプ 7 の頂面との間の隙間 Dの間隔力 機能バンプ 12と接続確認用バンプ 13との高さの 差よりも広くなる。そのため、はんだ接合材 16の量が適当な一定量であれば、親チッ プ 1の表面 3と子チップ 2の表面 11との間隔が広い部分において、熱処理時に接続 確認用バンプ 13の先端部のはんだ接合材 16が膨張しても、そのはんだ接合材 16 が接続確認用バンプ 7の頂面に届かず、接続確認用バンプ 7, 13間の接続が達成さ れない。
[0028] したがって、すべての接続確認用バンプ 7, 13間の接続が達成されていれば、子 チップ 2が親チップ 1に対して平行に接合されて 、ると判定することができ、 V、ずれか 1組の接続確認用バンプ 7, 13間の接続が達成されていなければ、子チップ 2が親 チップ 1に対して傾 、て接合されて 、る（平行に接合されて 、な 、）と判定することが できる。
従来の構成と同様に、親チップ 1の接続確認用バンプ 7が機能バンプ 6と同じ高さ に形成され、子チップ 2の接続確認用バンプ 13が機能バンプ 12と同じ高さに形成さ れている場合、子チップ 2が親チップ 1に対して傾いて接合されても、親チップ 1の表 面 3と子チップ 2の表面 11との間隔が広い部分において、接続確認用バンプ 13の先 端部のはんだ接合材 16と接続確認用バンプ 7の頂面との間に生じる隙間は僅かで ある。そのため、はんだ接合材 16が溶融して膨張すると、そのはんだ接合材 16が接 続確認用バンプ 7の頂面に達し、接続確認用バンプ 7, 13間の接続が達成されてし まつ。
[0029] これに対し、この実施形態の構成では、子チップ 2の接続確認用バンプ 13が機能 バンプ 12よりも低く形成されているので、子チップ 2の表面 11が親チップ 1の表面 3 に対して少しでも傾いていると、親チップ 1の表面 3と子チップ 2の表面 11との間隔が 広い部分において、接続確認用バンプ 13の先端部のはんだ接合材 16と接続確認 用バンプ 7の頂面との間に広い隙間が生じる。そのため、はんだ接合材 16が膨張し ても、そのはんだ接合材 16が接続確認用バンプ 7の頂面に届かず、接続確認用バ ンプ 7, 13間の接続が達成されない。よって、子チップ 2が親チップ 1に対して平行に 接合されている力否かを正確に判定することができる。
[0030] 図 4は、子チップ 2の製造工程を工程順に示す図解的な断面図である。
まず、図 4 (a)に示すように、配線層 22、層間絶縁膜 23および電極パッド 24が形成 された半導体基板 21上の全面に、たとえば、窒化シリコンまたは酸ィ匕シリコンが堆積 されることにより表面保護膜 25が形成される。窒化シリコンまたは酸ィ匕シリコンは、 CV D法により堆積させることができる。
[0031] 次に、図 4 (b)に示すように、フォトリソグラフイエ程により、表面保護膜 25に、パッド 開口 26および貫通孔 27が貫通形成される。
その後、図 4 (c)に示すように、選択めつき法により、パッド開口 26および貫通孔 27 内に金属材料が堆積されて、機能バンプ 12および接続確認用バンプ 13が形成され る。パッド開口 26の底面（電極パッド 24の表面）と貫通孔 27の底面 (層間絶縁膜 23 の表面）との高さ位置が異なるので、機能バンプ 12と接続確認用バンプ 13とを同一 工程で形成することにより、特別な工程を必要とせずに、表面保護膜 25の表面に対 する高さ（突出量）が互いに異なる機能バンプ 12および接続確認用バンプ 13を得る ことができる。
[0032] なお、これに限らず、機能バンプ 12および接続確認用バンプ 13は、それぞれ別ェ 程で形成されてもよい。すなわち、機能バンプ 12および接続確認用バンプ 13の一方 が先に形成され、他方が次に形成されてもよい。
図 5は、子チップ 2の他の構成を示す図解的な断面図である。この図 5において、図 2に示す各部に相当する部分には、図 2の場合と同一の参照符号を付して示してい る。また、以下では、図 2に示す構成の子チップ 2との相違点のみを取り上げて説明 し、各部の詳細な説明は省略する。
[0033] この図 5に示す子チップ 2では、層間絶縁膜 23に、表面保護膜 25の貫通孔 27と連 通する連通孔 28が貫通して形成されている。そして、接続確認用バンプ 13は、半導 体基板 21の表面カゝら隆起し、貫通孔 27を貫通して、表面保護膜 25上に機能バンプ 12の突出量よりも小さな突出量 (たとえば、 15 m)で突出している。 この構成によっても、図 2に示す構成の場合と同様な効果を達成することができる。
[0034] 以上、この発明の一実施形態を説明した力 この発明は他の形態で実施することも できる。たとえば、上述の実施形態では、子チップ 2において、接続確認用バンプ 13 が機能バンプ 12よりも低く形成されているとした力 図 6に示すように、親チップ 1に おいても、接続確認用バンプ 7が機能バンプ 6よりも低く形成されてもよい。この場合 、図 6 (a)に示すように、接続確認用バンプ 7, 13は、親チップ 1と子チップ 2とが接合 される過程において、機能バンプ 12の先端部のはんだ接合材 16が親チップ 1の機 能バンプ 6の頂面に接触した時点で、接続確認用バンプ 13の先端部のはんだ接合 材 16と親チップ 1の接続確認用バンプ 7の頂面との間に、 1〜5 /ζ πι (好ましくは、 1〜 2 m)の隙間 Dが生じるような高さにそれぞれ形成されるとよい。このように形成すれ ば、図 6 (b)に示すように、親チップ 1の表面 3と子チップ 2の表面 11とが互いに平行 であれば、互いに対向する各機能バンプ 6, 12間および各接続確認用バンプ 7, 13 間のはんだ接合材 16が接続金属層 14となって、それらの各間の良好な接続が達成 される。
[0035] また、子チップ 2において、機能バンプ 12と接続確認用バンプ 13とが同じ高さに形 成され、親チップ 1において、接続確認用バンプ 7が機能バンプ 6よりも低く形成され てもよい。すなわち、この実施形態では、親チップ 1および子チップ 2をそれぞれ第 1 の半導体チップおよび第 2の半導体チップとしたが、親チップ 1を第 2の半導体チップ とし、子チップ 2を第 1の半導体チップとしてもよい。
[0036] さらにまた、接続確認用バンプ 7, 13は、それぞれ親チップ 1および子チップ 2の内 部回路と接続されていてもよいし、それぞれ親チップ 1および子チップ 2の内部回路 カゝら電気的に切り離されていてもよい。接続確認用バンプ 7, 13が内部回路カゝら切り 離される場合、図 7に示すように、親チップ 1において、チップ接合領域の各角部に 2 個 1組の接続確認用バンプ 7が配置されるとともに、チップ接合領域外に各接続確認 用バンプ 7と電気的に接続された外部取出用電極 17が設けられる。一方、子チップ 2 において、各角部に 2個 1組の接続確認用バンプ 13が配置されるとともに、その 2個 1組の接続確認用バンプ 13が互いに電気的に接続される。これにより、親チップ 1と 子チップ 2とが平行をなして接合されると、各組の接続確認用バンプ 7, 13の間が接 続されて、各組の外部取出用電極 17間が短絡されるので、これらの間の電気抵抗が 小さくなる。一方、子チップ 2が親チップ 1に対して傾いて接合されると、それらの表面 間の間隔が広い部分において、接続確認用バンプ 7, 13の接続が達成されず、外部 取出用電極 17間の電気的導通が得られないので、それらの間の電気抵抗が大きく なる。したがって、各組の外部取出用電極 17間の電気抵抗の測定結果に基づいて 、子チップ 2が親チップ 1に対して平行に接合されて 、る力否かを正確に判定するこ とがでさる。
また、チップ ·オン 'チップ構造の半導体装置を例示したが、この発明は、半導体チ ップの表面を配線基板（固体装置）に対向させて接合するフリップ ·チップ ·ボンディ ング構造の半導体装置に適用されてもよい。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが 可能である。すなわち、前述の実施形態は、本発明の技術的内容を明らかにするた めに用いられた具体例に過ぎず、本発明はこれらの具体例に限定して解釈されるべ きではなぐ本発明の精神および範囲は添付の請求の範囲によってのみ限定される この出願は、 2005年 8月 23日に日本国特許庁に提出された特願 2005— 24152 0号および特願 2005— 241521号に対応しており、これらの出願の全開示はここに 引用により組み込まれるものとする。

Claims

請求の範囲
[1] 固体装置にその表面を対向させた状態で接合される半導体チップであって、
前記表面から第 1の突出量で突出し、前記固体装置との電気接続のための機能バ ンプと、
前記表面から前記第 1の突出量よりも小さい第 2の突出量で突出し、前記機能バン プによる電気接続の状態を確認するための接続確認用バンプとを含む。
[2] 請求項 1に係る半導体チップにおいて、
半導体基板と、
前記半導体基板の表面を覆う表面保護膜と、
前記半導体基板と前記表面保護膜との間に介在され、前記表面保護膜に形成さ れたパッド開口に臨んで配置された電極パッドとをさらに含み、
前記機能バンプは、前記電極パッド上に設けられ、前記パッド開口を貫通して、前 記表面保護膜上に第 1の突出量で突出し、
前記接続確認用バンプは、前記電極パッドよりも前記半導体基板側から隆起し、前 記表面保護膜に貫通形成された貫通孔を貫通して、前記表面保護膜上に前記第 1 の突出量よりも小さ 、第 2の突出量で突出して 、る。
[3] 請求項 2に係る半導体チップにおいて、
前記半導体基板と前記表面保護膜との間に介在され、その表面上に前記電極パッ ドが配置される層間膜をさらに含み、
前記接続確認用バンプは、前記層間膜の表面から隆起している。
[4] 請求項 2に係る半導体チップにおいて、
前記接続確認用バンプは、前記半導体基板の表面から隆起して 、る。
[5] 固体装置にその表面を対向させた状態で接合される半導体チップを製造する方法 であって、
半導体基板の表面に表面保護膜を形成する工程と、
前記表面保護膜に、前記半導体基板上に配置されている前記電極パッドを露出さ せるパッド開口および前記表面保護膜を貫通する貫通孔を形成する工程と、 前記パッド開口を貫通する機能バンプおよび前記貫通孔を貫通する接続確認用バ ンプを形成する工程とを含む。
[6] 第 1の半導体チップと第 2の半導体チップとを前記第 1の半導体チップの表面に前 記第 2の半導体チップの表面を対向させた状態で接合した、チップ 'オン'チップ構 造を有する半導体装置であって、
前記第 1の半導体チップの表面力 突出する第 1半導体チップ側機能バンプと、 前記第 1の半導体チップの表面力 突出する第 1半導体チップ側接続確認用バン プと、
前記第 2の半導体チップの表面から第 1の突出量で突出し、前記第 1半導体チップ 側機能バンプに接続されて、前記第 1の半導体チップと前記第 2の半導体チップとの 電気接続を達成するための第 2半導体チップ側機能バンプと、
前記第 2半導体チップの表面力 前記第 1の突出量よりも小さい第 2の突出量で突 出し、前記第 1半導体チップ側接続確認用バンプと接続されて、前記第 1の半導体 チップと前記第 2の半導体チップとの電気接続の状態を確認するための第 2半導体 チップ側接続確認用バンプとを含む。
[7] 請求項 6に係る半導体装置において、
前記第 1半導体チップ側機能バンプ、前記第 2半導体チップ側機能バンプ、前記 第 1半導体チップ側接続確認用バンプおよび前記第 2半導体チップ側接続確認用 バンプは、同じ金属材料を用いて形成され、
前記第 1半導体チップ側機能バンプと前記第 2半導体チップ側機能バンプとの間、 および前記第 1半導体チップ側接続確認用バンプと前記第 2半導体チップ側接続確 認用バンプとの間にそれぞれ介在され、前記金属材料と合金化して、それらの間の 接続を達成するための接続金属層をさらに含む。
[8] 請求項 6に係る半導体装置において、
前記第 2の半導体チップは、その表面を垂直に見下ろしたときの形状が略矩形状 をなしており、
前記第 2半導体チップ側機能バンプは、前記第 2の半導体チップの表面の中央部 に配置され、
前記第 2半導体チップ側接続確認用バンプは、前記第 2の半導体チップの表面の 各角部に配置されている。
請求項 6に係る半導体装置において、
前記第 1半導体チップ側接続確認用バンプは、前記第 1半導体チップ側機能バン プの前記第 1の半導体チップの表面からの突出量よりも小さい突出量で、前記第 1の 半導体チップの表面から突出している。
PCT/JP2006/316264 2005-08-23 2006-08-18 半導体チップおよびその製造方法ならびに半導体装置 WO2007023747A1 (ja)

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