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WO2002047161A3 - Barriere anti debordement de colle fixation d'une puce semi-conductrice - Google Patents

Barriere anti debordement de colle fixation d'une puce semi-conductrice Download PDF

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Publication number
WO2002047161A3
WO2002047161A3 PCT/FR2001/003834 FR0103834W WO0247161A3 WO 2002047161 A3 WO2002047161 A3 WO 2002047161A3 FR 0103834 W FR0103834 W FR 0103834W WO 0247161 A3 WO0247161 A3 WO 0247161A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip
semiconductor chip
barrier against
fixing adhesive
against overflow
Prior art date
Application number
PCT/FR2001/003834
Other languages
English (en)
Other versions
WO2002047161A2 (fr
Inventor
Philippe Patrice
Jean-Christophe Fidalgo
Olivier Brunet
Yves-Pierre Cuenot
Original Assignee
Gemplus Card Int
Philippe Patrice
Jean-Christophe Fidalgo
Olivier Brunet
Yves-Pierre Cuenot
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card Int, Philippe Patrice, Jean-Christophe Fidalgo, Olivier Brunet, Yves-Pierre Cuenot filed Critical Gemplus Card Int
Priority to AU2002216172A priority Critical patent/AU2002216172A1/en
Publication of WO2002047161A2 publication Critical patent/WO2002047161A2/fr
Publication of WO2002047161A3 publication Critical patent/WO2002047161A3/fr

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne l'isolation électrique de puces (3) regroupés, avant leur collage (9, 13) unitaire. Elle vise les étapes prévoyant: d'appliquer une couche (14) diélectrique de protection sur au moins une face active (6) de puce (3) de la plaquette; de placer puis de fixer sur son substrat (8) la puce (3), par collage de sa face arrière, une périphérie de la couche de protection (14) formant barrière (15); et connecter après protection, au moins un plot de contact (10) au plot correspondant (7). L'invention s'applique à la fabrication d'objets portables intelligents, tels que cartes ou étiquettes à puces.
PCT/FR2001/003834 2000-12-05 2001-12-05 Barriere anti debordement de colle fixation d'une puce semi-conductrice WO2002047161A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002216172A AU2002216172A1 (en) 2000-12-05 2001-12-05 Barrier against overflow for fixing adhesive of a semiconductor chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR00/15941 2000-12-05
FR0015941A FR2817656B1 (fr) 2000-12-05 2000-12-05 Isolation electrique de microcircuits regroupes avant collage unitaire

Publications (2)

Publication Number Publication Date
WO2002047161A2 WO2002047161A2 (fr) 2002-06-13
WO2002047161A3 true WO2002047161A3 (fr) 2003-04-24

Family

ID=8857387

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/FR2001/003846 WO2002047151A2 (fr) 2000-12-05 2001-12-05 Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree
PCT/FR2001/003834 WO2002047161A2 (fr) 2000-12-05 2001-12-05 Barriere anti debordement de colle fixation d'une puce semi-conductrice

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/FR2001/003846 WO2002047151A2 (fr) 2000-12-05 2001-12-05 Method de fabrication d'une puce semi-conductrice a l'aide d'une couche de rigidite integree

Country Status (3)

Country Link
AU (2) AU2002216172A1 (fr)
FR (1) FR2817656B1 (fr)
WO (2) WO2002047151A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2845805B1 (fr) * 2002-10-10 2005-06-03 Gemplus Card Int Adhesif d'encartage formant navette
DE102006010523B3 (de) 2006-02-20 2007-08-02 Siemens Ag Verfahren zur Herstellung von planaren Isolierschichten mit positionsgerechten Durchbrüchen mittels Laserschneiden und entsprechend hergestellte Vorrichtungen
JP4303282B2 (ja) 2006-12-22 2009-07-29 Ｔｄｋ株式会社 プリント配線板の配線構造及びその形成方法
EP2357875A1 (fr) * 2010-02-16 2011-08-17 Gemalto SA Procédé pour fabriquer un boîtier électronique

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535970A (en) * 1976-07-07 1978-01-19 Toshiba Corp Semiconductor device
JPS53120271A (en) * 1977-03-29 1978-10-20 Mitsubishi Electric Corp Semiconductor device
JPS5760844A (en) * 1980-09-30 1982-04-13 Nec Corp Semiconductor device
US5144407A (en) * 1989-07-03 1992-09-01 General Electric Company Semiconductor chip protection layer and protected chip
FR2779272A1 (fr) * 1998-05-27 1999-12-03 Gemplus Card Int Procede de fabrication d'un micromodule et d'un support de memorisation comportant un tel micromodule
FR2779851A1 (fr) * 1998-06-12 1999-12-17 Gemplus Card Int Procede de fabrication d'une carte a circuit integre et carte obtenue
DE19845296A1 (de) * 1998-09-03 2000-03-16 Fraunhofer Ges Forschung Verfahren zur Kontaktierung eines Schaltungschips
FR2791471A1 (fr) * 1999-03-22 2000-09-29 Gemplus Card Int Procede de fabrication de puces de circuits integres

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3212110B2 (ja) * 1991-07-15 2001-09-25 沖電気工業株式会社 半導体素子の製造方法
JP3128878B2 (ja) * 1991-08-23 2001-01-29 ソニー株式会社 半導体装置
FR2735284B1 (fr) * 1995-06-12 1997-08-29 Solaic Sa Puce pour carte electronique revetue d'une couche de matiere isolante et carte electronique comportant une telle puce
FR2806189B1 (fr) * 2000-03-10 2002-05-31 Schlumberger Systems & Service Circuit integre renforce et procede de renforcement de circuits integres

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535970A (en) * 1976-07-07 1978-01-19 Toshiba Corp Semiconductor device
JPS53120271A (en) * 1977-03-29 1978-10-20 Mitsubishi Electric Corp Semiconductor device
JPS5760844A (en) * 1980-09-30 1982-04-13 Nec Corp Semiconductor device
US5144407A (en) * 1989-07-03 1992-09-01 General Electric Company Semiconductor chip protection layer and protected chip
FR2779272A1 (fr) * 1998-05-27 1999-12-03 Gemplus Card Int Procede de fabrication d'un micromodule et d'un support de memorisation comportant un tel micromodule
FR2779851A1 (fr) * 1998-06-12 1999-12-17 Gemplus Card Int Procede de fabrication d'une carte a circuit integre et carte obtenue
DE19845296A1 (de) * 1998-09-03 2000-03-16 Fraunhofer Ges Forschung Verfahren zur Kontaktierung eines Schaltungschips
FR2791471A1 (fr) * 1999-03-22 2000-09-29 Gemplus Card Int Procede de fabrication de puces de circuits integres

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 002, no. 040 (E - 022) 16 March 1978 (1978-03-16) *
PATENT ABSTRACTS OF JAPAN vol. 002, no. 150 (E - 078) 15 December 1978 (1978-12-15) *
PATENT ABSTRACTS OF JAPAN vol. 006, no. 136 (E - 120) 23 July 1982 (1982-07-23) *

Also Published As

Publication number Publication date
WO2002047151A2 (fr) 2002-06-13
WO2002047151B1 (fr) 2004-02-26
AU2002216182A1 (en) 2002-06-18
FR2817656B1 (fr) 2003-09-26
AU2002216172A1 (en) 2002-06-18
WO2002047161A2 (fr) 2002-06-13
FR2817656A1 (fr) 2002-06-07
WO2002047151A3 (fr) 2003-02-13

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