TWI852648B - Method for making enhancement-mode field effect transistor - Google Patents

Abstract

This invention provides a method for making an enhancement-mode field effect transistor, which comprises the steps of (a) forming sequentially an undoped Ga ₂O ₃layer and a n type Ga ₂O ₃layer on a substrate; (b) forming a dielectric layer on a portion of the n type Ga ₂O ₃layer; (c) forming a gate electrode on the dielectric layer and a source electrode and a drain electrode disposed apart from each other on the n type Ga ₂O ₃layer; and (d) after the steps of (a), (b) and (c), subjecting a self-aligned etching to the n type Ga ₂O ₃layer exposed to the gate electrode, the source electrode by using the gate electrode, the source electrode and the drain electrode as a metal mask such that a cross-sectional area of the etched n type Ga ₂O ₃layer was reduced.

Description

Method for manufacturing enhancement mode field effect transistor

The present invention relates to a method for manufacturing a field effect transistor, and in particular to a method for manufacturing an enhancement-mode field effect transistor.

With the rapid development of technology industries such as mobile communications, consumer electronics, and new energy vehicles, the demand for power semiconductor devices such as frequency conversion, rectification, voltage conversion, power amplification, and power control is also increasing. High electron mobility field effect transistors (HEMTs) composed of GaN are suitable for operation at high frequencies and high power densities due to their high voltage operation, low parasitic capacitance, and low on-resistance. Existing GaN high electron mobility field effect transistors are mainly divided into two structures: enhancement mode (hereinafter referred to as E-mode) transistors and depletion mode (hereinafter referred to as D-mode) transistors.

Although E-mode field effect transistors are easier to operate than D-mode field effect transistors, their critical voltage changes with temperature more than D-mode field effect transistors. Therefore, E-mode field effect transistors will operate slower at high temperatures and may also cause circuit failure. Although D-mode field effect transistors do not have the aforementioned problems of E-mode field effect transistors, they require additional driving circuits to convert them to E-mode operation. Both E-mode field effect transistors and D-mode field effect transistors have their own advantages and disadvantages.

For example, referring to FIG. 1, the Republic of China's early publication number TW202105740A invention patent case (hereinafter referred to as the previous case 1) discloses an enhanced metal insulated semiconductor high electron mobility transistor (HEMT) 1 and its manufacturing method. The manufacturing method disclosed in the previous case 1 is to first grow a buffer layer (not shown), a GaN active layer 122, an AlGaN barrier layer 123 and a silicon nitride layer 124 in sequence on a substrate (not shown) by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Next, a source ohmic contact 13S and a drain ohmic contact 13D are formed on opposite sides of the AlGaN barrier layer 123 and the silicon nitride layer 124. Subsequently, a passivation layer 14 is formed on the AlGaN barrier layer 123, the silicon nitride layer 124, the source ohmic contact 13S and the drain ohmic contact 13D by plasma assisted chemical vapor deposition (PECVD). After the passivation layer 14 is completed, the passivation layer 14, the AlGaN barrier layer 123 and the silicon nitride layer 124 are subjected to plasma etching in combination with a lithography process to form a recessed gate region 150 that exposes the GaN active layer 122, and exposes the source ohmic contact 13S and the drain ohmic contact 13D. An AlN/Al ₂ O ₃ dielectric stack 16 is further deposited in sequence by atomic layer deposition (ALD) to cover the passivation layer 14 and the recessed gate region 150. Finally, a gate contact 15, a source metal layer 17S and a drain metal layer 17D are formed in the recessed gate region 150 through the exposed source ohmic contact 13S and the drain ohmic contact 13D, respectively, thereby completing the enhanced metal-insulated semiconductor high electron mobility transistor 1 as shown in FIG. 1 .

According to the technical contents described in the specification of the prior art 1, the manufacturing method of the prior art 1 can obtain the sheet resistance caused by the two-dimensional electron gas (2DEG) 125 between the AlGaN barrier layer 123 and the silicon nitride layer 124 through in-situ measurement during the manufacturing process, for example, during the growth of the silicon nitride layer 124. However, the prior art 1 still needs to cooperate with the lithography process to form a patterned photoresist layer before forming the recessed gate region 150. In terms of the process, the process of the prior art 1 is complicated and it is not easy to control the etching depth.

As can be seen from the above description, improving the manufacturing method of enhancement field effect transistors to simplify the manufacturing process is a problem to be solved by relevant industry players in the relevant technical field.

Therefore, the object of the present invention is to provide a method for manufacturing an enhancement field effect transistor with a simplified manufacturing process.

Therefore, the method for manufacturing an enhancement mode field effect transistor of the present invention includes the following steps: step (a), step (b), step (c), and step (d).

The step (a) is to sequentially form an undoped gallium oxide (Ga ₂ O ₃ ) layer and an n-type gallium oxide layer on a substrate.

The step (b) is to form a gate dielectric layer on a region of the n-type gallium oxide layer.

The step (c) is to form a gate electrode and a source electrode and a drain electrode spaced apart from each other on the gate dielectric layer and the n-type gallium oxide layer, respectively.

The step (d) is to use the gate electrode, source electrode and drain electrode as a metal mask after the step (a), step (b) and step (c), and to perform a self-aligned etching on the n-type gallium oxide layer exposed outside the metal mask, so that a cross-section of the n-type gallium oxide layer after the self-aligned etching is reduced.

The effect of the present invention is that the step (d) directly uses the gate electrode, source electrode and drain electrode as metal masks when implementing the self-aligned etching, and the self-aligned etching can be implemented without additionally forming a patterned photoresist through a lithography process, so that the cross-sectional area of the n-type gallium oxide layer (channel) after the self-aligned etching is reduced, which can increase the impedance of the device (transistor) and make it easier to control.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

An embodiment of the method for manufacturing an enhancement mode field effect transistor of the present invention is substantially composed of the following steps: step (a), step (b), step (c), and step (d).

Referring to FIG. 2 , step (a) is to sequentially form a gallium nitride (GaN) buffer layer (not shown), an undoped gallium oxide layer 3, and an n-type gallium oxide layer 4 on a substrate 2. Preferably, in step (a), the undoped gallium oxide layer 3 and the n-type gallium oxide layer 4 are composed of monoclinic gallium oxide. Specifically, the substrate 2 is a sapphire substrate, the undoped gallium oxide layer 3 and the n-type gallium oxide layer 4 of step (a) are prepared by MOCVD, and the n-type gallium oxide layer 4 is prepared by introducing tetraethoxysilane (hereinafter referred to as TEOS) into a MOCVD reactor during the MOCVD process as a precursor of n-type doping. In the embodiment of the present invention, TEOS is used as an example for illustration, but it is not limited thereto. More preferably, the thickness of the undoped gallium oxide layer 3 is between 50 nm and 1000 nm; the thickness of the n-type gallium oxide layer 4 is between 30 nm and 200 nm.

Referring to FIG. 3 , the step (b) is to form a gate dielectric layer 5 on a region of the n-type gallium oxide layer 4 after the step (a).

Referring to FIG. 4 , step (c) is to form a gate electrode 6 on the gate dielectric layer 5 and the n-type gallium oxide layer 4 respectively after step (b), and a source electrode 7 and a drain electrode 8 spaced apart from each other are disposed on the n-type gallium oxide layer 4 .

Referring to FIG5 , the step (d) is to perform a self-aligned etching on the n-type gallium oxide layer 4 exposed outside the metal mask using the gate electrode 6, the source electrode 7 and the drain electrode 8 as a metal mask after the step (a), the self-aligned etching reduces the cross-section of the n-type gallium oxide layer 4 after the self-aligned etching. More preferably, referring to FIG6 , in the step (d), the self-aligned etching is also performed on the undoped gallium oxide layer 3, the cross-section of the undoped gallium oxide layer 3 after the self-aligned etching reduces the cross-section.

The present invention provides the following specific examples and their corresponding analytical data according to the preparation method of the embodiment. The detailed preparation method and analytical data are described as follows.

＜Specific example 1(E1)＞

In a specific example 1 (E1) of the method for manufacturing an enhancement mode field effect transistor of the present invention, step (a) is to place a sapphire substrate in the MOCVD reactor (not shown), and introduce trimethyl gallium (TMG) and nitrogen (N ₂ ) into the MOCVD reactor to grow a GaN buffer layer on the sapphire substrate, and then stop introducing N ₂ into the MOCVD reactor; then, introduce oxygen (O ₂ ) into the MOCVD reactor to continue to grow a non-doped Ga ₂ O ₃ layer with a thickness of about 60 nm on the GaN buffer layer; then, introduce 20 N 2 into the MOCVD reactor at a temperature of -10°C. sccm of TEOS allowed a Si-doped n-type Ga ₂ O ₃ layer of about 60 nm thickness to grow on the undoped Ga ₂ O ₃ layer at 800-900˚C, thereby completing step (a) of embodiment 1 (E1).

The step (b) of the embodiment 1 (E1) of the present invention is to form a gate dielectric layer on a region of the n-type Ga ₂ O ₃ layer.

Step (c) of the specific example 1 (E1) of the present invention is to first form a patterned photoresist layer on the n _- type _Ga2O3 layer and the gate dielectric layer by a lithography process, so that the opposite sides of a surface of the n _- type _Ga2O3 layer and the gate dielectric layer are partially exposed outside the patterned photoresist layer, and then deposit a metal layer on the patterned photoresist layer by a thin film process, and then peel off the patterned photoresist layer to leave a gate electrode on the _gate dielectric layer, and leave a source electrode and a drain electrode spaced apart from each other on opposite sides of the surface of the n-type _Ga2O3 layer.

Step (d) of the specific example 1 (E1) of the present invention is to place the sapphire substrate formed with the gate electrode, source electrode and drain electrode in a dry etching machine (not shown), and use the gate electrode, source electrode and drain electrode as a metal mask to perform a self-aligned etching on the n-type _Ga2O3 layer exposed outside the metal mask. In the specific example 1 (E1) _of the present invention, an etching depth of the self-aligned etching is 50 nm.

＜Specific example 2(E2)＞

A specific example 2 (E2) of the method for manufacturing an enhancement field effect transistor of the present invention is substantially the same as the specific example 1 (E1), except that in the specific example 2 (E2), when growing an n-type Ga ₂ O ₃ layer, the TEOS flow rate introduced into the MOCVD reactor is 40 sccm, and the growth is obtained under the condition of 800-900°C. In addition, in the specific example 2 (E2), an etching depth when performing a self-aligned etching is 70 nm.

＜Specific example 3(E3)＞

A specific example 3 (E3) of the method for manufacturing an enhancement field effect transistor of the present invention is substantially the same as the specific example 2 (E2), except that in the specific example 3 (E3), when growing an n-type Ga ₂ O ₃ layer, the TEOS flow rate introduced into the MOCVD reactor is 25 sccm. In addition, in the specific example 3 (E3), an etching depth when performing a self-aligned etching is 90 nm.

As shown in the Id-Vg curve of FIG. 7 , the Id trend of the enhancement field effect transistor of the specific example 1 (E1) of the present invention begins to increase linearly when Vg exceeds 2.5 V under the operating condition of Vd being 30 V. FIG. 7 illustrates that after the 60 nm n-type Ga ₂ O ₃ layer of the specific example 1 (E1) of the present invention is self-aligned and etched for 50 nm, the cross-sectional area of the n-type Ga ₂ O ₃ layer (channel) that has been self-aligned and etched is reduced, which can increase the impedance of the transistor and make the specific example 1 (E1) better controlled.

Further, from the Id-Vg curve shown in FIG8 , it can be seen that, under the operating condition of Vd being 30 V, when Vg is 0 V, the Id trend of the transistor increases linearly. This shows that the control capability of the enhancement field effect transistor of the embodiment 2 (E2) is better than that of the embodiment 1 (E1).

In addition, from the Id-Vg curve shown in FIG. 9 , it can be seen that when the Vg of the enhancement field effect transistor of the specific example 3 (E3) of the present invention is 4 V under the operating condition of Vd being 30 V, the trend of the Id of the transistor has increased linearly, and its controllability is also better than that of the specific example 1 (E1).

Referring to FIG. 10 , the enhancement field effect transistor of the specific example 1 (E1) of the present invention starts to show a stratified trend in Id when Vd is around 10 V under the operating conditions of Vg being 0 V, 3 V, 6 V, 9 V, 12 V and 15 V, and starts to approach saturation when Vd is around 30 V under the operating conditions of Vg being 12 V and 15 V, respectively.

Referring to FIG. 11 again, the transistor of the specific example 2 (E2) of the present invention has begun to show a stratified trend in Id when Vd is around 10 V under the operating conditions where Vg is 0 V, 3 V, 6 V, 9 V, 12 V and 15 V, and has begun to approach saturation when Vd is around 20 V and 25 V under the operating conditions where Vg is 12 V and 15 V, respectively. Its control capability is better than that of the specific example 1 (E1).

As can be seen from the above detailed description of the present invention, in the process of reducing the cross-sectional area of the channel (that is, the cross-sectional area of the undoped gallium oxide layer 3 and the n-type gallium oxide layer 4), the manufacturing method of the embodiment of the present invention directly utilizes the gate electrode 6, the source electrode 7 and the drain electrode 8 as metal masks when implementing the self-aligned etching, so that the enhancement field effect transistor can be directly manufactured after the self-aligned etching is completed. The manufacturing method of the embodiment of the present invention does not need to be combined with a lithography process before the gate contact 15, the source metal layer 17S and the drain metal layer 17D are completed, as in the case of the previous embodiment 1, plasma etching is performed to form the recessed gate region 150, so that after the plasma etching, the photoresist layer left in the lithography process needs to be further stripped before the subsequent process can be performed. Therefore, compared with the previous embodiment 1, the embodiment of the present invention can still produce an enhanced field effect transistor under the condition of simplifying the process.

In summary, the method for manufacturing the enhanced field effect transistor of the present invention simplifies the manufacturing process and the enhanced field effect transistor still retains the required control capability, so the purpose of the present invention can be achieved.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

2: Substrate 3: Undoped GaO layer 4: n-type GaO layer 5: Gate dielectric layer 6: Gate electrode 7: Source electrode 8: Drain electrode

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, in which: FIG. 1 is a schematic diagram illustrating the enhanced metal insulated semiconductor high electron mobility transistor disclosed in the early publication number TW202105740A invention patent of the Republic of China; FIG. 2 is a schematic diagram illustrating a step (a) of an implementation example of a method for manufacturing an enhanced field effect transistor of the present invention; FIG. 3 is a schematic diagram illustrating a step (b) of the method for manufacturing the embodiment of the present invention; FIG. 4 is a schematic diagram illustrating a step (c) of the method for manufacturing the embodiment of the present invention; FIG. 5 is a schematic diagram illustrating a self-aligned etching implemented in a step (d) of the method for manufacturing the embodiment of the present invention; FIG6 is a schematic diagram illustrating that the self-aligned etching of step (d) of the manufacturing method of the embodiment of the present invention is also performed on an undoped gallium oxide layer; FIG7 is an Id-Vg curve diagram illustrating the Id-Vg characteristics of a transistor manufactured by a specific example 1 (E1) of the manufacturing method of the enhanced field effect transistor of the present invention; FIG8 is an Id-Vg curve diagram illustrating the Id-Vg characteristics of a transistor manufactured by a specific example 2 (E2) of the manufacturing method of the enhanced field effect transistor of the present invention; FIG9 is an Id-Vg curve diagram illustrating the Id-Vg characteristics of a transistor manufactured by a specific example 3 (E3) of the manufacturing method of the enhanced field effect transistor of the present invention; FIG. 10 is an Id-Vd curve diagram illustrating the Id-Vd characteristics of a transistor produced by the method of the specific example 1 (E1) of the present invention; and FIG. 11 is an Id-Vd curve diagram illustrating the Id-Vd characteristics of a transistor produced by the method of the specific example 2 (E2) of the present invention.

2: Substrate

3: Undoped gallium oxide layer

4: n-type gallium oxide layer

5: Gate dielectric layer

6: Gate electrode

7: Source electrode

8: Drain electrode

Claims (3)

A method for manufacturing an enhancement field effect transistor comprises the following steps: Step (a), sequentially forming an undoped gallium oxide layer and an n-type gallium oxide layer on a substrate; Step (b), forming a gate dielectric layer on a region of the n-type gallium oxide layer; Step (c), forming a gate electrode and a source electrode and a drain electrode spaced apart from each other on the gate dielectric layer and the n-type gallium oxide layer, respectively; and Step (d), after step (a), step (b) and step (c), the gate electrode, source electrode and drain electrode are used as a metal mask to perform a self-aligned etching on the n-type gallium oxide layer exposed outside the metal mask, so that a cross-section of the n-type gallium oxide layer after the self-aligned etching is reduced. The method for manufacturing an enhancement field effect transistor as described in claim 1, wherein in the step (d), the undoped gallium oxide layer is further subjected to the self-aligned etching so that a cross-sectional area of the undoped gallium oxide layer subjected to the self-aligned etching is reduced. The method for manufacturing an enhancement mode field effect transistor as described in claim 1, wherein in the step (a), the undoped gallium oxide layer and the n-type gallium oxide layer are composed of monoclinic gallium oxide.