CN113140630B - Preparation method of p-type nitride gate of enhancement mode HEMT and method of using same to prepare enhancement mode nitride HEMT - Google Patents

Abstract

The invention discloses a p-type nitride gate of an enhanced HEMT and a preparation method of the enhanced nitride HEMT, wherein when the p-type nitride gate is prepared, a first protection layer is prepared between a barrier layer and a p-type nitride layer by adopting a material with a thermal desorption temperature higher than that of the p-type nitride layer, the thickness range of the first protection layer is set to be 1nm-5nm, and then the p-type nitride layer outside a grid region is removed by high-temperature thermal desorption; and a second protective layer prepared by adopting a high-temperature resistant dielectric material is further arranged on the p-type nitride layer of the gate region before the p-type nitride layer outside the gate region is subjected to high-temperature desorption. Under the protection effect of the first protection layer and the second protection layer, the p-type nitride layer outside the grid region can be selectively etched through high-temperature thermal desorption, so that the repeatable and better-consistency etching effect can be realized, and the reliability of the performance of the enhanced nitride HEMT can be ensured.

Description

Preparation method of p-type nitride gate of enhancement mode HEMT and its application to prepare enhancement mode Nitride HEMT approach

Technical field

The present invention relates to the technical field of enhancement-mode high electron mobility transistors, and specifically relates to a method for preparing a p-type nitride gate of an enhancement-mode HEMT, and applying the method for preparing a p-type nitride gate to the preparation of an enhancement-mode nitride HEMT. in order to prepare a highly reliable enhancement-mode nitride HEMT.

Background technique

The third-generation semiconductor material has a wider band gap and has a higher breakdown voltage when used in power switches than traditional Si-based power switches. When these third-generation semiconductor materials with wider bandgaps are used in high electron mobility transistors (HEMTs for short), the inherent polarization characteristics (spontaneous polarization and Piezoelectric polarization), producing a two-dimensional electron gas (2DEG) with high concentration and high electron mobility, which makes the HEMT have a higher breakdown voltage and smaller on-state resistance, which can Create smaller HEMTs. However, due to the strong polarization effect at the heterojunction of HEMT devices, 2DEG is difficult to be depleted under normal conditions. Therefore, HEMT devices are usually depletion mode (normally open) devices and need to be matched with a device that provides negative voltage. A gate drive circuit is required to turn off the HEMT, which greatly increases the complexity of the circuit and reduces the practicality of the HEMT.

To this end, a commonly used solution is to deplete the 2DEG under the gate by setting a p-type nitride gate where the gate is located, thereby obtaining an enhancement mode (also known as normal) that is in the off state under zero gate bias. OFF type) HEMT. Currently, the most common way to set a p-type nitride gate at the location of the gate is to use etching. However, when etching is used to prepare a p-type nitride gate, dry etching of the p-type nitride gate is generally used. For large areas of p-type nitride outside the area, it is very difficult to control the uniformity of this type of etching process. Under-etching is prone to occur due to insufficient etching depth of the p-type nitride gate, or due to the etching depth exceeding the p-type nitride gate. Over-etching caused by damage to the barrier layer when the thickness of the compound gate is increased, whether it is under-etching or over-etching, will reduce the on-current of the enhancement-mode HEMT and significantly affect its operating performance.

Contents of the invention

In order to solve the problem of gate leakage, current collapse and threshold voltage instability in the enhancement HEMT due to under-etching or over-etching when the p-type nitride gate of the enhancement HEMT is prepared using the existing etching process, the invention was invented After a lot of research and experiments, people found that the p-type nitride layer can be selectively removed using a high-temperature thermal desorption process, and when using a high-temperature thermal desorption process to remove the p-type nitride layer, the etching selectivity can be effectively controlled to It is ensured that the underlying barrier layer will not be damaged when the p-type nitride outside the p-type nitride gate region is completely removed.

To this end, according to one aspect of the present invention, a method for preparing a p-type nitride gate of an enhancement mode HEMT is provided. When preparing the p-type nitride gate, the preparation method of the p-type nitride gate is through high-temperature thermal dehydration. The p-type nitride layer outside the gate region is additionally removed, and the preparation method of the p-type nitride gate also includes preparing a first protective layer between the barrier layer and the p-type nitride layer during the preparation process of the epitaxial structure. , wherein the thickness range of the first protective layer is set to 1nm-5nm, and a material with a thermal desorption temperature higher than that of the p-type nitride layer is used; the p-type nitride layer outside the gate region is processed Before high-temperature thermal desorption, a second protective layer is also prepared on the p-type nitride layer in the gate region, where the second protective layer uses a high-temperature resistant dielectric material.

In the embodiment of the present invention, a high-temperature thermal desorption process is applied to remove the p-type nitride layer outside the gate region, combined with special designs of the first protective layer and the second protective layer, for example, the first protective layer and the second protective layer are specially designed. The selection of the structure and performance of the second protective layer, the selection of the placement positions of the first protective layer and the second protective layer, etc., enable the p-type nitride gate to be prepared in the first protective layer when the preparation method of the embodiment of the present invention is used. Under the protection of the second protective layer and the second protective layer, the p-type nitride layer outside the gate area is selectively etched through high-temperature thermal desorption, and the p-type nitride layer outside the gate area can be completely removed. Without causing damage to the barrier layer and p-type nitride layer under the p-type nitride layer, repeatable and consistent etching effects can be achieved, thereby ensuring the reliability of the enhanced nitride HEMT performance. In addition, in the embodiment of the present invention, it is preferable to control the thickness of the first protective layer to less than 5 nm, which not only facilitates the preparation of the first protective layer, but also avoids cracking or causing cracking due to stress mutation due to excessive thickness of the first protective layer. There are defects such as cracking of the heterojunction below it; and, because the thickness of the first protective layer is thin, it is easy to remove it through other etching methods after high-temperature thermal desorption, so as to prepare the source electrode and the drain electrode on the barrier layer.

In some embodiments, the p-type nitride layer is a p-GaN layer; the temperature range of high-temperature thermal desorption is 500°C-1000°C. For example, high-temperature thermal desorption is performed in high-temperature processing equipment such as Metal-organic Chemical Vapor Deposition (MOCVD) equipment, tubular annealing furnaces, or high-temperature annealing furnaces.

Since the thermal desorption temperature of the p-GaN layer is 850°C-1000°C, the portion of the p-GaN layer that is not covered by the second protective layer (that is, the portion other than the gate region of the p-GaN layer), is at a temperature of It can be completely removed by being placed in a high temperature environment of 500℃-1000℃ for a period of time; and because the first protective layer uses a material with a higher thermal desorption temperature than the p-GaN layer, the second protective layer High-temperature resistant dielectric materials are used, so high-temperature thermal desorption at a temperature of 500°C-1000°C can prevent the second protective layer and the first protective layer from being removed, thereby protecting the p-GaN layer and potential in the gate area. The barrier layer is not destroyed during high temperature thermal desorption. In a preferred embodiment, Ga source (eg, Ga atomic flow) and N source (eg, N atomic flow) are not introduced during the high-temperature thermal desorption process to improve the desorption efficiency of the p-GaN layer outside the gate region.

In some embodiments, the first protective layer is an AlN layer or an AlGaN layer, and the Al composition of the AlGaN layer is between 0.5 and 1. That is, when the first protective layer is an AlGaN layer, the first protective layer has a high Al composition. AlGaN layer.

Since the thermal desorption temperatures of AlN and AlGaN with high Al composition are both higher than that of GaN, AlN or AlGaN with high Al composition is set as the first protective layer between the p-type nitride and the barrier layer. When removing the p-type GaN layer outside the gate area through high-temperature thermal desorption, the end point of the etching can be controlled at the first protective layer. Not only can a more consistent etching effect be obtained, but also the first protection layer can be avoided. The barrier layer underneath the layer is damaged when removing the p-type GaN layer outside the gate area.

In some embodiments, the second protective layer is a high temperature resistant dielectric layer such as Si ₃ N ₄ layer, SiO ₂ layer, AlN layer or HfO ₂ layer, and its thickness ranges from 50 nm to 200 nm. This ensures that the second protective layer can be removed by dry etching or wet etching, and at the same time, it can be ensured that the second protective layer will not be removed during high-temperature thermal desorption at a temperature of 500°C to 1000°C. Generally, the Si ₃ N ₄ layer can be prepared by CVD technology, and the SiO ₂ layer, AlN layer or HfO ₂ layer can be prepared by magnetron sputtering equipment. Moreover, since the thickness of the second protective layer is 50nm-200nm, it can not only protect the p-type nitride layer from being damaged during the high-temperature thermal desorption process, but also the second protection layer can be removed quickly after the high-temperature thermal desorption is completed. layer.

In some embodiments, before performing high-temperature thermal desorption of the p-type nitride layer outside the gate region, it also includes etching the p-type nitride layer outside the gate region until the p-type nitride layer outside the gate region is The residual thickness of the nitride layer is less than 30 nm.

Since the thickness of the p-type nitride gate is generally about 100nm, if the p-type nitride layer with a thickness of 100nm outside the gate area needs to be removed through high-temperature thermal desorption, the removal time will be long. In the embodiment of the present invention, Before performing high-temperature thermal desorption, controlling the thickness of the p-type nitride layer outside the gate area to less than 30nm can greatly reduce the time of high-temperature thermal desorption. It can also avoid damage to other layers due to long-term exposure to high-temperature environments. Such as the first protective layer and barrier layer, etc.) causing damage.

In some embodiments, preparing the second protective layer on the p-type nitride layer in the gate region includes: after etching the p-type nitride layer outside the gate region to a residual thickness of less than 30 nm, A second protective layer is prepared on the nitride layer; a mask layer is covered on the second protective layer in the gate region; and the second protective layer outside the gate region is removed by etching.

In this embodiment, the growth of the second protective layer on the p-type nitride layer gate is achieved by LPCVD technology. The removal of the second protective layer outside the gate region by etching is specifically implemented by using wet etching or dry etching to remove the second protective layer outside the gate region.

In other embodiments, preparing the second protective layer on the p-type nitride layer in the gate region includes: after preparing the p-type nitride layer, directly preparing the second protective layer on the p-type nitride layer; Before etching the p-type nitride layer, a gate region mask range is defined, and the second protective layer outside the defined gate region is removed by etching.

In this embodiment, for example, the second protective layer can be deposited on the p-type nitride layer through MOCVD technology, molecular beam epitaxy (MBE) technology, magnetron sputtering technology or low pressure chemical vapor phase. Deposition (Low Pressure Chemical Vapor Deposition, referred to as LPCVD) technology is realized. Preferably, MOCVD technology or MBE technology is used to prepare the second protective layer. Therefore, when the epitaxial growth of the p-type nitride layer is completed, the second protective layer can be directly epitaxially grown without changing equipment. Moreover, when a second protective layer is prepared on the p-type nitride layer and then etched outside the gate area to obtain a p-type nitride layer with a residual thickness of less than 30 nm, the second protective layer can act as a mask to protect the gate. The p-type nitride layer in the area is not removed, thereby reducing the number of mask settings, reducing the preparation process, and improving the preparation efficiency. In this embodiment, for example, the mask range of the gate region is defined by photolithography exposure; dry etching is used to remove the second protective layer outside the gate region. In this embodiment, the thickness of the p-type nitride layer outside the gate region is relatively thick when it is not etched, and the p-type nitride layer outside the gate region needs to be completely removed eventually. Therefore, even if When the second protective layer outside the gate region is removed by dry etching with a high etching rate, damage to the p-type nitride layer outside the gate region will not affect the performance of the final enhancement mode HEMT. Therefore, in this embodiment, by using dry etching to remove the second protective layer outside the gate region, the performance of the p-type nitride gate of the enhanced HEMT can be guaranteed. to improve preparation efficiency.

In some embodiments, low-power dry etching is used to etch the p-type nitride layer outside the gate region until the residual thickness of the p-type nitride layer outside the gate region is less than 30 nm. Since the etching rate of low-power dry etching is low, it is easy to control the thickness of the remaining p-type nitride after etching.

In some embodiments, the p-type nitride layer outside the gate region is etched until the residual thickness of the p-type nitride layer outside the gate region is less than 30 nm. Plasma oxidation combined with wet etching is used, and wet etching is used. The acid used for etching is dilute hydrochloric acid. Among them, in the embodiment of the present invention, the second protective layer is preferably made of a material resistant to corrosion by dilute hydrochloric acid.

For example, plasma oxidation combined with wet etching can be implemented as follows: first, use an oxygen-containing atmosphere to generate plasma, oxidize the surface of the p-type nitride layer, then use dilute hydrochloric acid to remove the oxide layer, and repeat plasma oxidation and wet etching. The etching process is carried out until the thickness of the p-type nitride layer to be etched is etched below 30 nm. Since plasma oxidation combined with wet etching is used to etch the p-type nitride layer, it needs to be repeated many times to complete. Therefore, the residual p after etching can be better controlled by controlling the number of plasma oxidation and wet etching. type nitride thickness.

According to one aspect of the present invention, a preparation method of enhanced nitride HEMT is provided, which includes the following steps:

Step S101: Prepare a p-type nitride gate of the enhancement-mode HEMT using the aforementioned preparation method of a p-type nitride gate of the enhancement-mode HEMT;

Step S102: Remove the second protective layer and remove the first protective layer in the source electrode region and the drain electrode region;

Step S103: Prepare a source electrode and a drain electrode on the barrier layer of the source electrode region and the drain electrode region respectively, and prepare a gate electrode on the p-type nitride gate.

Due to the selective etching of the p-type nitride layer by high-temperature thermal desorption, after the p-type nitride layer outside the gate area is removed, the damage to the surface of the barrier layer is small, resulting in a lower boundary state density on the surface of the barrier layer. Therefore, the source electrode and the drain electrode grown on the barrier layer are more likely to form ohmic contact. Moreover, since the second protective layer can prevent the p-type nitride gate from being desorbed during thermal desorption at high temperatures and prevent the surface of the p-type nitride gate from being damaged due to high temperature, the gate electrode grown on the p-type nitride gate is more likely to form ohmic contact or Schottky contact. Therefore, the enhanced HEMT prepared by the embodiment of the present invention has better stability.

In some embodiments, both the source electrode and the drain electrode can be made of at least two combinations of Ti, Al, Ni, Au, Cr, P, Pt and TiN. The selected material is grown on the barrier layer and then Annealing forms ohmic contact.

In some embodiments, the annealing process to form the ohmic contact is: placing in an air or nitrogen environment of 0°C-1000°C for 10s-1h.

In some embodiments, the gate electrode can be made of at least two combinations of Ti, Al, Ni, Au, Pd, Pt, TiN, and W. The selected material is grown on the p-type nitride gate to form Schott. base contact or ohmic contact.

In some embodiments, the Schottky contact of the gate electrode formed on the p-type nitride gate can be improved by annealing. For example, the annealing process to improve Schottky contact is: placing in an air or nitrogen environment of 0°C-500°C for 10s-1h.

In some embodiments, in step S102, the second protective layer is removed by BOE. Selective etching of the second protective layer through BOE can avoid damage to the surface of the p-type nitride gate when removing the second protective layer.

In some embodiments, in step S102, a mask etching process is used to remove the first protective layer in the source electrode region and the drain electrode region. Before growing the source electrode and the drain electrode on the barrier layer, the first protective layer in the source electrode and drain electrode regions is removed through a mask etching process, so that the source electrode and the drain electrode grown on the barrier layer can more easily form ohmic contact. Since the thickness of the first protective layer is controlled in the range of 1 nm to 5 nm when preparing the p-type nitride gate in the embodiment of the present invention, the first protective layer not only protects the barrier layer from damage, but also does not cause damage to the barrier layer. The performance of the prepared enhanced HEMT is affected. Therefore, in the process of preparing the enhanced HEMT, only the first protective layer in the source electrode and drain electrode regions needs to be removed. There is no need to remove the entire first protective layer. Not only can It further effectively protects the surface interface state density of the barrier layer, and does not increase the complexity of the preparation process of the enhanced HEMT. It can prepare a higher-stability enhanced HEMT with a simpler process.

In some embodiments, after step S103, step S104 is also included: depositing an insulating dielectric layer on the surface of the source electrode, drain electrode, gate electrode, p-type nitride gate and second protective layer, and using photolithography and etching processes to The positions of the insulating dielectric layer corresponding to the source electrode, drain electrode and gate electrode are removed until the source electrode, drain electrode and gate electrode are exposed.

The insulating dielectric layer deposited on the surface of the enhancement nitride HEMT can reduce the impact of external environments, such as radiation, on 2DEG and P-type nitride gates, ensuring the stability and reliability of the enhancement nitride HEMT operation.

In some embodiments, the insulating dielectric layer is a SiO ₂ layer, a SiN _x layer, a HfO ₂ layer, or a polyimide layer.

Description of the drawings

Figure 1 is a schematic flow chart of a p-type nitride gate preparation method for an enhancement mode HEMT according to the first embodiment of the present invention;

Figure 2 is a schematic flow chart of a p-type nitride gate preparation method for an enhancement mode HEMT according to the second embodiment of the present invention;

Figure 3 is a schematic flow chart of a p-type nitride gate preparation method for an enhancement mode HEMT according to the third embodiment of the present invention;

Figure 4 is a schematic diagram of the preparation method of the p-type nitride gate of the enhancement mode HEMT corresponding to each process step in Figure 2, shown in the form of a schematic structural diagram of an intermediate product according to one embodiment;

Figure 5 is a schematic diagram of the preparation method of the p-type nitride gate of the enhancement mode HEMT corresponding to each process step in Figure 2, shown in the form of a schematic structural diagram of an intermediate product according to another embodiment;

Figure 6 is a schematic flowchart of a specific implementation method of an embodiment of step S0;

Figure 7 is a schematic diagram of the preparation method of the p-type nitride gate of the enhancement mode HEMT corresponding to each process step in Figure 3, shown in the form of a schematic structural diagram of an intermediate product according to one embodiment;

Figure 8 is a schematic diagram of the preparation method of the p-type nitride gate of the enhancement mode HEMT corresponding to each process step in Figure 3, shown in the form of a schematic structural diagram of an intermediate product according to another embodiment;

Figure 9 is a schematic flow chart of a preparation method of an enhancement-mode nitride HEMT according to an embodiment of the present invention;

Figure 10 shows the p-type nitride gate of the enhancement-mode HEMT produced in Figure 7 or 8 as a blank, and shows the p-type nitride of the enhancement-mode HEMT corresponding to each process step in Figure 9 in the form of a schematic structural diagram of the intermediate product. Schematic diagram of how the gate is prepared;

Figure 11 is a schematic flow chart of a preparation method of an enhancement nitride HEMT according to another embodiment of the present invention;

Figure 12 shows the p-type nitride gate of the enhancement-mode HEMT produced in Figure 7 or Figure 8 as a blank. The p-type nitride of the enhancement-mode HEMT corresponding to each process step in Figure 11 is shown in the form of a schematic structural diagram of the intermediate product. Schematic diagram of how the gate is prepared;

31. Substrate; 32. Buffer layer; 33. Channel layer; 331. Insertion layer; 34. Barrier layer; 35. First protective layer; 36. P-type nitride layer; 37. Second protective layer; 38 , mask; 391, gate electrode; 392, source electrode; 393, drain electrode; 394, insulating dielectric layer.

Detailed ways

It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other.

It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or sequence between them. Furthermore, the terms "comprises" and "comprising" include not only those elements but also other elements not expressly listed or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element. The terms used in this article are generally terms commonly used by those skilled in the art. If there is any inconsistency with the commonly used terms, the terms in this article shall prevail.

In this article, the term "epitaxial structure" includes a single crystal substrate, as well as single crystal layers with the same crystallographic orientation as the substrate that are sequentially grown on the substrate using other materials.

In this article, the term "thermal desorption" refers to the separation of the surface layer of the epitaxial structure whose thermal desorption temperature is lower than the thermal desorption treatment temperature from the sub-surface layer of the epitaxial structure through direct or indirect heat exchange, and The process of removing the surface layer. Among them, the surface layer and subsurface layer of the epitaxial structure are used to represent the dimensions of the epitaxial structure in its growth direction, and the subsurface layer is a layer adjacent to the surface layer formed by growing using a material different from the surface layer.

In this article, the term "thermal desorption temperature" refers to the temperature at which the surface layer is separated from the subsurface layer during the thermal desorption treatment. This temperature is the thermal desorption temperature of the surface layer material.

In this article, the term "high temperature thermal desorption" refers to a thermal desorption treatment process with a thermal desorption temperature above 500°C.

As used herein, the term "dielectric material" refers to a material that is different from that of the substances in contact.

In this article, the term "high temperature resistant dielectric material" refers to a dielectric material whose thermal decomposition temperature is above 1000°C.

In this article, the term "thermal decomposition temperature" refers to the temperature at which decomposition of a compound begins to occur during a temperature increase.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

According to one aspect of the present invention, a method for preparing a p-type nitride gate of an enhancement mode HEMT is provided. The embodiment of the present invention includes an "epitaxial structure" including a substrate, a buffer layer and a channel epitaxially grown on the substrate. Taking the layer, barrier layer and p-type nitride layer as examples, the preparation method of the p-type nitride gate of the enhancement mode HEMT is described in detail.

Among them, in the embodiment of the present invention, when preparing the p-type nitride gate, the p-type nitride layer outside the gate region is removed through high-temperature thermal desorption, and the preparation method of the p-type nitride gate also includes During the preparation process of the epitaxial structure, a first protective layer with a thickness in the range of 1 nm to 5 nm and a thermal desorption temperature higher than that of the p-type nitride layer is prepared between the barrier layer and the p-type nitride layer. , in order to improve the preparation efficiency of the first protective layer while providing protection for the barrier layer, and to prevent the excessively thick first protective layer from cracking due to sudden stress changes or causing the heterojunction below it to crack; Before the p-type nitride layer outside the electrode region is subjected to high-temperature thermal desorption, a second protective layer is also prepared on the p-type nitride layer in the gate region, where the second protective layer is made of a high-temperature resistant dielectric material. As a result, the p-type nitride layer outside the gate region can be selectively etched through high-temperature thermal desorption; and after the p-type nitride layer outside the gate region is removed, the p-type nitride layer outside the gate region can be removed quickly. A first protective layer to prepare source and drain electrodes on the barrier layer.

Figure 1 schematically shows a flow chart of a first embodiment of a method for preparing a p-type nitride gate for an enhanced HEMT. Referring to Figure 1, the method for preparing a p-type nitride gate for an enhanced HEMT specifically includes the following. step:

Step S1: first deposit a first protective layer on the barrier layer, and then deposit a p-type nitride layer on the first protective layer;

Step S2: Set a second protective layer on the p-type nitride layer in the gate region;

Step S3: Selectively etch the p-type nitride layer outside the gate region through high-temperature thermal desorption to form a p-type nitride gate on the p-type nitride layer in the gate region.

Wherein, the barrier layer in step S1 may be formed by sequentially epitaxially growing a buffer layer, a channel layer and a barrier layer on the substrate. As one embodiment of the p-type nitride layer, the p-type nitride layer is a p-GaN layer.

In step S3, the thermal desorption temperature range of high-temperature thermal desorption is preferably 500°C-1000°C, so that the second protective layer and the first protective layer will not be removed when the p-GaN layer outside the gate region is removed by high-temperature thermal desorption. The protective layer. In a preferred embodiment, Ga source (eg, Ga atomic flow) and N source (eg, N atomic flow) are not introduced during the high-temperature thermal desorption process to improve the desorption efficiency of the p-GaN layer outside the gate region. For example, high-temperature thermal desorption is performed in high-temperature processing equipment such as MOCVD equipment, tubular annealing furnaces, or high-temperature annealing furnaces.

For example, the material used for the first protective layer is AlN or AlGaN with an Al component between 0.5-1. Therefore, the deposited first protective layer can be an AlN layer or an AlGaN layer with an Al component between 0.5-1. AlGaN layer. In step S3, when removing the p-type GaN layer outside the gate region through high-temperature thermal desorption, the end point of etching can be controlled at the first protective layer.

For example, the high temperature resistant dielectric material selected for the second protective layer is Si ₃ N ₄ or SiO ₂ or AlN or HfO _2. Therefore, the second protective layer provided can be a Si ₃ N ₄ layer, a SiO ₂ layer, The thickness of high temperature resistant dielectric layers such as AlN layer or HfO ₂ layer ranges from 50nm to 200nm. This ensures that the second protective layer can be removed by dry etching or wet etching, and at the same time, it can be ensured that the second protective layer will not be removed during high-temperature thermal desorption at a temperature of 500°C to 1000°C. For example, depositing the second protective layer on the p-type nitride layer can be achieved by MOCVD technology, MBE technology, magnetron sputtering technology or LPCVD technology. Generally, the Si ₃ N ₄ layer can be prepared by CVD technology, and the SiO ₂ layer, AlN layer or HfO ₂ layer can be prepared by magnetron sputtering equipment. Moreover, since the thickness of the second protective layer is 50nm-200nm, it can not only protect the p-type nitride layer from being damaged during the high-temperature thermal desorption process, but also can quickly remove the second protective layer after the high-temperature thermal desorption is completed. Second protective layer.

Preferably, MOCVD technology or MBE technology is used to prepare the second protective layer. Therefore, when the epitaxial growth of the p-type nitride layer is completed, the second protective layer can be directly epitaxially grown without changing equipment. In this case, step S2 of the embodiment of the present invention can be specifically implemented by: first preparing a second protective layer on the p-type nitride layer; then defining the gate region mask range; and then etching Remove the second protective layer outside the defined gate area. In step S3, when the p-type nitride layer outside the gate region is selectively etched through high-temperature thermal desorption, and when the p-type nitride layer outside the gate region is etched, a p-type nitride layer with a residual thickness less than 30 nm is obtained. (In the preferred embodiment, the p-type nitride layer will also be etched before step S3, and this preferred implementation will be described in more detail below), the second protective layer can act as a mask, The p-type nitride layer in the gate region is protected from being removed, thereby reducing the number of mask settings, reducing the preparation process, and improving the preparation efficiency. In this embodiment, for example, the mask range of the gate region is defined by photolithography exposure; dry etching is used to remove the second protective layer outside the gate region. Since in this embodiment, the second protective layer is directly prepared on the p-type nitride layer, that is, when the epitaxial growth of the p-type nitride layer is completed, the second protective layer is directly epitaxially grown. The nitride layer is not etched and its thickness is relatively thick. Even when the second protective layer outside the gate area is removed by dry etching with a high etching rate, it will cause damage to the p-type nitride layer outside the gate area. Damage, since the p-type nitride layer outside the gate area needs to be completely removed eventually, it will not affect the performance of the p-type nitride gate of the final enhancement mode HEMT. Therefore, this embodiment uses dry etching. Etching away the second protective layer outside the gate region can improve the preparation efficiency while ensuring the performance of the p-type nitride gate of the enhanced HEMT.

In a preferred embodiment, before performing high-temperature thermal desorption of the p-type nitride layer outside the gate region, it further includes etching the p-type nitride layer outside the gate region until the p-type nitride layer outside the gate region is The residual thickness of the nitride layer is less than 30 nm. This can greatly reduce the time of high-temperature thermal desorption, thereby avoiding damage to the barrier layer caused by high-temperature thermal desorption.

In some embodiments, low-power dry etching is used to etch the p-type nitride layer outside the gate region until the residual thickness of the p-type nitride layer outside the gate region is less than 30 nm. Since the etching rate of low-power dry etching is low, it is easy to control the thickness of the remaining p-type nitride after etching.

In other implementation examples, the p-type nitride layer outside the gate area is etched until the residual thickness of the p-type nitride layer outside the gate area is less than 30 nm. Plasma oxidation combined with wet etching is used, and wet etching is used. The acid used for etching is dilute hydrochloric acid. In this case, the second protective layer is preferably made of a material resistant to dilute hydrochloric acid corrosion, such as Si ₃ N ₄ .

For example, plasma oxidation combined with wet etching can be implemented as follows: first, use an oxygen-containing atmosphere to generate plasma, oxidize the surface of the p-type nitride layer, then use dilute hydrochloric acid to remove the oxide layer, and repeat plasma oxidation and wet etching. The etching process is carried out until the thickness of the p-type nitride layer to be etched is etched below 30 nm. Since plasma oxidation combined with wet etching is used to etch the p-type nitride layer, it needs to be repeated many times to complete. Therefore, the remaining p-type nitride after etching can be controlled by controlling the number of plasma oxidation and wet etching. thickness of.

Among them, the p-type nitride layer outside the gate area is etched until the residual thickness of the p-type nitride layer outside the gate area is less than 30 nm. This process can be performed before step S2 shown in Figure 1 It may also be performed after step S2 shown in FIG. 1 , and this is not limited in the embodiment of the present invention.

Taking step S2 shown in Figure 1 as an example, Figure 2 schematically shows a method for preparing a p-type nitride gate of an enhancement mode HEMT according to another embodiment of the present invention. As shown in Figure 2, in the present invention In an embodiment, the method includes:

Step S1: first deposit a first protective layer on the barrier layer, and then deposit a p-type nitride layer on the first protective layer;

Step S2: Set a second protective layer on the p-type nitride layer in the gate region;

Step S0: Etch the p-type nitride layer outside the gate area until the residual thickness of the p-type nitride layer outside the gate area is less than 30 nm;

Step S3: Selectively etch the p-type nitride layer outside the gate region through high-temperature thermal desorption to form a p-type nitride gate on the p-type nitride layer in the gate region.

In the embodiment of the present invention, the specific implementation of steps S1 and step S3 can be implemented with reference to the relevant description of the embodiment shown in Figure 1, and in step S2, a second protective layer is prepared on the p-type nitride layer in the gate region It can be implemented by: after preparing the p-type nitride layer, directly preparing a second protective layer on the p-type nitride layer; and before etching the p-type nitride layer, defining the gate region mask range, The second protective layer outside the defined gate area is removed by an etching process.

In this embodiment, since the second protective layer can be obtained by epitaxial growth after epitaxial growth of the p-type nitride layer, it is preferred to use common epitaxial growth technologies such as MOCVD or MBE to prepare the second protective layer, thereby avoiding After completing the epitaxial growth of the p-type nitride layer, the preparation equipment is replaced to improve preparation efficiency.

For example, in step S2, the mask range of the gate region may be defined through photolithography exposure, and dry etching may be used to remove the second protective layer outside the gate region.

For example, in step S0, etching the p-type nitride layer outside the gate region may be performed under low-power dry etching or plasma oxidation combined with wet etching conditions. In this embodiment, since the second protective layer also needs to act as a mask for the p-type nitride layer in the gate region during the high-temperature thermal desorption process, in order to prevent the second protective layer from being used during the etching process in step S0 Damage, resulting in weakening of its ability to protect the p-type nitride layer in the gate region during the high-temperature thermal desorption process. Preferably, in step S0, a lower etching rate is used and does not damage the second protective layer. Damaging low-power dry etching removes the p-type nitride layer outside the gate area.

Taking the example of etching the p-type nitride layer outside the gate region until the residual thickness of the p-type nitride layer outside the gate region is less than 30 nm before step S2 shown in Figure 1, Figure 3 schematically illustrates A method for preparing a p-type nitride gate of an enhancement mode HEMT according to another embodiment of the present invention is shown, as shown in Figure 3. In this embodiment of the present invention, the method includes:

Step S1: first deposit a first protective layer on the barrier layer, and then deposit a p-type nitride layer on the first protective layer;

Step S0: Etch the p-type nitride layer outside the gate area until the residual thickness of the p-type nitride layer outside the gate area is less than 30 nm;

Step S2: Set a second protective layer on the p-type nitride layer in the gate region;

Step S3: Selectively etch the p-type nitride layer outside the gate region through high-temperature thermal desorption to form a p-type nitride gate on the p-type nitride layer in the gate region.

Under the embodiment of the present invention, step S2 is implemented by: after etching the p-type nitride layer outside the gate area to a residual thickness of less than 30 nm, preparing a second protective layer on the p-type nitride layer; Covering the second protective layer in the region with a mask layer; and removing the second protective layer outside the gate region through etching. For example, growing the second protective layer on the p-type nitride layer gate is achieved by LPCVD technology. Among them, wet etching or dry etching is used to remove the second protective layer outside the gate region.

For example, with reference to FIG. 6 , in this embodiment, the specific operation steps of step S0 can be implemented to include the following steps:

Step S21': Define the gate area mask range through photolithography exposure;

Step S22': Etch the p-type nitride layer outside the gate region through the second etching until the p-type nitride layer with a thickness less than 30 nm remains outside the gate region.

For example, in step S22', the second etching may also be performed under low-power dry etching or plasma oxidation combined with wet etching conditions. In this embodiment, since the p-type nitride layer is not covered with the second protective layer, when performing the second etching, there is no need to worry that the etching process of the second etching will cause damage to the second protective layer. Therefore, the second protective layer For the second etching, low-power dry etching or plasma oxidation combined with wet etching can be used. Specifically, plasma oxidation combined with wet etching can be achieved as follows: first, use an oxygen-containing atmosphere to generate plasma to oxidize the surface of the p-type nitride layer outside the gate area, then use dilute hydrochloric acid to remove the oxide layer, and repeat Plasma oxidation and wet etching processes are performed until the thickness of the p-type nitride layer to be etched is etched below 30nm.

As a preferred implementation example, the p-type nitride layer in the above embodiment of the present invention may be a p-GaN layer. The second protective layer is a Si ₃ N ₄ layer. The method of growing the second protective layer on the p-type nitride layer can adopt MOCVD technology, MBE technology, magnetron sputtering technology or LPCVD technology.

Therefore, under the protection of the first protective layer and the second protective layer, the p-type nitride layer outside the gate region is selectively etched through high-temperature thermal desorption, and the p-type nitride layer outside the gate region can be completely removed. In the case of the p-type nitride layer, it does not cause damage to the p-type nitride layer and the barrier layer below it, so that repeatable and consistent etching effects can be achieved, and the reliability of the enhanced nitride HEMT performance can be ensured. sex.

As a preferred embodiment, an insertion layer is also provided between the channel layer and the barrier layer. The insertion layer is an AlN layer with a thickness of 1 nm to 5 nm. Thereby, the concentration of 2DEG can be increased.

The preparation method of the p-type nitride gate of the enhancement mode HEMT in the embodiment shown in FIG. 2 will be exemplified below with reference to specific examples.

Example 1

The preparation method steps of this embodiment and the structure of the intermediate product corresponding to each step are shown in Figure 4:

In the first step, MOCVD technology is used to sequentially epitaxially grow the buffer layer 32, the channel layer 33, the barrier layer 34, the first protective layer 35 and the p-type nitride layer 36 on the substrate 31, as shown in (a) of Figure 4 As shown; where the substrate is a sapphire substrate, the buffer layer is an AlGaN/GaN buffer layer, the channel layer is a GaN layer and its thickness is 50nm, the first protective layer is an AlN layer and its thickness is 1nm, and the barrier layer is AlGaN layer, the p-type nitride layer is a p-GaN layer; a heterojunction with 2DEG is formed between the channel layer and the barrier layer;

In the second step, MOCVD technology is used to continue to epitaxially grow the second protective layer 37 on the p-type nitride layer, as shown in (b) of Figure 4, where the second protective layer is a Si ₃ N ₄ layer and its thickness is 200nm;

The third step is to define the range of the gate area mask 38 through photolithography exposure, as shown in (c) of Figure 4;

The fourth step is to use dry etching to remove the second protective layer outside the gate area until the p-type nitride layer outside the gate area is exposed, as shown in (d) of Figure 4;

The fifth step is to remove the mask above the second protective layer, as shown in (e) of Figure 4;

The sixth step is to use a low-power dry etching process to etch the p-type nitride layer outside the gate area until the thickness of the p-type nitride layer outside the gate area is less than 30nm, as shown in Figure 4 (f ) as shown in the figure;

In the seventh step, high-temperature thermal desorption treatment is performed in MOCVD equipment at a reaction temperature of 500°C-1000°C until the p-type nitride layer outside the gate area is removed, as shown in (g) of Figure 4.

Example 2

The specific implementation of this embodiment is similar to Embodiment 1, and the main differences are:

The first protective layer is an AlGaN layer with a thickness of 5 nm, and the Al composition of the AlGaN layer is 0.6;

In the second step, magnetron sputtering technology is used to continue to epitaxially grow a second protective layer on the p-type nitride layer, where the second protective layer is a SiO ₂ layer and its thickness is 50nm;

The high-temperature thermal desorption treatment in the seventh step is performed in a tubular annealing furnace, and the flow of Ga atoms and N atoms must not be introduced during the reaction process.

Example 3

Referring to Figure 5, the specific implementation of this embodiment is similar to Embodiment 1, and the main differences are:

After depositing the channel layer and before depositing the barrier layer, an insertion layer 331 is also deposited. As shown in (a) of Figure 5 , the insertion layer is an AlN layer and its thickness is 1 nm;

In the second step, magnetron sputtering technology is used to continue to epitaxially grow a second protective layer on the p-type nitride layer, as shown in (b) of Figure 5, where the second protective layer is an AlN layer and its thickness is 80nm;

The high-temperature thermal desorption treatment in the seventh step is performed in a high-temperature annealing furnace.

The preparation method of the p-type nitride gate of the enhancement mode HEMT in the embodiment shown in FIG. 3 will be exemplified below with reference to specific examples.

Example 4

The preparation method steps of this embodiment are shown in Figure 7:

In the first step, MOCVD technology is used to sequentially epitaxially grow the buffer layer, channel layer, insertion layer, barrier layer, first protective layer and p-type nitride layer on the substrate, as shown in (a) of Figure 7; Among them, the substrate is a sapphire substrate, the buffer layer is an AlGaN/GaN buffer layer, the channel layer is a GaN layer and its thickness is 300nm, the insertion layer and the first protective layer are AlN layers and both have a thickness of 5nm. The barrier layer is an AlGaN layer, and the p-type nitride layer is a p-GaN layer; a heterojunction with 2DEG is formed between the channel layer and the barrier layer;

In the second step, the gate area mask range is defined through photolithography exposure, as shown in (b) in Figure 7;

In the third step, an oxygen-containing atmosphere is first used to generate plasma to oxidize the surface of the p-type nitride layer outside the gate area. Then, dilute hydrochloric acid is used to remove the oxide layer, and the plasma oxidation and wet etching processes are repeated until the gate The thickness of the p-type nitride layer outside the polar region is etched to less than 30nm, as shown in (c) in Figure 7;

The fourth step is to remove the mask above the p-type nitride layer, as shown in (d) of Figure 7;

The fifth step is to use magnetron sputtering technology to grow a second protective layer on the p-type nitride layer, as shown in (e) of Figure 7, where the second protective layer is a HfO ₂ layer and its thickness is 60nm;

The sixth step is to define the gate area mask range through photolithography exposure, as shown in (f) in Figure 7;

The seventh step is to use wet etching to remove the second protective layer outside the gate area until the p-type nitride layer outside the gate area is exposed, as shown in (g) of Figure 7;

The eighth step is to remove the mask above the second protective layer, as shown in (h) in Figure 7;

The ninth step is to use MOCVD technology to perform high-temperature thermal desorption at a temperature of 500°C-1000°C without introducing Ga atomic flow and N atomic flow until the p-type nitride layer outside the gate area is removed, such as As shown in (i) of Figure 7.

Example 5

Referring to Figure 8, the specific implementation of this embodiment is similar to Embodiment 4, and the main differences are:

After depositing the channel layer, the barrier layer is directly deposited, as shown in (a) of Figure 8 .

Figure 9 schematically shows the process flow of the preparation method of the enhancement type nitride HEMT according to the first embodiment of the present invention. In the process of preparing the enhancement type nitride HEMT, the method uses the p-type nitride gate of the aforementioned enhancement type HEMT. The preparation method prepares a p-type nitride gate of an enhancement-mode HEMT without damage to the surface of the barrier layer, and prepares an enhancement-mode nitride HEMT on this basis to obtain an enhancement-mode nitride HEMT with stable performance.

As shown in Figure 9, the preparation method of the enhancement nitride HEMT of the first embodiment includes the following steps:

Step S101: Prepare a p-type nitride gate of the enhancement-mode HEMT using the aforementioned preparation method of a p-type nitride gate of the enhancement-mode HEMT;

Step S102: Remove the second protective layer and remove the first protective layer in the source electrode region and the drain electrode region;

Step S103: Prepare a source electrode and a drain electrode on the barrier layer of the source electrode region and the drain electrode region respectively, and prepare a gate electrode on the p-type nitride gate.

In the embodiment of the present invention, the specific implementation of step S101 can be implemented with reference to the relevant description of the embodiment shown in Figure 1, Figure 2 or Figure 3.

For example, in step S102, a buffered oxide etching solution (Buffered Oxide Etch, BOE for short) is used to remove the second protective layer, where the second protective layer is a Si ₃ N ₄ layer.

In step S103, both the source electrode and the drain electrode can be made of at least two combinations of Ti, Al, Ni, Au, Cr, P, Pt and TiN. The selected material is grown on the barrier layer and then annealed. To form ohmic contact, the annealing process to form ohmic contact is: place it in an air or nitrogen environment of 0℃-1000℃ for 10s-1h. The gate electrode can be made of at least two combinations of Ti, Al, Ni, Au, Pd, Pt, TiN and W. The selected material is grown on the p-type nitride gate to form Schottky contact or ohmic contact. The Schottky contact of the gate electrode formed on the p-type nitride gate can be improved by annealing. For example, the annealing process to improve Schottky contact is: placing in an air or nitrogen environment of 0°C-500°C for 10s-1h.

Preferably, in step S102, a mask etching process is used to remove the first protective layer in the source electrode region and the drain electrode region. Wherein, the removal of the first protective layer in the source electrode region and the drain electrode region is preferably arranged after the removal of the second protective layer and before step S103. Due to the selective etching of the p-type nitride layer by high-temperature thermal desorption, after the p-type nitride layer outside the gate area is removed, the damage to the surface of the barrier layer is small, resulting in a lower boundary state density on the surface of the barrier layer. Therefore, the source electrode and the drain electrode grown on the barrier layer are more likely to form ohmic contact. Since the second protective layer can prevent the p-type nitride gate from being desorbed during thermal desorption at high temperatures, it can prevent the surface of the p-type nitride gate from being damaged due to high temperature. Therefore, the gate electrode grown on the p-type nitride gate is more likely to form ohms. contact or Schottky contact.

The preparation method of the enhanced nitride HEMT of the first embodiment is illustratively described below with reference to specific examples.

Example 6

Referring to Figure 10, this embodiment continues to be implemented on the basis of Embodiment 3:

The eighth step is to use BOE to remove the second protective layer, as shown in (j1) in Figure 10;

In the ninth step, remove the first protective layer in the source electrode and drain electrode areas through a mask etching process, as shown in (k1) in Figure 10;

In the tenth step, under room temperature conditions where the atmosphere is air, the source electrode 392 is prepared using Ti, Al and Ni, the drain electrode 393 is prepared using Cr, P, Pt and TiN, and the gate electrode is prepared using Au, Pd, Pt, TiN and W. 391, as shown in (m1) in Figure 10; where the source electrode and drain electrode form ohmic contact with the barrier layer, and the gate electrode and the p-type nitride gate form Schottky contact.

Example 7

The specific implementation manner of this embodiment is similar to that of Embodiment 6, and the main difference lies in the formation of ohmic contact between the gate electrode and the p-type nitride gate.

Example 8

Referring to Figure 10, the specific implementation of this embodiment is similar to Embodiment 7, and the main differences are:

After depositing the channel layer, the barrier layer is directly deposited, and the final enhanced nitride HEMT is shown in (m2) in Figure 10.

Figure 11 schematically shows the flow chart of the preparation method of the enhanced nitride HEMT according to the second embodiment of the present invention. This implementation mode further includes the following steps based on the first implementation mode of the preparation method of the enhanced nitride HEMT:

Step S104: Deposit an insulating dielectric layer 394 on the surfaces of the source electrode, drain electrode, gate electrode, p-type nitride gate and second protective layer, and connect the insulating dielectric layer 394 to the source electrode, drain electrode and the surface through photolithography and etching processes. The corresponding position of the gate electrode is removed until the source electrode, drain electrode and gate electrode are exposed. For example, the insulating dielectric layer is a SiO ₂ layer, a SiN _x layer, a HfO ₂ layer or a polyimide layer.

Therefore, the insulating dielectric layer deposited on the surface of the enhancement nitride HEMT can reduce the impact of external environments, such as radiation, on the 2DEG and P-type nitride gate, ensuring the stability and reliability of the enhancement nitride HEMT operation.

The preparation method of the enhanced nitride HEMT of the second embodiment is illustratively described below with reference to specific examples.

Example 9

Referring to Figure 12, this embodiment continues to be implemented on the basis of Embodiment 6:

In the eleventh step, an insulating dielectric layer is deposited on the surface of the source electrode, drain electrode, gate electrode, p-type nitride gate and second protective layer; where the dielectric layer is a SiN _x layer, as shown in (n1) in Figure 12 Show.

In the twelfth step, the positions of the insulating dielectric layer corresponding to the source electrode, drain electrode and gate electrode are removed through photolithography and etching processes until the source electrode, drain electrode and gate electrode are exposed, as shown in (o1) in Figure 12 Show.

Example 10

Referring to Figure 12, the specific implementation of this embodiment is similar to Embodiment 9, and the main differences are:

After depositing the channel layer, the barrier layer is directly deposited, and the final enhanced nitride HEMT is shown in (o2) in Figure 12.

In the p-type nitride gate preparation method of the enhancement mode HEMT and the preparation method of the enhancement mode nitride HEMT of the present invention, the MOCVD method and the MBE method are used for the specific process of epitaxial growth, and the photolithography exposure defines the gate area mask range. The specific process includes dry etching to remove the second protective layer outside the gate area, low-power dry etching to etch the p-type nitride layer outside the gate area, and the LPCVD method is used to etch the p-type nitride layer outside the gate area. The specific process of depositing a second protective layer on the nitride layer to grow the second protective layer, the specific process of removing the second protective layer outside the gate area by wet etching, the specific process of removing the second protective layer by BOE, using a mask The specific process of removing the first protective layer in the source electrode region and the drain electrode region by film etching, preparing the source electrode and the drain electrode respectively on the barrier layers of the source electrode region and the drain electrode region, and on the p-type nitride gate The specific process of preparing the gate electrode and covering the surface of the enhancement mode nitride HEMT with an insulating dielectric layer can refer to the commonly used processes in the prior art. The present invention does not limit the specific implementation of the above process.

The specific process of using plasma oxidation combined with wet etching to etch the p-type nitride layer outside the gate area can be implemented by referring to the specific process in publication number CN112067402A.

What is described above are only some embodiments of the present invention. For those of ordinary skill in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, and these all belong to the protection scope of the present invention.

Claims (10)

1. A method for manufacturing a p-type nitride gate of an enhancement HEMT, characterized in that, when manufacturing the p-type nitride gate, the method removes a p-type nitride layer outside a gate region by high temperature thermal desorption, and the method further comprises:

in the preparation process of the epitaxial structure, a first protective layer is deposited on the barrier layer, and then a p-type nitride layer is deposited on the first protective layer, wherein the first protective layer is made of a material with the thermal desorption temperature higher than that of the p-type nitride layer, and the thickness range of the first protective layer is set to be 1nm-5nm;

before the p-type nitride layer outside the gate region is subjected to high-temperature thermal desorption, etching treatment is further carried out on the p-type nitride layer outside the gate region until the residual thickness of the p-type nitride layer outside the gate region is smaller than 30nm, and a second protective layer is further prepared on the p-type nitride layer of the gate region, wherein the second protective layer is made of a high-temperature resistant dielectric material.

2. The method for manufacturing a p-type nitride gate of an enhancement HEMT according to claim 1, wherein said p-type nitride layer is a p-GaN layer;

the temperature range of the high-temperature thermal desorption is 500-1000 ℃.

3. The method of manufacturing a p-type nitride gate of an enhanced HEMT of claim 2, wherein said high temperature thermal desorption is performed in a high temperature processing apparatus.

4. The method for manufacturing a p-type nitride gate of an enhanced HEMT according to claim 2, wherein said first protective layer is an AlN layer;

or the first protective layer is an AlGaN layer, and the Al component of the AlGaN layer is between 0.5 and 1.

5. The method for manufacturing a p-type nitride gate of an enhanced HEMT according to claim 2, wherein the second protective layer is a high-temperature resistant dielectric layer with a thickness ranging from 50nm to 200nm.

6. The method of manufacturing a p-type nitride gate of an enhancement HEMT according to any one of claims 1 to 5, wherein said manufacturing a second protective layer on the p-type nitride layer of the gate region is realized by comprising:

after etching the p-type nitride layer outside the gate region to a residual thickness of less than 30nm, preparing a second protective layer on the p-type nitride layer;

Covering a mask layer on the second protective layer of the grid electrode region; and

removing the second protective layer outside the grid region through etching treatment;

or is realized as comprising:

after preparing the p-type nitride layer, preparing a second protective layer directly on the p-type nitride layer; and

before etching the p-type nitride layer, defining a mask range of the gate region, and removing the second protective layer outside the defined gate region by etching.

7. The method for manufacturing a p-type nitride gate of an enhanced HEMT according to claim 6, wherein the etching treatment is performed on the p-type nitride layer outside the gate region until the residual thickness of the p-type nitride layer outside the gate region is less than 30nm, by low-power dry etching or by plasma oxidation in combination with wet etching.

8. The method for manufacturing a p-type nitride gate of an enhanced HEMT according to claim 7, wherein the acid used for wet etching is dilute hydrochloric acid and the second protective layer is a material resistant to dilute hydrochloric acid etching.

9. The preparation method of the enhanced nitride HEMT is characterized by comprising the following steps of:

step S101: a p-type nitride gate of an enhancement HEMT manufactured by the manufacturing method of the p-type nitride gate of an enhancement HEMT according to any one of claims 1 to 8;

Step S102: removing the second protective layer and removing the first protective layers of the source electrode region and the drain electrode region;

step S103: source and drain electrodes are respectively prepared on barrier layers of the source and drain regions, and a gate electrode is prepared on the p-type nitride gate.

10. The method of manufacturing an enhancement nitride HEMT according to claim 9, further comprising, after step S103

Step S104: and depositing an insulating dielectric layer on the surfaces of the source electrode, the drain electrode, the gate electrode, the p-type nitride gate and the second protective layer, and removing the positions of the insulating dielectric layer corresponding to the source electrode, the drain electrode and the gate electrode through photoetching and corrosion processes until the source electrode, the drain electrode and the gate electrode are exposed.