JP5768340B2 - Compound semiconductor device - Google Patents

Description

  The present invention relates to a compound semiconductor device including a compound semiconductor layer and a manufacturing method thereof.

  Nitride semiconductor devices have been actively developed as high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. As nitride semiconductor devices, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). In particular, AlGaN / GaN HEMTs using GaN as an electron transit layer and AlGaN as an electron supply layer are attracting attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, high breakdown voltage and high output can be realized.

JP-A-9-246285 Japanese Patent Laid-Open No. 61-228664 JP-A-4-255235 JP-A-6-132314

  In the HEMT, research and development of a gate electrode capable of reducing the gate capacitance and the gate resistance in order to further improve the high-frequency characteristics is underway. In a HEMT having a so-called overhang-shaped T-shaped gate electrode, it is necessary to separate the gate and the drain to some extent in consideration of improvement in breakdown voltage and higher output, and in consideration of higher frequency, between the gate and the source. It is necessary to have a structure that reduces the capacitance and source resistance. In order to reduce the capacitance between the gate and the source, it is desirable to increase the distance between the gate and the source. On the other hand, in order to reduce the source resistance, it is desirable to reduce the distance between the gate and the source. Several techniques have been devised to devise the structure of the gate electrode, but no gate electrode that satisfies the above-mentioned conflicting structural requirements has been devised. A gate electrode that satisfies this requirement is considered to require a relatively complicated shape, and it is very difficult to manufacture the gate electrode.

  The present invention has been made in view of the above-described problems, and is capable of mass production that easily and reliably realizes reduction in gate-source capacitance and source resistance, as well as improvement in breakdown voltage, higher output, and higher frequency. An object of the present invention is to provide a highly reliable compound semiconductor device having excellent reliability and a method for manufacturing the same.

One aspect of the compound semiconductor device includes a substrate, a compound semiconductor layer formed above the substrate, a source electrode and a drain electrode formed above the compound semiconductor layer, and the compound semiconductor layer above the compound semiconductor layer. A gate electrode formed between the source electrode and the drain electrode, the gate electrode including a trunk-like lower portion including a contact surface with the upper side of the compound semiconductor layer, and an umbrella shape from the lower portion The lower portion is integrally formed with the expanding upper portion, and the lower portion is provided at a position where the contact surface is biased to the source electrode as compared to the drain electrode. of the end face, the high height from the surface of the substrate than the site of the site of the source electrode side is the drain electrode side, the gate electrode, the compound half from the lower end surface of the upper portion Region to the surface of the body layer is hollow.

  According to the above aspects, the gate-source capacitance is reduced, the source resistance is reduced, and withstand voltage improvement, high output, and high frequency can be achieved easily and reliably. A compound semiconductor device is realized.

It is a schematic sectional drawing which shows the manufacturing method of the Schottky type AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 illustrating a Schottky-type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view showing the Schottky type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing method of the Schottky type AlGaN / GaN.HEMT according to the first embodiment in order of processes following FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating the manufacturing method of the Schottky-type AlGaN / GaN.HEMT according to the first embodiment in order of processes following FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating the manufacturing method of the Schottky type AlGaN / GaN.HEMT according to the first embodiment in the order of steps, following FIG. 5. It is a schematic sectional drawing which shows the manufacturing method of MIS type AlGaN / GaN * HEMT by 2nd Embodiment to process order. FIG. 7 is a schematic cross-sectional view illustrating the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the second embodiment in the order of steps, following FIG. 6. It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the following embodiments, AlGaN / GaN HEMT is disclosed as a compound semiconductor device, and the configuration thereof will be described together with a manufacturing method. In the following drawings, there are constituent members that are not shown in a relatively accurate size and thickness for convenience of illustration. In various embodiments, element isolation is performed by a predetermined element isolation method, for example, an STI (Shallow Trench Isolation) method, ion implantation into an element isolation region, or the like.

(First embodiment)
In the present embodiment, a Schottky type AlGaN / GaN HEMT is disclosed.
1 to 6 are schematic cross-sectional views showing a method of manufacturing a Schottky AlGaN / GaN HEMT according to the first embodiment in the order of steps. 2 to 6 show only components above the cap layer 5.

  First, as shown in FIG. 1A, an electron transit layer 2, an intermediate layer 3, an electron supply layer 4, and a cap layer 5 are sequentially formed on, for example, a semi-insulating SiC substrate 1 as a growth substrate. In the AlGaN / GaN.HEMT, a two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2 and the electron supply layer 4 (directly the intermediate layer 3).

Specifically, the following compound semiconductor layers are grown on the SiC substrate 1 by, for example, a molecular beam epitaxy (MBE) method. Instead of the MBE method, a metal organic chemical vapor deposition (MOCVD) method which is a metal organic vapor phase epitaxy method may be used.
On the SiC substrate 1, i-GaN, i-AlGaN, n-AlGaN, and n ⁺ -GaN are sequentially deposited to form an electron transit layer 2, an intermediate layer 3, an electron supply layer 4, and a cap layer 5. . As growth conditions for the above i-GaN, i-AlGaN, n-GaN, and n-AlGaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. The presence / absence and flow rate of trimethylaluminum gas as an Al source and trimethylgallium gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C. When growing n-GaN and n-AlGaN, for example, SiH ₄ gas containing, for example, Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

  Here, the electron transit layer 2 has a thickness of about 2 μm, the intermediate layer 3 has a thickness of about 5 nm, for example, an Al ratio of 0.2, the electron supply layer 4 has a thickness of about 30 nm, for example, an Al ratio of 0.2, and the cap layer 5 has The film is formed to a thickness of about 10 nm. The electron supply layer 4 may be an intentionally undoped AlGaN (i-AlGaN) layer.

Subsequently, as shown in FIG. 1B, a resist mask 10 for forming a source electrode and a drain electrode is formed.
Specifically, a resist is applied on the cap layer 5 and the resist is processed by lithography. Thereby, the resist mask 10 having the openings 10a and 10b is formed. The opening 10 a is formed so as to expose a source electrode formation site on the surface of the cap layer 5. The opening 10b is formed so as to expose the drain electrode formation site on the surface of the cap layer 5.

Subsequently, as shown in FIG. 1C, a source electrode 6 and a drain electrode 7 are formed.
Specifically, for example, Ti / Al is used as the electrode material, and Ti / Al is deposited on the resist mask 10 so as to fill the openings 10a and 10b by vapor deposition or the like. The resist mask 10 and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, SiC substrate 1 is heat-treated at, for example, about 600 ° C. in a nitrogen atmosphere to establish ohmic contact. Thus, the source electrode 6 and the drain electrode 7 are formed on the cap layer 5.

Subsequently, as shown in FIG. 2A, a passivation film 8 is formed.
Specifically, for example, an insulating film, here, a SiN film is deposited to a thickness of, for example, about 35 nm to 45 nm so as to cover the entire surface of the SiC substrate 1 including the source electrode 6 and the drain electrode 7 by PECVD. Thereby, passivation film 8 that functions as a protective film on the surface of SiC substrate 1 including on source electrode 6 and on drain electrode 7 is formed.

Subsequently, as shown in FIG. 2B, a first electron beam resist 11 and a second electron beam resist 12 are applied.
Specifically, a resist, here, the first electron beam resist 11 and the second electron beam resist 12 are sequentially applied and formed on the passivation film 8 to a thickness of about 300 nm and a thickness of about 300 nm to 500 nm, for example. The first electron beam resist 11 is lower in electron beam sensitivity than the second electron beam resist 12. Specifically, for example, polymethyl methacrylate (PMMA) resist or the like is used as the first electron beam resist 11, and for example, trade name ZEP520A-7 manufactured by Nippon Zeon Co., Ltd. is used as the second electron beam resist 12.

Subsequently, as shown in FIG. 2C, the second electron beam resist 12 is exposed to an electron beam.
Specifically, a portion of the second electron beam resist 12 on the drain electrode 7 side is exposed with a relatively low dose, for example, an electron beam of about 140 μC to 200 μC. In the example shown in the figure, the electron beam exposed portion of the second electron beam resist 12 is defined as an exposed portion 12a. At this time, since the first electron beam resist 11 is a resist having a lower electron beam sensitivity than the second electron beam resist 12, it does not open due to development even if it is exposed.

Subsequently, as shown in FIG. 3A, the exposed portion 12a is removed.
Specifically, the exposed portion 12a of the second electron beam resist 12 is developed and removed. Thereby, the second electron beam resist 12 remains in a stepped manner in a region including a portion corresponding to the upper portion of the source electrode 6 on the first electron beam resist 11.

Subsequently, as shown in FIG. 3B, a third electron beam resist 13 and a fourth electron beam resist 14 are applied.
Specifically, the third electron beam resist 13 and the fourth electron beam resist 14 are formed on the first electron beam resist 11 so as to cover the second electron beam resist 12, for example, a thickness of about 500 nm to 550 nm and a thickness. The coating is sequentially formed to about 250 nm to 300 nm. The third electron beam resist 13 is a resist having higher electron beam sensitivity than the first electron beam resist 11 and the second electron beam resist 12. Specifically, as the third electron beam resist 13, for example, polydimethylglutarimide (PMGI) or the like is used, and as the fourth electron beam resist 14, for example, trade name ZEP520A-7 manufactured by Nippon Zeon Co., Ltd. is used.

Subsequently, as shown in FIG. 3C, the fourth electron beam resist 14 and the third electron beam resist 13 are subjected to electron beam exposure.
Specifically, the fourth electron beam resist 14 and the second electron beam resist 14 biased to the source electrode 8 side with respect to the drain electrode 6 so as to extend over the tip portion 12b of the second electron beam resist 12 below the third electron beam resist 13. The third electron beam resist 13 is exposed with an electron beam having a dose of about 120 μC, for example. In the illustrated example, the exposed portions 15 of the third electron beam resist 13 and the fourth electron beam resist 14 are exposed. At this time, since the first electron beam resist 11 and the second electron beam resist 12 are resists having electron beam sensitivity lower than that of the third electron beam resist 13, they are not opened by development even if exposed.

Subsequently, as shown in FIG. 4A, a first opening 16 is formed in the third electron beam resist 13 and the fourth electron beam resist 14.
Specifically, the exposed portions 15 of the third electron beam resist 13 and the fourth electron beam resist 14 are developed and removed. As a result, the third electron beam resist 13 and the fourth electron beam resist 14 are exposed to a part of the surface of the first electron beam resist 11 and the tip portion 12 b of the second electron beam resist 12. The opening 16 is formed.

Subsequently, as shown in FIG. 4B, the third electron beam resist 13 exposed on the side surface of the first opening 16 is retracted.
Specifically, the third electron beam resist 13 is developed following FIG. The third electron beam resist 13 has higher electron beam sensitivity than the first electron beam resist 11, the second electron beam resist 12, and the fourth electron beam resist 14, and is developed by using a predetermined developer. The rate will be higher. Therefore, the portion of the third electron beam resist 13 exposed on the side surface of the first opening 16 recedes in the lateral direction by a predetermined amount corresponding to the development time or the like. As a result, a gap 17a is formed between the second electron beam resist 12 and the fourth electron beam resist 14 in the third electron beam resist 13, and the first electron beam resist 11 and the fourth electron beam resist. 14 are formed in the gaps 17b. By forming the gap 17a, the tip portion 12b of the second electron beam resist 12 is enlarged.

Subsequently, as shown in FIG. 4C, the first electron beam resist exposed from the first opening 16 is exposed to an electron beam.
Specifically, the portion biased to the source electrode 6 is exposed to an electron beam having a relatively high dose, for example, about 500 μC to 600 μC, as compared with the drain electrode 7 of the first electron beam resist exposed from the first opening 16. . In the example shown in the drawing, an electron beam exposed portion of the first electron beam resist 11 is defined as an exposed portion 11a.

Subsequently, as shown in FIG. 5A, a second opening 11 b is formed in the first electron beam resist 11.
Specifically, the exposed portion 11a of the first electron beam resist 11 is developed and removed. As a result, the second opening 11b of the fine gate is formed in the first electron beam resist 11 at a portion biased to the source electrode 6 as compared with the drain electrode 7 of the first electron beam resist. The first opening 16 and the second opening 11b communicate with each other. In the example shown in the figure, this open opening is referred to as a gate opening 17.

Subsequently, as shown in FIG. 5B, a third opening 8 a is formed in the passivation film 8.
Specifically, using the first electron beam resist 11 as a mask, the passivation film 8 is dry etched until the surface of the cap layer 5 is exposed. As a result, a third opening 8 a that follows the second opening 11 b of the first electron beam resist 11 is formed in the passivation film 8.

Subsequently, as shown in FIG. 5C, the second opening 11b of the first electron beam resist 11 is enlarged in a tapered shape.
The SiC substrate 1 is heat-treated at 120 ° C. for about 1 minute, for example. Thereby, the 2nd opening 11b of the 1st electron beam resist 11 expands in a taper shape.

Subsequently, as shown in FIG. 6A, an electrode material 18 of a gate electrode is formed.
Specifically, for example, Ni / Au is used as the electrode material 18, and Ni / Au is deposited so as to embed the second opening 11b and the third opening 8a in the gate opening 17 by vapor deposition or the like. The electrode material 18 is also deposited on the fourth electron beam resist 15. As the electrode material 18, Ti / Pt / Au may be deposited instead of Ni / Au.

Subsequently, as shown in FIG. 6B, a gate electrode 19 is formed.
Specifically, the first electron beam resist 11, the second electron beam resist 12, the third electron beam resist 13, the fourth electron beam resist 15, and the fourth electron beam resist 15 are formed by a lift-off method. Ni / Au deposited on the substrate is removed. As described above, the overhanging gate electrode 19 is formed on the cap layer 5 so as to fill the third opening 8a with Ni / Au and protrude upward from the surface of the passivation film 8. When Ti / Pt / Au is used for the electrode material 18, the third opening 8 a is filled with Ti / Pt / Au so as to protrude upward from the surface of the passivation film 8. An overhanging gate electrode 19 is formed.

  After that, a Schottky type AlGaN / GaN HEMT is formed through various processes such as formation of an interlayer insulating film covering the gate electrode 19, formation of the source electrode 6, the drain electrode 7, and a wiring electrically connected to the gate electrode 19. Is done.

  In the present embodiment, since only the electron beam resist (first to fourth electron beam resists 11 to 14) is used as a resist in the step of forming the gate electrode 19, the first to fourth electron beams are used for electron beam exposure. What is necessary is just to set irradiation dose amount according to the sensitivity of the resists 11-14. Thereby, there is no problem of difficulty in controllability of etching as in the case of performing lithography and dry etching for forming the gate electrode, and the gate electrode 19 can be precisely formed more easily. Since the gate opening 17 is formed by electron beam exposure, a fine gate structure can be realized, and the AlGaN / GaN HEMT can be further increased in frequency and output.

  As shown in FIG. 6B, the gate electrode 19 is integrally formed with a trunk-like lower part 19a including a contact surface with the cap layer 5 and an upper part 19b extending in an umbrella shape from the lower part 19a. The upper portion 19b has an asymmetric shape between the source electrode 6 side and the drain electrode 7 side. The lower portion 19 a is provided at a position where the contact surface with the cap layer 5 is biased toward the source electrode 6 as compared with the drain electrode 7. When the gate electrode 19 is formed, the first opening 16 is formed so that the tip portion 12b of the second electron beam resist 12 is exposed. Therefore, the upper portion 19b has a portion 19b1 on the source electrode 6 side of the umbrella-shaped lower end surface that is higher than the portion 19b2 on the drain electrode 7 side from the surface of the cap layer 5 (or the surface of the SiC substrate 1). Is formed high. Thus, in the gate electrode 19, the portion 19 b 1 on the source electrode 6 side is formed higher than the portion 19 b 2 on the drain electrode 7 side, so that the upper portion 19 b is separated from the source electrode 6 as much as possible. And the gate electrode 19 are reduced. In addition, by adopting the asymmetric shape, the gate electrode 19 (the contact surface with the cap layer 5) can be brought close to the source electrode 6, and the electrical resistance between the source electrode 6 and the gate electrode 19 is reduced. The At this time, since the gate electrode 19 is sufficiently separated from the drain electrode 7, the breakdown voltage of the AlGaN / GaN HEMT can be improved and the output can be increased. Furthermore, in the present embodiment, the manufacturing variation of the gate electrode 19 that occurs when the umbrella-shaped upper portion 19b is close to the source electrode 6 is reduced. Therefore, efficient mass production of AlGaN / GaN.HEMT becomes possible.

  As described above, according to the present embodiment, the capacitance between the gate electrode 19 and the source electrode 6 and the source resistance can be reduced, and the breakdown voltage can be improved, the output can be increased, and the frequency can be increased easily and reliably. A highly reliable AlGaN / GaN HEMT with excellent mass production is realized.

(Second Embodiment)
In the present embodiment, an MIS type AlGaN / GaN HEMT is disclosed.
7 and 8 are schematic cross-sectional views showing the method of manufacturing the MIS type AlGaN / GaN HEMT according to the second embodiment in the order of steps. 6 and 7, only the components above the cap layer 5 are shown.

First, similarly to the first embodiment, the same processes as in FIGS. 1A to 1C are executed.
Subsequently, as shown in FIG. 7A, a gate insulating film 21 is formed.
More specifically, a high dielectric film, in this case, a SiN film, for example, having a film thickness of 35 nm to 45 nm is formed as an insulating film so as to cover the entire surface of the SiC substrate 1 including the source electrode 6 and the drain electrode 7 by, for example, PECVD. Deposit to a degree. Thereby, the gate insulating film 21 is formed. The gate insulating film 21 also functions as a protective film for the surface of the SiC substrate 1 including the source electrode 6 and the drain electrode 7. As the gate insulating film 21, SiO ₂ , HfSiO, HfAlON, HfO ₂ or the like may be formed instead of forming SiN.

Subsequently, similarly to the first embodiment, the same processes as in FIGS. 2B to 5A are executed.
Subsequently, as shown in FIG. 7B, the second opening 11b of the first electron beam resist 11 is enlarged in a tapered shape.
The SiC substrate 1 is heat-treated at 120 ° C. for about 1 minute, for example. Thereby, the 2nd opening 11b of the 1st electron beam resist 11 expands in a taper shape.

Subsequently, as shown in FIG. 8A, an electrode material 18 of a gate electrode is formed.
Specifically, for example, Ni / Au is used as the electrode material 18, and Ni / Au is deposited so as to embed the second opening 11b in the gate opening 17 by vapor deposition or the like.

Subsequently, as shown in FIG. 8B, a gate electrode 19 is formed.
Specifically, the first electron beam resist 11, the second electron beam resist 12, the third electron beam resist 13, the fourth electron beam resist 15, and the fourth electron beam resist 15 are formed by a lift-off method. Ni / Au deposited on the substrate is removed. As described above, the overhanging gate electrode 19 is formed on the cap layer 5 via the gate insulating film 21 so as to protrude upward from the surface of the gate insulating film 21.

  Thereafter, an MIS type AlGaN / GaN HEMT is formed through various processes such as formation of an interlayer insulating film covering the gate electrode 19, formation of the source electrode 6, the drain electrode 7, and a wiring electrically connected to the gate electrode 19. The

  As described above, according to the present embodiment, it is possible to easily and surely reduce the capacitance between the gate electrode 19 and the source electrode 6 and the source resistance, and improve the breakdown voltage, increase the output, and increase the frequency. A highly reliable AlGaN / GaN.HEMT excellent in mass production is realized.

  In the first and second embodiments described above, the AlGaN / GaN HEMT is exemplified as the compound semiconductor device. However, the present invention is not limited to this, and can be applied to other HEMTs. For example, the following modes (1) to (5) can be considered.

Aspect (1)
An AlN / InAlN.HEMT is disclosed as a compound semiconductor device.
InAlN and AlN are compound semiconductors in which the latter has a smaller lattice constant than the former. In this case, for example, in FIG. 1A, the electron transit layer 2 is formed of i-InAlN, the intermediate layer 3 is formed of i-AlN, the electron supply layer 4 is formed of n-AlN, and the cap layer 5 is formed of n ⁺ -InAlN.

Aspect (2)
An AlN / InAlGaN.HEMT is disclosed as a compound semiconductor device.
InAlGaN and AlN are compound semiconductors in which the latter has a smaller lattice constant than the former. In this case, for example, in FIG. 1A, the electron transit layer 2 is formed of i-InAlGaN, the intermediate layer 3 is formed of i-AlN, the electron supply layer 4 is formed of n-AlN, and the cap layer 5 is formed of n ⁺ -InAlGaN.

Aspect (3)
InAlGaN / InAlN.HEMT is disclosed as a compound semiconductor device.
In InAlN and InAlGaN, the magnitude relation of the lattice constant changes by adjusting the composition ratio of In, Al, and Ga. By adjusting the composition ratio, the lattice constant of InAlN can be made smaller than the lattice constant of InAlGaN, or conversely, the lattice constant of InAlGaN can be made smaller than the lattice constant of InAlN. Here, a case where the lattice constant of InAlGaN is made smaller than the lattice constant of InAlN is illustrated.
In this case, for example, in FIG. 1A, the electron transit layer 2 is formed of i-InAlN, the intermediate layer 3 is formed of i-InAlGaN, the electron supply layer 4 is formed of n-InAlGaN, and the cap layer 5 is formed of n ⁺ -InAlN.

Aspect (4)
As a compound semiconductor device, Al _0.5 Ga _0.5 N / Al _0.3 Ga _0.7 N · HEMT is disclosed.
Even in the same type of compound semiconductor, the lattice constants are different if the composition ratio is different. As different lattice constants in one compound semiconductor, for example, the AlGaN, it is conceivable to Al _0.3 Ga _0.7 N and Al _0.5 Ga _0.5 N. In AlGaN, the lattice constant decreases as the Al composition ratio increases. Therefore, Al _0.5 Ga _0.5 N has a smaller lattice constant than Al _0.3 Ga _0.7 N.
In this case, for example, in FIG. 1A, the electron transit layer 2 is i-Al _0.3 Ga _0.7 N, the intermediate layer 3 is i-Al _0.5 Ga _0.5 N, the electron supply layer 4 is n-Al _0.5 Ga _0.5 N, and the cap Layer 5 is formed of n ⁺ -Al _0.3 Ga _0.7 N.

Aspect (5)
As a compound semiconductor device, ZnMgO / ZnO.HEMT is disclosed.
In this case, for example, in FIG. 1A, the electron transit layer 2 is formed of i-ZnO, the intermediate layer 3 is formed of i-ZnMgO, the electron supply layer 4 is formed of n-ZnMgO, and the cap layer 5 is formed of n ⁺ -ZnO.

(Third embodiment)
In the present embodiment, a power supply device including a HEMT according to any one of the first and second embodiments is disclosed.
FIG. 9 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes an AC power supply 34, a so-called bridge rectifier circuit 35, and a plurality (four in this case) of switching elements 36a, 36b, 36c, and 36d. The bridge rectifier circuit 35 includes a switching element 36e.
The secondary side circuit 32 includes a plurality (three in this case) of switching elements 37a, 37b, and 37c.

  In the present embodiment, the switching elements 36a, 36b, 36c, 36d, 36e of the primary side circuit 31 are HEMTs according to any one of the first and second embodiments. On the other hand, the switching elements 37a, 37b, 37c of the secondary circuit 32 are general MIS • FETs using silicon.

  In the present embodiment, the reliability between the gate electrode 19 and the source electrode 6 is reduced in capacitance and the source resistance, and is excellent in mass production that can easily and surely improve the breakdown voltage, increase the output, and increase the frequency. A high HEMT is applied to the high voltage circuit. As a result, a highly reliable high-power power supply circuit is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier including a HEMT according to any one of the first and second embodiments is disclosed.
FIG. 10 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high frequency amplifier according to the present embodiment is applied to, for example, a power amplifier for a base station of a mobile phone. The high-frequency amplifier includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies the input signal mixed with the AC signal, and includes the HEMT according to any one of the first and second embodiments. In FIG. 10, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In the present embodiment, the reliability between the gate electrode 19 and the source electrode 6 is reduced in capacitance and the source resistance, and is excellent in mass production that can easily and surely improve the breakdown voltage, increase the output, and increase the frequency. A high HEMT is applied to a high frequency amplifier. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

  Hereinafter, various aspects of the compound semiconductor device and the manufacturing method thereof will be collectively described as supplementary notes.

(Appendix 1) a substrate;
A compound semiconductor layer formed above the substrate;
A source electrode and a drain electrode formed above the compound semiconductor layer;
A gate electrode formed between the source electrode and the drain electrode above the compound semiconductor layer; and
The gate electrode is integrally formed with a trunk-like lower part including a contact surface with the upper part of the compound semiconductor layer and an upper part extending in an umbrella shape from the lower part,
The lower portion is provided at a position where the contact surface is biased to the source electrode compared to the drain electrode,
The compound semiconductor device according to claim 1, wherein the upper portion of the umbrella-shaped lower end surface has a higher height from the surface of the substrate than the portion on the source electrode side than the portion on the drain electrode side.

  (Supplementary note 2) The compound semiconductor device according to supplementary note 1, wherein the gate electrode is formed on the compound semiconductor layer.

(Additional remark 3) The insulating film which covers the said compound semiconductor layer and has an opening which exposes a part of surface of the said compound semiconductor layer is formed,
The compound semiconductor device according to appendix 2, wherein the gate electrode is formed so that the lower portion is embedded in the opening.

(Appendix 4) An insulating film covering the compound semiconductor layer is formed,
The compound semiconductor device according to appendix 1, wherein the gate electrode is formed on the insulating film.

(Appendix 5) Forming a compound semiconductor layer above the substrate;
Forming a source electrode and a drain electrode above the compound semiconductor layer;
Forming a gate electrode between the source electrode and the drain electrode above the compound semiconductor layer, and
The step of forming the gate electrode includes:
A first resist and a second resist are sequentially formed above the compound semiconductor layer;
Removing a part of the second electron beam resist on the drain electrode side;
A third resist and a fourth resist are sequentially formed so as to cover the first resist and the second resist,
Forming a first opening in the fourth resist and the third resist so that a part of the surface of the first resist and a tip portion of the second resist are exposed;
A second opening is formed in the first resist exposed from the first opening at a portion biased to the source electrode compared to the drain electrode;
A method of manufacturing a compound semiconductor device, wherein a conductive material is embedded in the first opening and the second opening that are in communication to form the gate electrode.

  (Additional remark 6) The said 1st resist, the said 2nd resist, the said 3rd resist, and the said 4th resist are electron beam resists, The manufacture of the compound semiconductor device of Additional remark 5 characterized by the above-mentioned Method.

  (Supplementary note 7) The method of manufacturing a compound semiconductor device according to supplementary note 6, wherein the first resist has lower electron beam sensitivity than the second resist.

  (Supplementary note 8) The method for manufacturing a compound semiconductor device according to supplementary note 7, wherein the first resist and the second resist have lower electron beam sensitivity than the third resist.

  (Appendix 9) The compound according to any one of appendices 5 to 8, wherein after the first opening is formed, the third resist exposed on the side surface of the first opening is retracted. A method for manufacturing a semiconductor device.

(Additional remark 10) Before forming the said 1st resist, it further includes the process of forming the insulating film which covers the said compound semiconductor layer,
A third opening that follows the second opening is formed in the insulating film so as to expose a part of the surface of the compound semiconductor layer. The manufacturing method of the compound semiconductor device of description.

(Additional remark 11) Before forming the said 1st resist, it further includes the process of forming the insulating film which covers the said compound semiconductor layer,
The manufacturing method of a compound semiconductor device according to any one of appendices 5 to 9, wherein the second opening is formed in the first resist so as to expose a part of the surface of the insulating film. Method.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 Electron travel layer 3 Intermediate layer 4 Electron supply layer 5 Cap layer 6 Source electrode 7 Drain electrode 8 Passivation film 8a Third opening 10 Resist mask 11 First electron beam resists 11a, 12a, 15 Exposed portion 11b First 2 opening 12 second electron beam resist 12b tip portion 13 third electron beam resist 14 fourth electron beam resist 15 exposed portion 16 first opening 17 gap 18 electrode material 19 gate electrode 19a lower portion 19b upper portion 19b1 Site 19b2 on source electrode 6 Site 21 on drain electrode 7 Gate insulating film 31 Primary side circuit 32 Secondary side circuit 33 Transformer 34 AC power supply 35 Bridge rectifier circuits 36a, 36b, 36c, 36d, 36e, 37a, 37b, 37c Switching element 41 Digital predistortion circuit 42 a, 42b Mixer 43 Power amplifier

Claims (4)

A substrate,
A compound semiconductor layer formed above the substrate;
A source electrode and a drain electrode formed above the compound semiconductor layer;
A gate electrode formed between the source electrode and the drain electrode above the compound semiconductor layer; and
The gate electrode is integrally formed with a trunk-like lower part including a contact surface with the upper part of the compound semiconductor layer and an upper part extending in an umbrella shape from the lower part,
The lower portion is provided at a position where the contact surface is biased to the source electrode compared to the drain electrode,
The upper portion of the umbrella-shaped lower end surface has a higher height from the surface of the substrate than the portion on the source electrode side of the source electrode side portion,
The compound semiconductor device , wherein the gate electrode has a hollow area from the lower end surface of the upper portion to the surface of the compound semiconductor layer. Covering the compound semiconductor layer, an insulating film having an opening exposing a part of the surface of the compound semiconductor layer is formed,
2. The compound semiconductor device according to claim 1, wherein the gate electrode is formed on the compound semiconductor layer so that the opening is embedded in the lower portion. An insulating film covering the compound semiconductor layer is formed;
The compound semiconductor device according to claim 1, wherein the gate electrode is formed on the insulating film.   The compound semiconductor device according to claim 1, wherein the lower portion of the gate electrode is formed in a tapered shape.

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