TWI701789B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes isolation structures, lightly doped regions, a gate, a gate dielectric layer, heavily doped regions, a dielectric layer, a first contact, second contacts and a connection line. The isolation structure is disposed in a substrate to define an active area. The lightly doped region is disposed in the substrate in the active area. The gate is disposed in the substrate in the active area, and a bottom surface of the gate is lower than a bottom surface of the lightly doped regions. The gate dielectric layer is disposed between the gate and the substrate. The heavily doped regions are disposed in the lightly doped regions and are located at opposite sides of the gate. The dielectric layer is disposed on the substrate. The first contact is disposed in the dielectric layer and connected to the gate. The second contacts are disposed in the dielectric layer and connected to the heavily doped regions. The connecting line is disposed in the dielectric layer and the isolation structure therebelow.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and its manufacturing method.

In the current semiconductor manufacturing process, after the gate structure is formed, a dielectric layer is formed on the substrate, and then a contact window connected to the source/drain of the gate structure is formed in the dielectric layer. A connecting line connected with the contact window is formed on the layer. However, in the process of forming the contact window, the position of the contact window is often shifted due to process deviation. As a result, the contact window may be partially formed on the gap wall in the gate structure, which affects the electrical performance of the contact window. In addition, if the position of the contact window is too large, the contact window may contact the gate electrode and cause a short circuit.

In addition, in the above-mentioned manufacturing process, the gate electrode, the contact window and the connecting line are formed in different process steps, so different masks need to be used to define the gate electrode, the contact window and the connecting line respectively. As a result, the above-mentioned problem of the positional deviation of the contact window cannot be effectively solved, and the manufacturing process cannot be simplified.

The present invention provides a semiconductor structure in which gates, contact windows and connections are formed in the same process steps.

The present invention provides a method for manufacturing a semiconductor structure, in which the gate, contact window and connection are formed in the same process step.

The semiconductor structure of the present invention includes an isolation structure, a lightly doped region, a gate electrode, a gate dielectric layer, a heavily doped region, a dielectric layer, a first contact window, a second contact window, and connecting lines. The isolation structure is arranged in the substrate to define an active area. The lightly doped region is disposed in the substrate in the active region. The gate is disposed in the substrate in the active region, and the bottom surface of the gate is lower than the bottom surface of the lightly doped region. The gate dielectric layer is disposed between the gate electrode and the substrate. The heavily doped region is arranged in the lightly doped region and located on opposite sides of the gate electrode. The dielectric layer is disposed on the substrate. The first contact window is disposed in the dielectric layer and connected to the gate electrode. The second contact window is disposed in the dielectric layer and connected to the heavily doped region. The connecting line is arranged in the dielectric layer and the isolation structure below it.

In an embodiment of the semiconductor structure of the present invention, the gate electrode, the first contact window, the second contact window, and the connecting line each include a polysilicon layer and a metal layer on the polysilicon layer.

In an embodiment of the semiconductor structure of the present invention, the gate electrode, the first contact window, the second contact window, and the connecting line each include a metal layer.

In an embodiment of the semiconductor structure of the present invention, there is a first distance between the second contact window located on one side of the gate and the gate, and all located on the other side of the gate There is a second distance between the second contact window and the gate, and the first distance is equal to the second distance.

In an embodiment of the semiconductor structure of the present invention, it further includes a pad layer disposed between the dielectric layer and the lightly doped region.

The manufacturing method of the semiconductor structure of the present invention includes the following steps: forming an isolation structure in a substrate to define an active region; forming a lightly doped region in the substrate in the active region; forming a dielectric on the substrate Layer; a first trench and a second trench are formed in the dielectric layer and a third trench is simultaneously formed in the dielectric layer and the isolation structure, wherein the second trench is located in the first Opposite sides of a trench, and the first trench and the second trench expose part of the substrate; a part of the substrate exposed by the first trench is removed to form a fourth A trench, wherein the bottom surface of the fourth trench is lower than the bottom surface of the lightly doped region; a gate dielectric layer is formed on the surface of the substrate exposed by the fourth trench; in the second trench A heavily doped region is formed in the substrate below the trench; a conductive layer is formed in the first trench, the second trench, the third trench, and the fourth trench.

In an embodiment of the method of manufacturing a semiconductor structure of the present invention, the second trench located on one side of the first trench has a first distance between the first trench, and is located at the first trench. There is a second distance between the second groove on the other side of a groove and the first groove, and the first distance is equal to the second distance.

In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the fourth trench includes the following steps: forming a protective layer on the dielectric layer, wherein the protective layer fills the second The trench and the third trench are exposed, and the first trench is exposed; an anisotropic etching process is performed using the protective layer as an etching mask to remove the exposed portion of the first trench Part of the substrate.

In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the conductive layer includes the following steps: in the first trench, the second trench, the third trench, and the A polysilicon layer is formed on the sidewall and bottom of the fourth trench; a metal layer is formed on the polysilicon layer.

In an embodiment of the manufacturing method of the semiconductor structure of the present invention, after forming the lightly doped region and before forming the dielectric layer, it further includes forming a pad layer on the substrate.

Based on the above, in the present invention, only one photomask can be used to simultaneously form the trenches defining the gate position, contact window position, and connection line position. Therefore, the manufacturing process is relatively simple, the cost is reduced, and the gate can be effectively avoided. It overlaps with the contact window and causes a short circuit. In addition, by defining the position of the contact window in this way, the contact window can be formed at an accurate position without additional alignment.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The following examples are listed in conjunction with the accompanying drawings for detailed description, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. To facilitate understanding, the same elements will be described with the same symbols in the following description.

The terms "include", "include", "have", etc. mentioned in the text are all open terms, which means "including but not limited to".

In addition, the directional terms such as "上" and "下" mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention.

When the terms "first", "second", etc. are used to describe elements, they are only used to distinguish these elements from each other, and do not limit the order or importance of these elements. Therefore, in some cases, the first element can also be referred to as the second element, and the second element can also be referred to as the first element, and this does not deviate from the scope of the patent application.

In the following embodiments, the numbers and shapes mentioned are only used to illustrate the present invention in detail to facilitate understanding of the content, but not to limit the present invention.

1A to 1E are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate or a silicon-on-insulator (SOI) substrate. In addition, a P-type well area and/or an N-type well area (not shown) may be formed in the substrate 100 according to actual needs. Then, an isolation structure 102 is formed in the substrate 100 to define the active region 100a. The active region 100a is a region for forming various semiconductor devices (such as logic devices, memory devices, etc.). The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. The formation method of the isolation structure 102 is well known to those skilled in the art, and will not be repeated here.

Then, a lightly doped region 104 is formed in the substrate 100 in the active region 100a. The lightly doped region 104 is adjacent to the surface of the substrate 100. The method for forming the lightly doped region 104 is, for example, an ion implantation process to implant dopants into the substrate 100. The lightly doped region 104 may be a P-type doped region or an N-type doped region, which is not limited in the present invention. Next, a cushion layer 106 is selectively formed on the substrate 100 in the active region 100a. In this embodiment, the pad layer 106 is, for example, a silicon oxide layer, and its formation method is, for example, a thermal oxidation process or a chemical vapor deposition process. Then, a hard mask layer 108 is selectively formed on the cushion layer 106. In this embodiment, the hard mask layer 108 is, for example, a silicon nitride layer, and its formation method is, for example, a chemical vapor deposition process. In this embodiment, after the cushion layer 106 and the hard mask layer 108 are formed, the top surface of the hard mask layer 108 is lower than the top surface of the isolation structure 102, but the invention is not limited thereto. In other embodiments, the top surface of the hard mask layer 108 and the top surface of the isolation structure 102 may also be coplanar, or the top surface of the hard mask layer 108 may also be higher than the top surface of the isolation structure 102. After that, a dielectric layer 110 is formed on the substrate 100. In this embodiment, the dielectric layer 110 is, for example, a silicon oxide layer, and its formation method is, for example, a chemical vapor deposition process. Then, the dielectric layer 110 can be selectively planarized. The planarization process is, for example, a chemical mechanical polishing (CMP) process.

Then, referring to FIG. 1B, a first trench 112 and a second trench 114 are formed in the dielectric layer 110 and the hard mask layer 108, and a third trench 116 is formed in the dielectric layer 110 and the isolation structure 102 at the same time. In this embodiment, the second trench 114 is located on opposite sides of the first trench 112, and the first trench 112 and the second trench 114 expose a part of the cushion layer 106. When the pad layer 106 is not formed, the first trench 112 and the second trench 114 expose a part of the substrate 100 (the lightly doped region 104). The first trench 112 is used to define the position where the gate is subsequently formed, the second trench 114 is used to define the position where the contact window is subsequently formed, and the third trench 116 is used to define the position where the connection line is subsequently formed. In this embodiment, the first trench 112, the second trench 114, and the third trench 116 are formed by forming a patterned photoresist layer (not shown) on the dielectric layer 110, for example. Then, using the patterned photoresist layer as an etching mask, an anisotropic etching process is performed to remove part of the dielectric layer 110 and the hard mask layer 108 underneath, and remove part of the dielectric layer 110 and the underneath The structure 102 is partially isolated, and the pad layer 106 is used as an etch stop layer. After that, the patterned photoresist layer is removed.

In this embodiment, only one patterning process (that is, only one photomask is used) can simultaneously form the first groove 112 and the second groove 114 respectively defining the gate position, the contact window position, and the connecting line position. With the third trench 116, the process steps are simplified and the cost is reduced, and the gate position and the contact window position can be ensured not to overlap, so as to avoid a short circuit between the contact window and the gate electrode. In addition, by defining the position of the contact window in this way, the contact window can be formed at an accurate position without additional alignment.

In addition, in this embodiment, the positions of the first groove 112, the second groove 114, and the third groove 116 formed can be adjusted by adjusting the mask pattern. For example, in this embodiment, the distance between the first trench 112 and the second trench 114 on one side can be equal to the distance between the first trench 112 and the second trench 114 on the other side. . In this way, the distance between the gate electrode to be formed later and the contact windows located on both sides of the gate electrode will be equal, so that a semiconductor device with a symmetric structure can be easily formed. In other embodiments, the distance between the first groove 112 and the second groove 114 on one side may not be equal to the distance between the first groove 112 and the second groove 114 on the other side according to actual needs. , To form a semiconductor element with an asymmetric structure.

Next, referring to FIG. 1C, a protective layer 118 is formed on the dielectric layer 110 so that the protective layer 118 fills the second trench 114 and the third trench 116 and exposes the first trench 112. In this embodiment, the protective layer 118 is, for example, a photoresist layer. Then, using the protective layer 118 as an etching mask, an anisotropic etching process is performed to remove a part of the substrate 100 exposed by the first trench 112 to form the fourth trench 120. The fourth trench 120 is a region where the gate electrode is subsequently formed. In this embodiment, the bottom surface of the fourth trench 120 is lower than the bottom surface of the lightly doped region 104. In this way, when a gate is subsequently formed in the fourth trench 120, the lightly doped regions 104 located on opposite sides of the gate can serve as a lightly doped drain (LDD).

Then, referring to FIG. 1D, the protective layer 118 is removed. At this time, the first trench 112 communicates with the fourth trench 120 and exposes a part of the substrate 100, the second trench 114 exposes a part of the lightly doped region 104, and the third trench 116 exposes a part of the isolation structure 102, and The depths of the first trench 112 and the second trench 114 and the third trench 116 are the same. Next, a gate dielectric layer 121 is formed on the surface of the substrate 100 exposed by the fourth trench 120. In this embodiment, the gate dielectric layer 121 is, for example, a silicon oxide layer, and its formation method is, for example, a thermal oxidation method. In addition, when the gate dielectric layer 121 is formed, a silicon oxide layer is also formed on the lightly doped region 104 exposed by the second trench 114. Therefore, a protective layer 122 is formed in the first trench 112 and the fourth trench 120, and then an etching process is performed to remove the silicon oxide layer on the lightly doped region 104. In this embodiment, the protective layer 122 is, for example, a photoresist layer.

After that, referring to FIG. 1E, the protective layer 122 is removed. Next, a polysilicon layer 123 is formed on the sidewalls and bottoms of the first trench 112, the second trench 114, the third trench 116, and the fourth trench 120. The formation method of the polysilicon layer 123 is, for example, a chemical vapor deposition process to form a polysilicon layer conformally on the substrate 100, and then a chemical mechanical polishing process is performed to remove the polysilicon layer on the top surface of the dielectric layer 110. In addition, before performing the chemical mechanical polishing process, a protective layer may be formed in the first trench and 112, the second trench 114, the third trench 116, and the fourth trench 120 to avoid being located in the first trench. The polysilicon layers in the AND 112, the second trench 114, the third trench 116, and the fourth trench 120 are damaged during the chemical mechanical polishing process, and the protective layer is removed after the chemical mechanical polishing process is completed.

After the polysilicon layer 123 is formed, a heavily doped region 124 is formed in the substrate 100 under the second trench 114. The heavily doped region 124 is located in the lightly doped region 104 and has the same conductivity type (N type or P type) as the lightly doped region 104. The method for forming the heavily doped region 124 is, for example, an ion implantation process. Then, a metal layer 126 is formed in the first trench 112, the second trench 114, the third trench 116, and the fourth trench 120, and the metal layer 126 fills the first trench 112, the second trench 114, The third trench 116 and the fourth trench 120. The method for forming the metal layer 126 is, for example, a chemical vapor deposition process to form a metal layer conformally on the dielectric layer 110 and fill the first trench 112, the second trench 114, the third trench 116, and the The four trenches 120 are then subjected to a chemical mechanical polishing process to remove the metal layer on the top surface of the dielectric layer 110. In this way, the semiconductor structure of this embodiment is completed. In this embodiment, the metal layer 126 is, for example, a tungsten layer, but the invention is not limited to this. In another embodiment, the metal layer 126 can also be replaced with a composite conductive layer composed of a titanium layer/titanium nitride layer/tungsten layer.

In the semiconductor structure of this embodiment, the polysilicon layer 123 and the metal layer 126 in the fourth trench 120 serve as the gate 128a, the heavily doped region 124 serves as the source/drain, and the polysilicon layer in the first trench 112 The layer 123 and the metal layer 126 serve as the first contact 128b connected to the gate 128a, and the polysilicon layer 123 and the metal layer 126 located in the second trench 114 serve as the second contact 128c connected to the source/drain, and The polysilicon layer 123 and the metal layer 126 located in the third trench 116 serve as a connecting line 128d.

In this embodiment, the distance between the gate electrode 128a and the second contact window 128c on one side is equal to the distance between the gate electrode 128a and the second contact window 128c on the other side. Therefore, the semiconductor structure of this embodiment may have a symmetrical structure, and the second contact window 128c will not contact the gate electrode 128a to cause a short circuit. In addition, the second contact window 128c can also be accurately connected with the source/drain to prevent the positional deviation from affecting the electrical performance of the semiconductor structure.

In this embodiment, the gate electrode 128a, the first contact window 128b, the second contact window 128c and the connecting line 128d are all composed of the polysilicon layer 123 and the metal layer 126, but the invention is not limited thereto. In other embodiments, the gate electrode 128a, the first contact window 128b, the second contact window 128c, and the connecting line 128d may also be composed of other conductive layers. For example, in one embodiment, in the step described in FIG. 1E, the step of forming the polysilicon layer 123 may be omitted, and after the heavily doped region 124 is formed, a conductive layer is formed to fill the first trench 112, The second trench 114, the third trench 116 and the fourth trench 120.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: base

100a: active area

102: Isolation structure

104: Lightly doped area

106: cushion

108: hard mask layer

110: Dielectric layer

112: The first groove

114: second groove

116: The Third Ditch

118, 122: protective layer

120: The fourth groove

121: gate dielectric layer

123: Polysilicon layer

124: heavily doped area

126: Metal layer

128a: gate

128b: first contact window

128c: second contact window

128d: connection line

1A to 1E are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to an embodiment of the invention.

100: base

100a: active area

102: Isolation structure

104: Lightly doped area

106: cushion

108: hard mask layer

110: Dielectric layer

112: The first groove

114: second groove

116: The Third Ditch

120: The fourth groove

121: gate dielectric layer

123: Polysilicon layer

124: heavily doped area

126: Metal layer

128a: gate

128b: first contact window

128c: second contact window

128d: connection line

Claims (10)

A semiconductor structure includes: an isolation structure arranged in a substrate to define an active area; a lightly doped area arranged in the substrate in the active area; a gate electrode arranged in the active area In the substrate, and the bottom surface of the gate is lower than the bottom surface of the lightly doped region; the gate dielectric layer is disposed between the gate and the substrate; the heavily doped region is disposed on the lightly doped region The miscellaneous region is located on opposite sides of the gate; a dielectric layer is disposed on the substrate; a first contact window is disposed in the dielectric layer and is connected to the gate, wherein The first contact window and the gate electrode are made of the same material and formed at the same time; a second contact window is provided in the dielectric layer and connected to the heavily doped region; and a connecting line is provided in the dielectric The electrical layer and the isolation structure underneath are isolated from the substrate by the isolation structure. The semiconductor structure according to claim 1, wherein the gate electrode, the first contact window, the second contact window, and the connecting line each include a polysilicon layer and a metal layer on the polysilicon layer . The semiconductor structure according to claim 1, wherein the gate electrode, the first contact window, the second contact window, and the connecting line each include a metal layer. The semiconductor structure according to claim 1, wherein there is a first distance between the second contact window located on one side of the gate electrode and the gate electrode, and is located on the other side of the gate electrode There is a second distance between the second contact window and the gate, and the first distance is equal to the second distance. The semiconductor structure described in item 1 of the scope of the patent application further includes a pad layer disposed between the dielectric layer and the lightly doped region. A method for manufacturing a semiconductor structure includes: forming an isolation structure in a substrate to define an active region; forming a lightly doped region in the substrate in the active region; forming a dielectric layer on the substrate; A first trench and a second trench are formed in the dielectric layer and a third trench is simultaneously formed in the dielectric layer and the isolation structure, wherein the second trench is located in the first trench And the first groove and the second groove expose part of the substrate; removing a part of the substrate exposed by the first groove to form a fourth groove, The bottom surface of the fourth trench is lower than the bottom surface of the lightly doped region; a gate dielectric layer is formed on the surface of the substrate exposed by the fourth trench; A heavily doped region is formed in the substrate; and a conductive layer is formed in the first trench, the second trench, the third trench, and the fourth trench. The method for manufacturing a semiconductor structure as described in the scope of the patent application, wherein the second trench located on one side of the first trench and the first trench There is a first distance between them, and there is a second distance between the second groove on the other side of the first groove and the first groove, and the first distance is equal to the second distance . According to the manufacturing method of the semiconductor structure described in claim 6, wherein the method for forming the fourth trench includes: forming a protective layer on the dielectric layer, wherein the protective layer fills the second A trench and the third trench, and the first trench is exposed; and an anisotropic etching process is performed using the protective layer as an etching mask to remove the first trench and expose Part of the substrate. According to the manufacturing method of the semiconductor structure described in claim 6, wherein the method of forming the conductive layer includes: in the first trench, the second trench, the third trench, and the A polysilicon layer is formed on the sidewall and bottom of the fourth trench; and a metal layer is formed on the polysilicon layer. According to the manufacturing method of the semiconductor structure described in the scope of the patent application, after forming the lightly doped region and before forming the dielectric layer, it further includes forming a cushion layer on the substrate.

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