CN1674292A - Non-volatile memory location and producing method thereof - Google Patents
Non-volatile memory location and producing method thereof Download PDFInfo
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- CN1674292A CN1674292A CN200410031215.6A CN200410031215A CN1674292A CN 1674292 A CN1674292 A CN 1674292A CN 200410031215 A CN200410031215 A CN 200410031215A CN 1674292 A CN1674292 A CN 1674292A
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- 238000000034 method Methods 0.000 title description 19
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 239000002131 composite material Substances 0.000 claims abstract description 46
- 210000000352 storage cell Anatomy 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 22
- 238000005516 engineering process Methods 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims 2
- 210000004027 cell Anatomy 0.000 description 32
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000012163 sequencing technique Methods 0.000 description 8
- 238000007667 floating Methods 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000005039 memory span Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
A non- volatile storage cell is composed of substrate, grid, the first source electrode / drain electrode area, composite dielectric layer and the second source electrode / drain electrode area. It is featured as setting a slot on substrate; placing grid in slot, the first source electrode / drain electrode area at slot bottom; setting composite dielectric layer between grid and slot surface and placing the second source electrode / drain electrode area in substrate at two side of grid.
Description
Technical field
The present invention relates to a kind of semiconductor memory component, and be particularly related to a kind of Nonvolatile storage unit (non-volatile memory cell) and manufacture method thereof.
Background technology
In various non-volatility memorizer products, has the actions such as depositing in, read, erase that to carry out repeatedly data, and can erasing and programmable read only memory (EEPROM) by electricity of the advantage that the data that deposit in also can not disappear after outage, become personal computer and electronic equipment a kind of memory element of extensively adopting.Typically can electricity erase and programmable read only memory is to make floating grid (floating gate) and control grid (control gate) with the polysilicon (polysilicon) that mixes.When memory carried out sequencing (program), the electronics that injects floating grid can be uniformly distributed among the whole polysilicon floating gate layer.Yet the tunnel oxide (tunneling oxide) below the polysilicon floating gate layer just causes the leakage current of element when defectiveness exists easily, influences the reliability of element.
Therefore, in order to solve the problem of the programmable read only memory element leakage current of can electric erasing, present method is to adopt a charge trap layer (charge trapping layer) to replace the polysilicon floating gate of existing memory, and the material of this charge trap layer for example is a silicon nitride.This silicon nitride charge trap layer respectively has one deck silica up and down usually, and form a kind of silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide that comprises, be called for short ONO) layer nesting structural embedded control (stacked structure) that is constituted, read-only memory with this stacked gate structure can be described as silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (silicon-oxide-nitride-oxide-silicon is called for short SONOS) memory element.
Fig. 1 illustrate is the generalized section of existing a kind of SONOS memory cell.Please refer to Fig. 1, composite dielectric layer 102, control grid 104, drain region 106a, source area 106b that the SONOS memory cell comprises substrate 100, is made of silica 102a/ silicon nitride 102b/ silica 102c.Wherein, silica 102a/ silicon nitride 102b/ silica 102c composite dielectric layer 102 and control grid 104 are disposed on the substrate 100 in regular turn, and form a stacked gate structure 108.In addition, channel region 110 is disposed in the substrate 100 of stacked gate structure 108 belows, and drain region 106a, source area 106b are disposed in the substrate 100 of stacked gate structure 108 both sides.
Yet along with integrated circuit just develops with the element of higher integrated level towards miniaturization, the size of above-mentioned SONOS memory cell can be reached by reducing to control the grid length mode.But, grid length diminishes and can shorten raceway groove 110 length (Channel Length) of oxide layer 102a below, so when this memory cell of sequencing, abnormal electrical perforation (Punch Through) just takes place between drain region and the source area easily, so will have a strong impact on the electrical property of this memory cell.And the channel width 104a of SONOS memory cell has very big influence to efficiency of storage; The size that is grid width 104a is dwindled, and makes its efficiency of storage be affected and variation.In addition, in the manufacture process of memory, lithography process also has the problem of so-called critical size, and limits dwindling of memory cell size.So will how under the trend of miniaturization of components, increase the coupling efficiency of SONOS memory cell, and then improve its efficiency of storage at present, will be one of emphasis of all circles' research.
In addition, because computer application software is huge gradually, therefore required memory span is also just more and more big, for this size decreases and memory span needs the situation that increases, the structure and the manufacture method that show existing SONOS memory cell must change to some extent, and be required to meet trend.Therefore, in the technology of deep-submicron, how in limited space, keep original memory capacity, even to strengthen original memory capacity also be the problem that the technology of memory component is concerned about.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of preparing non-volatile storage cell, produce Nonvolatile storage unit than effectively high coupling ratios with the development of co-operating member miniaturization.
A further object of the present invention provides a kind of Nonvolatile storage unit, effectively dwindling component size, and increases the element integrated level, and increases the coupling efficiency of Nonvolatile storage unit, and then improve its efficiency of storage.
The present invention proposes a kind of Nonvolatile storage unit, and this memory cell is made of substrate, grid, first source/drain regions, composite dielectric layer, second source/drain regions.Wherein, substrate has a groove; Grid is arranged in groove; First source/drain regions is positioned at channel bottom; Composite dielectric layer is between grid and flute surfaces, and composite dielectric layer comprises the charge trap layer at least; Second source/drain regions is arranged in the substrate of grid both sides.。
In above-mentioned Nonvolatile storage unit, composite dielectric layer is made of end dielectric layer, charge trap layer and top dielectric layer, and composite dielectric layer comprises the silicon oxide/silicon nitride/silicon oxide layer.
From the above, the composite dielectric layer of nonvolatile memory cell of the present invention (dielectric layer/charge trap layer/dielectric layer) is arranged in the groove of substrate with grid, and source/drain regions is arranged in the substrate at channel bottom and top, therefore the channel region of memory cell is to be arranged in the substrate of trenched side-wall (rectilinear channel region), can control channel length exactly by the degree of depth of control groove, and then the problem that is produced can avoid component size to dwindle the time, and can increase the element integrated level.
The invention provides a kind of preparing non-volatile storage cell, a substrate at first is provided.After in substrate, forming groove, form first source/drain regions in channel bottom.Then, form composite dielectric layer in groove, this composite dielectric layer comprises the charge trap layer at least.Afterwards, on composite dielectric layer, form grid, and in the substrate of grid both sides, form second source/drain regions.
The present invention is formed at composite dielectric layer and grid in the groove of substrate, and source/drain regions is arranged in the substrate at channel bottom and top, therefore the channel region of memory cell is to be formed in the substrate of trenched side-wall (rectilinear channel region), can control channel length exactly by the degree of depth of control groove, and then the problem that is produced can avoid component size to dwindle the time, and can increase the element integrated level.
And, because composite dielectric layer (dielectric layer/charge trap layer/dielectric layer) is formed in the groove of substrate with grid, similar two element parallel connections, so under same component size and live width, can increase its length of effective channel, and then the raising memory cell current, make " 0 " or the one state of its easier judgement memory cell.In addition, the technology of non-volatility memorizer of the present invention is simple, belongs to single-polysilicon technology (single poly process), and can match with CMOS (Complementary Metal Oxide Semiconductor) technology.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrate is the profile of existing silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon memory cell;
Fig. 2 A is the structure vertical view according to the Nonvolatile storage unit of the preferred embodiments of the present invention;
Fig. 2 B to Fig. 2 C is the section of structure according to a kind of Nonvolatile storage unit of the preferred embodiments of the present invention;
Fig. 3 is the electrical schematic diagram of Nonvolatile storage unit of the present invention;
Fig. 4 A and Fig. 4 B illustrate are the sequencing of Nonvolatile storage unit of the present invention/read schematic diagram;
Fig. 5 A to Fig. 5 F is the manufacturing process profile according to a kind of Nonvolatile storage unit of a preferred embodiment of the present invention;
Fig. 6 A to Fig. 6 D is the manufacturing process profile according to a kind of Nonvolatile storage unit of another preferred embodiment of the present invention.
Description of reference numerals
100,200,300 substrates 102,210,310,310a composite dielectric layer
102a, 102c oxide layer 102b nitration case
104,208,318 grid 104a grid widths
106a, 206,214,308,326 source/drain regions
108 stacked gate, 202,306 grooves
204,402 component isolation structure 210a, 312 top dielectric layers
210b, 314 charge trap layer 210c, 316 end dielectric layers
212,322 clearance wall 214a, 320 light doping sections
214b, 324 heavily doped regions, 216,328 inner layer dielectric layers
218,330 connectors, 220,332 leads
302 pad oxides, 304 mask layers
305 openings
Embodiment
Fig. 2 A illustrate is the vertical view of a kind of Nonvolatile storage unit of one embodiment of the present invention.Fig. 2 B illustrate is the generalized section of a kind of Nonvolatile storage unit of one embodiment of the present invention, and it is the generalized section of Fig. 2 A along A-A '.
Please be simultaneously with reference to Fig. 2 A and Fig. 2 B, this Nonvolatile storage unit comprises substrate 200, component isolation structure 204, source/drain regions 206, grid 208, composite dielectric layer 210, clearance wall 212, source/drain regions 214, inner layer dielectric layer 216, connector 218, lead 220.
Source/drain regions 206 for example is to be arranged at groove 202 bottoms.Grid 208 for example is to be arranged in groove 202, and it fills up groove 202 and outstanding substrate 200 surfaces, and grid 208 more extends on the groove 202 part substrate 200 outward.The material of grid 208 for example is a doped polycrystalline silicon.
Composite dielectric layer 210 for example is between grid 208 and groove 202 surfaces and between grid 208 and the substrate 200.Composite dielectric layer 210 comprises end dielectric layer 210a, charge trap layer 210b, top dielectric layer 210c at least.Wherein the material of end dielectric layer 210a for example is a silica, and it is as tunnel dielectric layer.The material of top dielectric layer 210c for example is a silica, and it is as the usefulness of isolated charge trap layer 210b and grid 208.Certainly the material of end dielectric layer 210a and top dielectric layer 210c also can be other dielectric material.The material of charge trap layer 210b for example is a silicon nitride, and certainly the material of charge trap layer 210b also can be that other has electric charge is absorbed in material wherein, as tantalum oxide, strontium titanates and hafnium oxide etc.
Inner layer dielectric layer 216 for example is to be positioned on the substrate 200.Lead 220 for example is to be positioned on the inner layer dielectric layer 216, and it is electrically connected source/drain regions 214 by connector 218.At this, lead 220 for example is as bit line, and grid 208 for example is as word line.
From the above, the composite dielectric layer of nonvolatile memory cell of the present invention (dielectric layer/charge trap layer/dielectric layer) is arranged in the groove 202 of substrate 200 with grid, and source/drain regions is arranged in the substrate at channel bottom and top, therefore the channel region of memory cell is to be arranged in the substrate of trenched side-wall (rectilinear channel region), can control channel length exactly by the degree of depth of control groove, and then the problem that is produced can avoid component size to dwindle the time, and can increase the element integrated level.
The grid 208 of Nonvolatile storage unit of the present invention is not limited to shown in Fig. 2 B.Grid 208 also can only fill up groove 202 and outstanding substrate 200 surfaces (shown in Fig. 2 C).Certainly, grid 208 also can only fill up groove, and not outstanding substrate 200 surfaces.
Fig. 3 illustrate is the electrical schematic diagram of Nonvolatile storage unit of the present invention.As shown in Figure 3, memory cell of the present invention can be considered the semiconductor element of two serial connections, share grid (word line WL), drain line (bit line BL) and source electrode line (SL), therefore can improve current density, and improve the efficient of the sequencing/erase operation for use of memory component.
The programming operations of Nonvolatile storage unit of the present invention below is described.Fig. 4 A and Fig. 4 B illustrate are the sequencing of Nonvolatile storage unit of the present invention/read schematic diagram.In Fig. 4 A and Fig. 4 B, member identical person with Fig. 2 B give identical label, and omit its explanation.
Please refer to Fig. 4 A, when memory cell is carried out sequencing, can apply a bias voltage Vgp to grid 208, source/drain regions 214 is applied a bias voltage Vup, source/drain regions 206 is floated, and deposits electronics in approaching the charge trap layer 210b of source/drain regions 214 sides.When memory cell is read, grid 208 is applied a bias voltage Vcc, source/drain regions 214 is applied a bias voltage Vur, source/drain regions 206 is floated, to read the data of source/drain regions 214 side positions.
Same, shown in Fig. 4 B, when memory cell is carried out sequencing, can apply a bias voltage Vgp to grid 208, source/drain regions 206 is applied a bias voltage Vdp, and source/drain regions 214 is floated, and deposits electronics in approaching the charge trap layer 210b of source/drain regions 206 sides.When memory cell is read, grid 208 is applied a bias voltage Vcc, source/drain regions 206 is applied a bias voltage Vdr, source/drain regions 214 is floated, to read the data of source/drain regions 206 side positions.And make memory cell of the present invention can become the non-volatility memorizer of two storages of a kind of single memory cell.
Non-volatility memorizer of the present invention is when sequencing, can make charge trap layer near source/drain side have electronics simultaneously, both one of them has electronics or neither has electronics, and form two bit architectures, therefore can under the situation that does not increase the memory cell volume, increase the figure place of storage data and can improve the element integrated level.
Below, preparing non-volatile storage cell of the present invention then is described.
Fig. 5 A to Fig. 5 F is the manufacturing process profile according to a kind of Nonvolatile storage unit of a preferred embodiment of the present invention.
Please refer to Fig. 5 A, a substrate 300 is provided earlier, be formed with component isolation structure in this substrate 300, to define active area.Then, form a pad oxide 302 (pad oxide) and one deck mask layer 304 (patterned mask layer) in regular turn on substrate 300, its material for example is silicon nitride or other suitable material.Subsequently, patterned mask layer 304 and pad oxide 302 are to form opening 305.
Please refer to Fig. 5 B, is mask with the mask layer 304 and the pad oxide 302 of patterning, removes the part substrate 300 that exposes, to form groove 306.The method that removes part substrate 300 comprises the dry-etching method, for example is the reactive ion etching method.
Then, form source/drain regions 308 in groove 306 bottoms.The formation method of this source/drain regions 308 for example is an ion implantation.Certainly, the formation method of source/drain regions 308 also can form one deck insulation doped layer (not shown) in groove 306 bottoms, and on the sidewall of groove 306, forming one deck cap layer (Cap Layer) (not shown).Then, substrate 100 is carried out a thermal process, make the diffusion of impurities in the doping insulating barrier enter formation source/drain regions 308 in groove 306 substrate of bottom portion 300.Then, remove the doping insulating barrier of groove 306 bottoms and the cap layer of groove 306 sidewalls.
Please refer to Fig. 5 C, remove mask layer 304 and pad oxide 302 after, form an end dielectric layers 312 in substrate 300 and groove 306 surfaces, its material comprises silica, and this end dielectric layer 312 for example utilizes a thermal oxidation technology to form.Afterwards, on end dielectric layer 312, form a charge trap layer (charge trapping layer) 314, its material is a silicon nitride for example, and this charge trap layer 314 is to utilize a chemical vapour deposition (CVD) (chemical vapor deposition for example, being called for short CVD) technology forms, and charge trap layer 314 can also be that other is as nitration case, tantalum oxide layer, strontium titanate layer or hafnium oxide layer etc.Subsequently, form a top dielectric layer 316 on charge trap layer 314, its material comprises silica.And dielectric layer of the aforesaid end 312, charge trap layer 314 and top dielectric layer 316 constitute composite dielectric layer 310.
Please refer to Fig. 5 D, form a conductive layer (not shown) on top dielectric layer 316, this conductive layer for example is to fill up groove 306, and the material of conductive layer for example doped polycrystalline silicon (polysilicon) or other suitable material.
Then, patterning conductive layer is to form a grid 318 on groove 306.And grid 318 can be selected to extend on the groove 306 part substrate 300 outward (as shown in this figure), or directly is formed on the groove 306.Then, remove the composite dielectric layer 310 do not covered by grid 318, remain then as composite dielectric layer 310a.Certainly, composite dielectric layer 310a is a silicon oxide/silicon nitride/silicon oxide layer stack structure, and the Nonvolatile storage unit with this stack architecture can be described as silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (silicon-oxide-nitride-oxide-silicon is called for short SONOS) memory cell.
Then, carry out a light dope technology (lightly doping process), in the substrate 300 in grid 318 outsides, to form light doping section (lightly doping region) 320.
Please refer to Fig. 5 E, form clearance wall 322 in grid 318 sidewalls, its material comprises insulating material, for example silicon nitride or other suitable material.Afterwards, carry out heavy doping technology, to form heavily doped region 324 in the substrate 300 outside the clearance wall 322 of grid 318 sidewalls.Wherein, light doping section 320 constitutes source/drain regions (source/drain region) 326 with heavily doped region 324.
Please refer to Fig. 5 F, on substrate 300, form one deck inner layer dielectric layer 328.The material of inner layer dielectric layer 328 for example is boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG), and the method that forms inner layer dielectric layer 328 for example is a chemical vapour deposition technique.Carry out a chemical mechanical milling tech then, make the flattening surface of inner layer dielectric layer 328.
Then, form the connector 330 that is electrically connected with source/drain regions 326 in inner layer dielectric layer 328, the material of connector 330 for example is the tungsten metal.The method that forms connector 330 for example is prior to forming the opening (not shown) that exposes contact hole source/drain regions 326 in the inner layer dielectric layer 328, inserting conductor material then to form it in opening.Afterwards, on inner layer dielectric layer 328, form the lead 332 that electrically connects with connector 330.The follow-up technology of finishing memory cell is that those skilled in that art are known, repeats no more inferior.
Fig. 6 A to Fig. 6 D is the manufacturing process profile according to a kind of Nonvolatile storage unit of another preferred embodiment of the present invention.In Fig. 6 A to Fig. 6 D, member gives identical label with the identical person of Fig. 5 A to Fig. 5 F, and omits its explanation.
Please refer to Fig. 5 A, a substrate 300 is provided earlier, be formed with one deck pad oxide 302 (pad oxide) and one deck mask layer 304 (patterned mask layer) of patterning on this substrate 300 in regular turn.In substrate 300, be formed with a groove 306.And be formed with source/drain regions 308 in groove 306 bottoms.
Please refer to Fig. 6 B, form conformal composite dielectric layer 310 on substrate 300, it comprises an end dielectric layer 312, a charge trap layer (charge trapping layer) 314 and one top dielectric layer 316.Then, form a conductive layer (not shown) on top dielectric layer 316, this conductive layer for example is to fill up groove 306.Then, remove groove 306 conductive layer and composite dielectric layer 310 in addition, up to exposing mask layer 304, to form grid 318.
Please refer to Fig. 6 C, remove mask layer 304 and pad oxide 302, the part composite dielectric layer 310 of grid 318 sidewalls on outstanding substrate 300 surfaces also can be removed simultaneously, and only stays the composite dielectric layer 310a that is arranged in groove 306.
Then, in the substrate 300 in grid 318 outsides, behind the formation light doping section 320, form clearance wall 322 in grid 318 sidewalls.Afterwards, form heavily doped region 324 in the substrate 300 outside the clearance wall 322 of grid 318 sidewalls.Wherein, light doping section 320 constitutes source/drain regions (source/drainregion) 326 with heavily doped region 324.
Please refer to Fig. 6 D, after forming one deck inner layer dielectric layer 328 on the substrate 300, in inner layer dielectric layer 328, form the connector 330 that electrically connects with source/drain regions 326.Afterwards, on inner layer dielectric layer 328, form the lead 332 that is electrically connected with connector 330.The follow-up technology of finishing memory cell is conventionally known to one of skill in the art, does not repeat them here.
Nonvolatile memory cell of the present invention is formed at composite dielectric layer (dielectric layer/charge trap layer/dielectric layer) and grid in the groove 306 of substrate 300, and source/drain regions is arranged in the substrate at channel bottom and top, therefore the channel region of memory cell is to be formed in the substrate of trenched side-wall (rectilinear channel region), can control channel length exactly by the degree of depth of control groove, and then the problem that is produced can avoid component size to dwindle the time, and can increase the element integrated level.
And, because the present invention is formed at composite dielectric layer (dielectric layer/charge trap layer/dielectric layer) and grid in the groove 306 of substrate 300, under same component size and live width, can increase its coupling efficiency, and then improve efficiency of storage.In addition, the technology of non-volatility memorizer of the present invention is simple, belongs to single-polysilicon technology (single poly process), and can match with CMOS (Complementary Metal Oxide Semiconductor) technology.
Though the present invention is open in conjunction with the preferred embodiments as above; so it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (17)
1. Nonvolatile storage unit comprises:
One substrate, this substrate has a groove;
One grid is arranged in this groove;
One first source/drain regions is positioned at this channel bottom;
One composite dielectric layer, between this grid and this flute surfaces, this composite dielectric layer comprises a charge trap layer at least; And
One second source/drain regions is arranged in this substrates of this grid both sides.
2. Nonvolatile storage unit as claimed in claim 1, wherein this grid fills up this groove.
3. Nonvolatile storage unit as claimed in claim 1, wherein this grid fills up this groove, and outstanding this substrate surface.
4. Nonvolatile storage unit as claimed in claim 1, wherein this grid also comprises on this substrate of part that extends outside this groove.
5. Nonvolatile storage unit as claimed in claim 4, wherein this composite dielectric layer also comprises between this grid and this substrate.
6. Nonvolatile storage unit as claimed in claim 1, wherein this composite dielectric layer comprises:
One bottom oxide is between this grid and this flute surfaces;
This charge trap layer is between this grid and this bottom oxide; And
One top oxide layer is between this grid and this charge trap layer.
7. Nonvolatile storage unit as claimed in claim 1 also comprises a clearance wall, is positioned at the sidewall of this grid.
8. Nonvolatile storage unit as claimed in claim 7 also comprises a lightly doped region, is arranged in this substrate of this clearance wall below.
9. Nonvolatile storage unit as claimed in claim 1, wherein the material of this grid comprises polysilicon.
10. Nonvolatile storage unit as claimed in claim 1, wherein this composite dielectric layer comprises the silicon oxide/silicon nitride/silicon oxide layer.
11. a preparing non-volatile storage cell comprises:
One substrate is provided;
In this substrate, form a groove;
Form one first source/drain regions in this channel bottom;
Form a composite dielectric layer in this groove, this composite dielectric layer comprises a charge trap layer at least;
On this composite dielectric layer, form a grid; And
In this substrate of these grid both sides, form one second source/drain regions.
12. preparing non-volatile storage cell as claimed in claim 11, the step that wherein forms this groove in this substrate comprises:
Form a mask layer on this substrate, this mask layer has an opening;
Remove this opening institute this substrate of exposed portions, in this substrate, to form this groove; And
After this channel bottom forms the step of this first source/drain regions and in this groove, form in regular turn and comprise before the step of this composite dielectric layer and remove this mask layer.
13. preparing non-volatile storage cell as claimed in claim 12 wherein forms this composite dielectric layer and comprises with the step that forms this grid on this composite dielectric layer in this groove:
Form a bottom oxide in this substrate and this flute surfaces;
On this bottom oxide, form this charge trap layer;
On this charge trap layer, form a top oxide layer;
On this top oxide layer, form a conductive layer;
This conductive layer of composition, to form this grid, this grid is arranged in this groove at least; And
Remove this grid this top oxide layer, this charge trap layer and this bottom oxide in addition.
14. preparing non-volatile storage cell as claimed in claim 13 wherein also is included in the step of this conductive layer of composition on outer this substrate of part of this groove and forms this grid.
15. preparing non-volatile storage cell as claimed in claim 12 wherein forms this composite dielectric layer and comprises with the step that forms this grid on this composite dielectric layer in this groove:
Deposit a bottom oxide, this charge trap layer and a top oxide layer in this mask layer and this flute surfaces, to form this composite dielectric layer;
Form a conductive layer on this composite dielectric layer, this conductive layer fills up this groove and this opening;
Remove this opening this conductive layer of part and this composite dielectric layer in addition; And
Remove this mask layer, to form this grid.
16. preparing non-volatile storage cell as claimed in claim 11 wherein forms before this groove in this substrate, also is included in to form an element isolation structure in this substrate, to define active area.
17. preparing non-volatile storage cell as claimed in claim 11 wherein forms in this substrate of these grid both sides in the step of this second source/drain regions, also comprises:
Carry out a light dope technology;
Form a clearance wall in this gate lateral wall; And
Carry out a heavy doping technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312156A CN100362664C (en) | 2004-03-26 | 2004-03-26 | Non-volatile memory location and producing method thereof |
Applications Claiming Priority (1)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100459074C (en) * | 2006-02-22 | 2009-02-04 | 南亚科技股份有限公司 | Semiconductor device with recess grid and its manufacturing method |
| CN100466293C (en) * | 2005-12-27 | 2009-03-04 | 东部电子股份有限公司 | Flash memory device and method of manufacturing the same |
| CN101840881B (en) * | 2009-03-16 | 2012-07-25 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit element |
| CN102800677A (en) * | 2012-01-12 | 2012-11-28 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Silicon) device unit |
| CN108831884A (en) * | 2018-06-08 | 2018-11-16 | 长鑫存储技术有限公司 | memory structure and preparation method thereof |
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| CN1407626A (en) * | 2001-09-06 | 2003-04-02 | 旺宏电子股份有限公司 | Vertical nitride read out-only memory unit |
| CN1240127C (en) * | 2001-11-21 | 2006-02-01 | 旺宏电子股份有限公司 | Method for mfg. vertical nitride read-only memory unit |
| US7411246B2 (en) * | 2002-04-01 | 2008-08-12 | Silicon Storage Technology, Inc. | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby |
| US6952034B2 (en) * | 2002-04-05 | 2005-10-04 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried source line and floating gate |
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| CN100466293C (en) * | 2005-12-27 | 2009-03-04 | 东部电子股份有限公司 | Flash memory device and method of manufacturing the same |
| CN100459074C (en) * | 2006-02-22 | 2009-02-04 | 南亚科技股份有限公司 | Semiconductor device with recess grid and its manufacturing method |
| CN101840881B (en) * | 2009-03-16 | 2012-07-25 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit element |
| CN102800677A (en) * | 2012-01-12 | 2012-11-28 | 上海华力微电子有限公司 | SONOS (Silicon Oxide Nitride Oxide Silicon) device unit |
| CN108831884A (en) * | 2018-06-08 | 2018-11-16 | 长鑫存储技术有限公司 | memory structure and preparation method thereof |
| TWI701789B (en) * | 2019-07-23 | 2020-08-11 | 力晶積成電子製造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112289861A (en) * | 2019-07-23 | 2021-01-29 | 力晶积成电子制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112289861B (en) * | 2019-07-23 | 2024-03-26 | 力晶积成电子制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN100362664C (en) | 2008-01-16 |
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