JP2008053275A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To introduce impurity ions into a high-concentration impurity area as well as into a polysilicon gate without causing fault due to the displacement of a mask, when forming a MOS transistor structure wherein a drain area is formed of a low-concentration impurity area and a high-concentration impurity area. <P>SOLUTION: A side wall oxide film 21 is formed in an n-channel transistor area, and it is adjacent to the side of an n-type polysilicon gate 19 on an n-type drain low-concentration impurity area 13, and its thickness is larger than that of a gate oxide film 17. It does not cover the upper surface of the n-type polysilicon gate 19, its upper surface is flat, and it is made of a silicon oxide film. The side wall oxide film 21 is also formed in a p-channel transistor area, it is adjacent to the side of a p-type polysilicon gate 33 on a p-type drain low-concentration impurity area 29, and its thickness is larger than that of the gate oxide film 17. It does not cover the upper surface of the p-type polysilicon gate 33, and its upper surface is flat and it is made of a silicon oxide film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a source region, a drain region, and a semiconductor layer between the source region and the drain region formed in the semiconductor layer in the element region surrounded by the element isolation insulating film with a space therebetween. A low-concentration impurity region having a channel region formed and a polysilicon gate formed on the channel region via a gate insulating film, and at least the drain region of the source region and the drain region is adjacent to the channel region. In addition, the present invention relates to a semiconductor device including a MOS transistor formed by a high-concentration impurity region formed adjacent to an end portion of a low-concentration impurity region opposite to a channel region, and a manufacturing method thereof.

  Unlike a MOS transistor formed on a bulk silicon substrate, a MOS transistor formed on an SOI (Silicon On Insulator) substrate is limited in the substrate depth direction by the buried oxide film of the SOI substrate. There is a feature that there are few. This feature has the advantage of operating even under high temperature conditions.

In order to create a high breakdown voltage device on an SOI substrate, particularly a thin film SOI of 1 μm (micrometer) or less, there is a method of increasing the breakdown voltage between the source and drain of a MOS transistor by forming a low concentration impurity region only on the drain region side. Yes (see Patent Document 1).
In this technique, a low-concentration impurity region is extended only on the drain region side of the MOS transistor and the region is depleted to improve the breakdown voltage between the source and drain of the MOS transistor.

FIG. 8 shows a cross-sectional view of a conventional N-channel MOS transistor.
The SOI substrate includes a support substrate 1, a buried oxide film 3, and an SOI layer 5 made of a silicon layer. A LOCOS (local oxidation of silicon) oxide film 7 for element isolation is formed on the SOI layer 5. An N-type source high-concentration impurity region 9 and an N-type drain high-concentration impurity region 11 are formed at an interval from each other in the SOI layer 5 in the element region surrounded by the LOCOS oxide film 7. The SOI layer 5 between the N-type source high-concentration impurity region 9 and the N-type drain high-concentration impurity region 11 is adjacent to the N-type drain high-concentration impurity region 11 and adjacent to the N-type source high-concentration impurity region 11 and the N-type drain high-concentration impurity region 11. An N-type drain low-concentration impurity region 13 having an N-type impurity concentration lower than that of the concentration impurity region 11 is formed. A P-type channel region 15 is formed in the SOI layer 5 between the N-type source high concentration impurity region 9 and the N-type drain low concentration impurity region 13. An N-type polysilicon gate 17 is formed on the P-type channel region 15 via a gate oxide film 17.
In this MOS transistor, the drain-source breakdown voltage can be increased by depleting the N-type drain low concentration impurity region 13 during operation.

When forming a structure having such a low concentration impurity region, a method using a sidewall oxide film in an LDD (lightly doped drain) structure is conceivable.
FIG. 9 shows a cross-sectional view of a conventional N-channel MOS transistor having an LDD structure. The LDD structure MOS transistor includes a sidewall oxide film 55 on the side surface of the N-type polysilicon gate 17, and an N-type low-concentration impurity region 57 in the SOI layer 5 below the sidewall oxide film 55.

According to the conventional manufacturing method of the LDD structure, the polysilicon gate 17 is formed, the polysilicon gate 17 is used as a mask, the impurity implantation for the low concentration impurity region is performed, and the silicon oxide film is formed by the CVD (chemical vapor deposition) method. After the film formation, the sidewall oxide film 55 is formed on the polysilicon gate 17 by performing etch back. Thereafter, N-type polysilicon gate 17, N-type source high-concentration impurity region 9, and N-type drain high-concentration impurity region are implanted by high-concentration impurity implantation into N-type source high-concentration impurity region 9 and N-type drain high-concentration impurity region 11. 11 is formed.
However, in the manufacturing method of the LDD structure, the length of the N-type low concentration impurity region 57 in the channel length direction is short, and the high breakdown voltage cannot be increased.

  Therefore, in general, in the conventional manufacturing method, an N-type drain low concentration impurity region 13 is formed as shown in FIG. 10A in order to form a structure having a low concentration impurity region as shown in FIG. After that, using the resist mask 59, the N-type drain low-concentration impurity region 13 is secured only on the drain region side, and high-concentration impurity implantation is performed on the source region and drain region formation regions. Here, in order to form the N-type polysilicon gate 17, the resist mask 59 must not cover the polysilicon gate 17.

In the conventional manufacturing method, self-alignment cannot be used for impurity implantation into the polysilicon gate 17. Therefore, when the impurity implantation into the polysilicon gate 17 is performed, if the formation position of the resist mask 59 is shifted to the drain region side as shown in FIG. There is a problem in that high concentration impurity implantation is performed in the region 13 and the N type high concentration impurity region 61 is formed between the P type channel region 15 and the N type drain low concentration impurity region 13 and the breakdown voltage cannot be increased. .
Further, as shown in FIG. 10C, when the formation position of the resist mask 59 is shifted to the polysilicon gate 17 side, a region 63 where no impurity is implanted into the polysilicon gate 17 is generated by the alignment error. However, there is a problem that transistor characteristics vary.

  Such a problem, including the MOS transistor formed on the bulk silicon substrate, is opposite to the channel region in the low concentration impurity region in which at least the drain region of the source region and the drain region is formed adjacent to the channel region. When manufacturing a MOS transistor formed by a high-concentration impurity region formed adjacent to the end of the low-concentration impurity region on the side, polysilicon is introduced simultaneously with the introduction of impurity ions into the high-concentration impurity region using a resist mask It occurs when impurity ions are introduced into the gate.

Japanese Patent No. 3232343

  An object of the present invention is to introduce impurity ions into a high concentration impurity region and impurity ions into a polysilicon gate when forming a MOS transistor structure in which at least a drain region is formed of a low concentration impurity region and a high concentration impurity region. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can be introduced without causing problems caused by mask displacement.

  A semiconductor device according to the present invention includes a source region, a drain region, and a channel region formed in a semiconductor layer between the source region and the drain region, which are formed in a semiconductor layer in an element region surrounded by an element isolation insulating film. A low-concentration impurity region having a polysilicon gate formed on the channel region with a gate insulating film interposed between the source region and the drain region, at least the drain region being adjacent to the channel region; Is a semiconductor device including a MOS transistor formed by a high concentration impurity region formed adjacent to an end portion of a low concentration impurity region on the opposite side, at least on the drain region side with respect to the polysilicon gate On the semiconductor layer, adjacent to the side surface of the polysilicon gate, the gate insulating film is thicker than the gate insulating film. Does not cover the silicon gate top, and the top surface is provided with a side wall oxide film made of flat silicon oxide film, the low concentration impurity regions are those formed under the side wall oxide film.

A method of manufacturing a semiconductor device according to the present invention includes forming a source region, a drain region, and a semiconductor layer between the source region and the drain region formed in the semiconductor layer of the element region surrounded by the element isolation insulating film at intervals. A low-concentration impurity region in which at least a drain region of the source region and the drain region is formed adjacent to the channel region, and a polysilicon gate formed on the channel region via a gate insulating film, A method for manufacturing a semiconductor device including a MOS transistor formed by a high concentration impurity region formed adjacent to an end portion of a low concentration impurity region opposite to a channel region, the following steps (A) to (D) is included in that order.
(A) forming a polysilicon gate on the semiconductor layer in the element region via a gate insulating film;
(B) forming a low-concentration impurity region by introducing impurity ions into the semiconductor layer using the polysilicon gate as a mask;
(C) At least on the low-concentration impurity region on the drain region side with respect to the polysilicon gate, adjacent to the side surface of the polysilicon gate and thicker than the gate insulating film, and covering the upper surface of the polysilicon gate Forming a side wall oxide film made of a silicon oxide film having a flat top surface,
(D) Impurity ions are introduced into the low concentration impurity region by using the polysilicon gate and the sidewall oxide film as a mask to form a high concentration impurity region, and impurity ions are introduced into the polysilicon gate, and the high concentration Forming a drain region comprising the impurity region, the low concentration impurity region under the sidewall oxide film, and a source region comprising at least the high concentration impurity region;

In the manufacturing method of the present invention, in the step (C), a silicon oxide film is formed on the low-concentration impurity region and the polysilicon gate with a thickness greater than that of the polysilicon gate, and the silicon oxide film is formed on the silicon oxide film. An example of forming the sidewall oxide film by patterning the silicon oxide film after performing a planarization process by a CMP (chemical mechanical polishing) method can be given.
Furthermore, an example in which the planarization process is performed until the upper surface of the polysilicon gate is exposed can be given.

In the manufacturing method of the present invention, in the step (C), a silicon oxide film is formed on the low-concentration impurity region and the polysilicon gate, and an SOG film is further formed on the silicon oxide film. An example can be given in which the sidewall oxide film is formed by flattening the oxide film and the SOG film so that the total film thickness is larger than that of the polysilicon gate, and patterning the SOG film and the silicon oxide film.
Furthermore, an example in which an etchback process is performed on the SOG film and the silicon oxide film before patterning the SOG film and the silicon oxide film can be given.
Furthermore, an example in which the etch back process is performed until the upper surface of the polysilicon gate is exposed can be given.

In the semiconductor device of the present invention, in the semiconductor device including the MOS transistor in which at least the drain region of the source region and the drain region is formed by the low concentration impurity region and the high concentration impurity region, the drain region is at least with respect to the polysilicon gate. On the semiconductor layer on the side, a sidewall oxide film made of a silicon oxide film that is thicker than the gate insulating film thickness adjacent to the side surface of the polysilicon gate, does not cover the upper surface of the polysilicon gate, and has a flat upper surface, The low concentration impurity region is formed under the sidewall oxide film,
According to the manufacturing method of the present invention, in a manufacturing method of a semiconductor device including a MOS transistor in which at least a drain region of a source region and a drain region is formed by a low concentration impurity region and a high concentration impurity region, Forming a polysilicon gate through the gate insulating film (A), forming a low concentration impurity region in the semiconductor layer using the polysilicon gate as a mask (B), at least on the drain region side with respect to the polysilicon gate A sidewall oxide film made of a silicon oxide film that is thicker than the gate insulating film adjacent to the side surface of the polysilicon gate, does not cover the upper surface of the polysilicon gate, and has a flat upper surface is formed on the low concentration impurity region. Step (C), using the polysilicon gate and the sidewall oxide film as a mask, the impurity ions are formed in the low concentration impurity region. By performing introduction introducing impurity ions into the polysilicon gate to form the high-concentration impurity region, the step of forming the drain region and the source region (D) and to include in that order,
Impurity ions can be introduced into the polysilicon gate and the high concentration impurity region formation region by self-alignment using the sidewall oxide film as a mask. As a result, the introduction of impurity ions into the high concentration impurity region and the introduction of impurity ions into the polysilicon gate can be performed without causing problems due to mask displacement, and a MOS transistor with stable transistor characteristics can be created.

In the manufacturing method of the present invention, in the step (C), a silicon oxide film having a thickness larger than that of the polysilicon gate is formed on the low-concentration impurity region and the polysilicon gate, and the silicon oxide film is formed by CMP. An example of forming the sidewall oxide film by patterning the silicon oxide film after performing the planarization process can be given.
If a silicon oxide film for a sidewall oxide film remains on the polysilicon gate after the above planarization process, the sidewall oxide film is formed after patterning the silicon oxide film for the sidewall oxide film. A process of exposing the upper surface of the polysilicon gate by performing an etch-back process on the silicon oxide film is required.
Therefore, if the planarization process is performed until the upper surface of the polysilicon gate is exposed, the silicon oxide film for the sidewall oxide film remains on the polysilicon gate after the planarization process. In comparison, it is not necessary to perform the etch back process, and the number of manufacturing steps can be reduced.

In the manufacturing method of the present invention, in the step (C), a silicon oxide film is formed on the low-concentration impurity region and the polysilicon gate, and an SOG film is further formed on the silicon oxide film. An example can be given in which the sidewall oxide film is formed by flattening the oxide film and the SOG film so that the total film thickness is larger than that of the polysilicon gate, and patterning the SOG film and the silicon oxide film.
An example of performing an etch back process on the SOG film and the silicon oxide film before patterning the SOG film and the silicon oxide film can be given.
Here, when the silicon oxide film for the sidewall oxide film remains on the polysilicon gate after the etch back process, the silicon oxide film for the sidewall oxide film is patterned after the etch back process. Thereafter, a step of performing a second etch back process on the silicon oxide film for the sidewall oxide film to expose the upper surface of the polysilicon gate is required.
Therefore, if the etch back process is performed until the upper surface of the polysilicon gate is exposed, the silicon oxide film for the sidewall oxide film remains on the polysilicon gate after the etch back process is performed. In comparison, it is not necessary to perform the second etch-back process, and the number of manufacturing steps can be reduced.

  1A and 1B are diagrams illustrating an embodiment of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line A-A ′ in FIG. This embodiment includes an N channel type MOS transistor (hereinafter referred to as an N-ch transistor) and a P channel type MOS transistor (hereinafter referred to as a P-ch transistor) formed on an SOI substrate.

  The SOI substrate includes a support substrate 1, a buried oxide film 3 having a thickness of 300 nm, and an SOI layer (semiconductor layer) 5 made of silicon having a thickness of 400 nm. A LOCOS oxide film (element isolation insulating film) 7 for element isolation is formed on the SOI layer 5 to define an N-ch transistor region and a P-ch transistor region (element region).

In the N-ch transistor region, an N-type source high-concentration impurity region (N +) 9 and an N-type drain high-concentration impurity region (N +) 11 are formed in the SOI layer 5 with a space therebetween.
The SOI layer 5 between the N-type source high-concentration impurity region 9 and the N-type drain high-concentration impurity region 11 is adjacent to the N-type drain high-concentration impurity region 11 and is spaced from the N-type source high-concentration impurity region 9. An N-type drain low-concentration impurity region (N−) 13 having an N-type impurity concentration lower than that of the N-type source high-concentration impurity region 9 and the N-type drain high-concentration impurity region 11 is formed.

A P-type channel region (Pbody) 15 is formed adjacent to both the regions 9 and 13 in the SOI layer 5 between the N-type source high-concentration impurity region 9 and the N-type drain low-concentration impurity region 13.
An N-type polysilicon gate 19 is formed on a P-type channel region 15 between the N-type source high-concentration impurity region 9 and the N-type drain low-concentration impurity region 13 via a gate oxide film (gate insulating film) 17. Yes.

On the N-type drain low-concentration impurity region 13, adjacent to the side surface of the N-type polysilicon gate 19, thicker than the gate oxide film 17, does not cover the upper surface of the N-type polysilicon gate 19, and A sidewall oxide film 21 made of a silicon oxide film having a flat upper surface is formed.
A P-type body contact region 23 is formed in the SOI layer 5 adjacent to the P-type channel region 15 at a position different from the position where the N-type polysilicon gate 19 is formed.

In the P-ch transistor region, a P-type source high-concentration impurity region (P +) 25 and a P-type drain high-concentration impurity region (P +) 27 are formed in the SOI layer 5 at intervals.
The SOI layer 5 between the P-type source high-concentration impurity region 25 and the P-type drain high-concentration impurity region 27 is adjacent to the P-type drain high-concentration impurity region 27 and is spaced from the P-type source high-concentration impurity region 25. A P-type drain low-concentration impurity region (P−) 29 having a P-type impurity concentration lower than that of the P-type source high-concentration impurity region 25 and the P-type drain high-concentration impurity region 27 is formed.

An N-type channel region (Nbody) 31 is formed adjacent to both regions 25 and 29 in the SOI layer 5 between the P-type source high-concentration impurity region 25 and the P-type drain low-concentration impurity region 29.
A P-type polysilicon gate 33 is formed on the N-type channel region 31 between the P-type source high concentration impurity region 25 and the P-type drain low concentration impurity region 29 via the gate oxide film 17.

On the P-type drain low-concentration impurity region 29, adjacent to the side surface of the P-type polysilicon gate 33, thicker than the gate oxide film 17, does not cover the upper surface of the P-type polysilicon gate 33, and A sidewall oxide film 21 made of a silicon oxide film having a flat upper surface is formed.
An N-type body contact region 35 is formed in the SOI layer 5 adjacent to the N-type channel region 31 at a position different from the position where the P-type polysilicon gate 33 is formed.

  The N-type drain high concentration impurity region 11, the N-type drain high concentration impurity region 13, and the N-type body contact region 35 have the same impurity concentration. The P-type source high concentration impurity region 25, the P-type drain high concentration impurity region 27, and the P-type body contact region 23 have the same impurity concentration.

  An interlayer insulating film 37 (not shown in (A)) is formed on the N-ch transistor and the P-ch transistor. Interlayer insulating film 37 is formed on N-type source high-concentration impurity region 9, N-type drain high-concentration impurity region 11, N-type polysilicon gate 19, P-type body contact region 23, and P-type source high-concentration impurity region 25. On the upper side, contacts are formed on the P-type drain high-concentration impurity region 27, the P-type polysilicon gate 33, and the N-type body contact region 35.

In this embodiment, the N-ch transistor region is adjacent to the side surface of the N-type polysilicon gate 19 and is thicker than the gate oxide film 17 and does not cover the upper surface of the N-type polysilicon gate 19. Further, since the sidewall oxide film 21 made of a silicon oxide film having a flat upper surface is provided, the N-type source high-concentration impurity region 9 and the N-type drain high-concentration impurity region 11 are formed at the time of high-concentration impurity ion implantation. Ion implantation into the type polysilicon gate 19 can also be performed simultaneously by self-alignment.
Further, in the P-ch transistor region, adjacent to the side surface of the P-type polysilicon gate 33, it is thicker than the gate oxide film 17, does not cover the upper surface of the P-type polysilicon gate 33, and the upper surface is not covered. Since the sidewall oxide film 21 made of a flat silicon oxide film is provided, the P-type polysilicon is formed during the high-concentration impurity ion implantation when forming the P-type source high-concentration impurity region 25 and the P-type drain high-concentration impurity region 27. Ion implantation into the gate 33 can also be performed at the same time by self-alignment.
Thus, high-concentration impurities are implanted into the low-concentration impurity regions 13 and 29 and high-concentration impurity implantation into the polysilicon gates 19 and 33 due to the alignment error of the resist mask, which has been a problem of the prior art. Can be eliminated.

  2 to 4 are process cross-sectional views for explaining an embodiment of the manufacturing method. 2 to 4 correspond to the cross-sectional position of FIG. The numbers in parentheses in FIGS. 2 to 4 correspond to the following steps. This embodiment will be described with reference to FIGS.

(1) An SOI substrate is used in which a buried oxide film 3 having a thickness of 300 nm is formed on a support substrate 1 and an SOI layer 5 having a thickness of 400 nm is further formed thereon.

(2) The LOCOS oxide film 7 is formed by a general LOCOS method, and the SOI layer 5 is completely separated to define an N-ch transistor region and a P-ch transistor region. Here, a silicon oxide film (not shown) serving as a base film for the oxidation resistant film used in the LOCOS method was formed to a thickness of about 1000 nm by wet oxidation at 1000 ° C.

(3) In order to adjust the threshold voltage of the N-ch transistor, the N-type body contact region 35 of the N-ch transistor region and the P-ch transistor using a general photolithography technique and ion implantation technique ( 1A) is patterned, and the resist mask 39 is used as a mask, for example, boron as an N-ch transistor channel doping impurity is implanted with an energy of 80 keV and a dose of 8 × 10 ^11. Ions are implanted into the SOI layer 5 under the condition of cm ⁻² to form the N-type channel region 15 of the N-ch transistor.

(4) The resist mask 39 is removed. Using a general photoengraving technique and ion implantation technique, the resist mask 41 in which the P-type body contact region 23 (see FIG. 1A) of the P-ch transistor region and the N-ch transistor is opened is patterned. Then, using the resist mask 41 as a mask, for example, phosphorus is implanted as a channel dope impurity of the P-ch transistor, and ion implantation is performed under the conditions of an implantation energy of 100 keV and a dose of 1 × 10 ¹² cm ^−2. A channel region 31 is formed.

(5) The resist mask 41 is removed. After the gate oxide film 17 is formed by dry oxidation at 920 ° C. to a thickness of 40 nm, a non-doped polysilicon film 43 is formed to a thickness of about 350 nm by LP-CVD (low-pressure CVD).

(6) The resist mask 45 is patterned in the polysilicon gate formation region by photolithography. The polysilicon film 43 is patterned by a dry etching method in which HBr and HCl gas are mixed to form the polysilicon gate 19 in the N-ch transistor region and the polysilicon gate 33 in the P-ch transistor region.

(7) The resist mask 45 is removed. The resist mask 39 is patterned by photolithography using a photomask in which the N-ch transistor region and the body contact region of the P-ch transistor used in step (3) are opened. Ion implantation is performed using the polysilicon gate 19 and the resist mask 39 as a mask by ion implantation under the conditions of implantation energy of 70 keV and dose of 2.5 × 10 ¹³ cm ⁻² , for example, phosphorus. The N-type drain low concentration impurity region 13 is formed in the N-ch transistor region. At this time, phosphorus is also implanted into the polysilicon gate 19.

(8) The resist mask 39 is removed. The resist mask 41 is patterned by photolithography using a photomask in which the P-ch transistor region and the body contact region of the N-ch transistor used in the step (4) are opened. By using the polysilicon implantation 33 and the resist mask 41 as a mask, ion implantation is performed using, for example, boron, which is a P-type impurity, under the conditions of an implantation energy of 15 keV and a dose of 2 × 10 ¹³ cm ^−2. A P-type drain low concentration impurity region 29 is formed in the -ch transistor region. At this time, boron is also implanted into the polysilicon gate 33.

(9) The resist mask 41 is removed. For example, using a mixed gas of SiH ₄ and N ₂ O, the silicon oxide film 47 is formed by LP-CVD so as to have a film thickness of 700 nm under the condition where the film formation temperature is 800 ° C.

(10) The silicon oxide film 47 is planarized using the CMP method. At this time, the silicon oxide film 47 exists on the polysilicon gates 19 and 33.

(11) A resist mask that covers the regions where the N-type drain low-concentration impurity region 13 and the P-type drain low-concentration impurity region 29 remain on the silicon oxide film 47 and a part of the polysilicon gates 19 and 33 by photolithography. 49 is patterned. Etch back processing is performed under the conditions of anisotropic etching using a mixed gas of Ar / CHF ₃ / CF ₄ to form a silicon oxide film pattern 51.

(12) The resist mask 49 is removed. Again, etch back processing is performed on the silicon oxide film pattern 51 until the upper surfaces of the polysilicon gates 19 and 33 are exposed under conditions of anisotropic etching using a mixed gas of Ar / CHF ₃ / CF _4. Sidewall oxide film 21 is formed only on the side wall on the drain region side of silicon gates 19 and 33. Here, the LOCOS oxide film 7 is also etched, but in the figure, the LOCOS oxide film 7 is shown in a film thickness before the etch-back process.

(13) The resist mask 39 is patterned by photolithography using a photomask in which the N-ch transistor region and the body contact region of the P-ch transistor used in steps (3) and (7) are opened. Using the ion implantation technique, the polysilicon gate 19 and the resist mask 39 are used as a mask, and N-type impurities such as arsenic (As) are implanted under the conditions of an implantation energy of 50 keV and a dose of 6 × 10 ¹⁵ cm ^−2. Then, an N-type source high concentration impurity region 9 and an N-type drain high concentration impurity region 11 of the N-ch transistor and an N-type body contact region 35 (see FIG. 1A) of the P-ch transistor are formed. At this time, arsenic is also implanted into the polysilicon gate 19 to form an N-type polysilicon gate.

(14) The resist mask 39 is removed. The resist mask 41 is patterned by photolithography using a photomask in which the P-ch transistor region and the body contact region of the N-ch transistor used in the steps (4) and (8) are opened. With the ion implantation technique, the polysilicon gate 33 and the resist mask 41 are used as a mask. For example, boron difluoride (BF ₂ ), which is a P-type impurity 32, is implanted at an energy of 50 keV and a dose of × 10 ¹⁵ cm ⁻² . Are implanted, and the P-type source high concentration impurity region 25 and the P-type drain high concentration impurity region 27 of the P-ch transistor and the P-type body contact region 23 of the N-ch transistor (see FIG. 1A). Form. At this time, boron difluoride is also implanted into the polysilicon gate 33 to form a P-type polysilicon gate.

(15) Thereafter, an interlayer insulating film 37 made of a CVD oxide film is formed to a film thickness of about 800 nm by a general method for manufacturing a semiconductor device, and subjected to a reflow process at a temperature condition of 920 ° C., for example. A transistor is completed by forming a hole and forming a wiring pattern made of a metal material such as aluminum (see FIG. 1).

  In this embodiment of the manufacturing method, as described in the above step (13), impurity ions are introduced into the formation region of the N-type polysilicon gate 19 and the high-concentration impurity regions 9 and 11 using the sidewall oxide film 21 as a mask. It can be done by self-alignment. Further, as described in the above step (14), impurity ions can be introduced into the formation region of the P-type polysilicon gate 33 and the high-concentration impurity regions 25 and 27 by self-alignment using the sidewall oxide film 21 as a mask. it can. Thereby, the introduction of impurity ions into the high concentration impurity regions 9 and 11 and the introduction of impurity ions into the polysilicon gate 19, and the introduction of impurity ions into the high concentration impurity regions 25 and 27 and impurity ions into the polysilicon gate 33. Can be introduced without causing a problem due to mask displacement, and a MOS transistor having stable transistor characteristics can be produced.

  FIG. 5 is a part of a process cross-sectional view for explaining another embodiment of the manufacturing method. This embodiment is different only in the step (10) of the above embodiment of the manufacturing method described with reference to FIGS. Therefore, description of steps (1) to (9) and (11) to (15) is omitted, and only step (10) is described.

(10) After the SOG film 53 is formed on the silicon oxide film 47 formed in the step (9) by spin coating, baking is performed to flatten the SOG film 53 (see FIG. 5).
Thereafter, the same steps as the above steps (11) to (15) are performed to form a transistor.

  In this embodiment of the manufacturing method, as in the above-described embodiment of the manufacturing method described with reference to FIGS. 1 to 4, impurity ions are introduced into the high-concentration impurity regions 9 and 11 and impurity ions are introduced into the polysilicon gate 19. And the introduction of impurity ions into the high-concentration impurity regions 25 and 27 and the introduction of impurity ions into the polysilicon gate 33 can be carried out without causing problems due to mask misalignment, resulting in stable transistor characteristics. MOS transistors can be created.

  FIG. 6 is a part of a process sectional view for explaining still another embodiment of the manufacturing method. Also in this embodiment, only the step (10) of the above embodiment of the manufacturing method described with reference to FIGS. 1 to 4 is different. Description of steps (1) to (9) and (11) to (15) is omitted, and only step (10) is described.

(10-1) After the SOG film 53 is formed on the silicon oxide film 47 formed in the step (9) by spin coating, baking is performed to flatten the SOG film 53 (FIG. 5 ( 10-1)).

(10-2) An etch-back process is performed on the SOG film 53 and the silicon oxide film 47. At this time, the silicon oxide film 47 exists on the polysilicon gates 19 and 33. Here, the etch-back process is performed until the silicon oxide film 47 has a film thickness comparable to the film thickness of the silicon oxide film 47 after the CMP process in the step (10) described with reference to FIG. Was done.
Thereafter, the same steps as the above steps (11) to (15) are performed to form a transistor.

  In this embodiment of the manufacturing method, as in the above-described embodiment of the manufacturing method described with reference to FIGS. 1 to 4, impurity ions are introduced into the high-concentration impurity regions 9 and 11 and impurity ions are introduced into the polysilicon gate 19. And the introduction of impurity ions into the high-concentration impurity regions 25 and 27 and the introduction of impurity ions into the polysilicon gate 33 can be carried out without causing problems due to mask misalignment, resulting in stable transistor characteristics. MOS transistors can be created.

  In the embodiment of the above manufacturing method, when the silicon oxide film 47 is patterned to form the silicon oxide film pattern 51, the silicon oxide film 47 exists on the polysilicon gates 19 and 33. Alternatively, the silicon oxide film 47 may be formed until the upper surfaces of the polysilicon gates 19 and 33 are exposed.

  FIG. 7 is a part of a process cross-sectional view for explaining still another embodiment of the manufacturing method. In this embodiment, steps (10) to (12) of the above embodiment of the manufacturing method described with reference to FIGS. 1 to 4 are different. Description of steps (1) to (9) and (13) to (15) is omitted, and only steps (10) to (12) are described.

(10) The silicon oxide film 47 is planarized using the CMP method. A planarization process by CMP is performed until the upper surfaces of the polysilicon gates 19 and 33 are exposed. In this planarization process, the upper surfaces of the polysilicon gates 19 and 33 and the upper surface of the silicon oxide film 47 are the same, or the upper surface of the silicon oxide film 47 is higher than the upper surfaces of the polysilicon gates 19 and 33. This is done so that it is lower than the height.

(11) A resist mask that covers the regions where the N-type drain low-concentration impurity region 13 and the P-type drain low-concentration impurity region 29 remain on the silicon oxide film 47 and a part of the polysilicon gates 19 and 33 by photolithography. 49 is patterned. Using the resist mask 49 as a mask, the silicon oxide film 47 is etched back under the condition of anisotropic etching using, for example, a mixed gas of Ar / CHF ₃ / CF ₄ , and drains of the polysilicon gates 19 and 33 are formed. Sidewall oxide film 21 is formed only on the side wall on the region side. Here, the LOCOS oxide film 7 is also etched, but in the figure, the LOCOS oxide film 7 is shown in a film thickness before the etch-back process.

(12) By removing the resist mask 49, the formation of the sidewall oxide film 21 is completed.

  In this embodiment, since the silicon oxide film 47 is formed until the upper surfaces of the polysilicon gates 19 and 33 are exposed before the silicon oxide film 47 is patterned in the step (10), refer to FIG. Since it is not necessary to perform the etch back process again as in the above-described step (12), the number of manufacturing steps can be reduced. In the step (12) described with reference to FIG. 4 (12), the LOCOS oxide film 7 is etched by the etch back process again. In this embodiment, the etch back process is performed in the process (12). Since this is not performed, the LOCOS oxide film 7 can be left thick.

  In the embodiment described with reference to FIG. 6, in the step (10-2), the etch back process for the silicon oxide film 47 is performed so that the silicon oxide film 47 exists on the polysilicon gates 19 and 33. However, the etch-back process may be performed until the upper surfaces of the polysilicon gates 19 and 33 are exposed. As a result, it is not necessary to perform another oxide film etch-back process after patterning the silicon oxide film 47 to form the sidewall oxide film 21.

As mentioned above, although the Example of this invention was described, this invention is not limited to these, A dimension, a shape, material, arrangement | positioning, a manufacturing process condition, etc. are examples, This book described in the claim Various modifications are possible within the scope of the invention.
For example, although the sidewall oxide film 21 is formed only on the drain region side in the above embodiment, it may be formed on the source region side. In this case, a source low concentration impurity region is formed under the sidewall oxide film on the source region side.

In the above embodiment, the LOCOS oxide film 7 is used as the element isolation insulating film. However, the present invention is not limited to this, and STI (shallow trench isolation) may be used as the element isolation insulating film.
Moreover, although the SOI substrate is used in the above embodiment, the present invention is not limited to this, and the semiconductor layer may be a bulk silicon substrate or an epitaxial growth layer formed on the bulk silicon substrate.

The gate insulating film is not limited to the silicon oxide film, and may be made of another insulating material such as a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film.
In the above embodiment, the N-type drain high-concentration impurity region 11, the N-type drain high-concentration impurity region 13, and the N-type body contact region 35 have the same impurity concentration, and the P-type source high-concentration impurity region 25, P-type drain Although the high concentration impurity region 27 and the P-type body contact region 23 have the same impurity concentration, the present invention is not limited to this, and the body contact region, the source high concentration impurity region, and the drain high concentration impurity region have an impurity concentration. May be different.
In the embodiment of the manufacturing method, the same photomask is used in the steps (3), (7), and (13), and the same photomask is used in the steps (4), (8), and (14). However, the same photomask is not necessarily used.

1A and 1B are diagrams illustrating an example of a semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line A-A ′ in FIG. The beginning of process sectional drawing of one Example of a manufacturing method is shown. It is process sectional drawing of the continuation of the Example. It is process sectional drawing of the continuation of the Example. It is a part of process sectional drawing for demonstrating the other Example of the manufacturing method. It is a part of process sectional drawing for demonstrating other Example of a manufacturing method. It is a part of process sectional drawing for demonstrating other Example of a manufacturing method. It is sectional drawing of the conventional N channel type MOS transistor. It is sectional drawing of the other conventional N channel type MOS transistor. It is sectional drawing for demonstrating the malfunction of the conventional manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 3 Embedded oxide film 5 SOI layer (semiconductor layer)
7 LOCOS oxide film (element isolation oxide film)
9 N-type source high-concentration impurity region 11 N-type drain high-concentration impurity region 13 N-type drain low-concentration impurity region 15 P-type channel region 17 Gate oxide film (gate insulating film)
19 N type polysilicon gate 21 Side wall oxide film 25 P type source high concentration impurity region 27 P type drain high concentration impurity region 29 P type drain low concentration impurity region 31 N type channel region 33 P type polysilicon gate

Claims (7)

A source region and a drain region formed in a semiconductor layer in an element region surrounded by an element isolation insulating film, a channel region formed in a semiconductor layer between the source region and the drain region, and a gate insulation on the channel region A low-concentration impurity region having a polysilicon gate formed through a film, at least the drain region being adjacent to the channel region of the source region and the drain region, and a low-concentration impurity region opposite to the channel region In a semiconductor device including a MOS transistor formed by a high concentration impurity region formed adjacent to an end portion,
At least on the semiconductor layer on the drain region side with respect to the polysilicon gate, adjacent to the side surface of the polysilicon gate, thicker than the gate insulating film thickness, does not cover the upper surface of the polysilicon gate, and A semiconductor device comprising: a sidewall oxide film made of a flat silicon oxide film, wherein the low concentration impurity region is formed under the sidewall oxide film. A source region and a drain region formed in a semiconductor layer in an element region surrounded by an element isolation insulating film, a channel region formed in a semiconductor layer between the source region and the drain region, and a gate insulation on the channel region A low-concentration impurity region having a polysilicon gate formed through a film, at least the drain region being adjacent to the channel region of the source region and the drain region, and a low-concentration impurity region opposite to the channel region In a method of manufacturing a semiconductor device including a MOS transistor formed by a high concentration impurity region formed adjacent to an end portion,
A semiconductor device comprising the following steps (A) to (D) in that order.
(A) forming a polysilicon gate on the semiconductor layer in the element region via a gate insulating film;
(B) forming a low-concentration impurity region by introducing impurity ions into the semiconductor layer using the polysilicon gate as a mask;
(C) At least on the low-concentration impurity region on the drain region side with respect to the polysilicon gate, adjacent to the side surface of the polysilicon gate and thicker than the gate insulating film thickness, covering the upper surface of the polysilicon gate Forming a side wall oxide film made of a silicon oxide film having a flat top surface,
(D) Impurity ions are introduced into the low-concentration impurity region by using the polysilicon gate and the sidewall oxide film as a mask to form a high-concentration impurity region and impurity ions are introduced into the polysilicon gate, Forming a drain region comprising the impurity region, the low concentration impurity region under the sidewall oxide film, and a source region comprising at least the high concentration impurity region;   In the step (C), a silicon oxide film having a thickness larger than that of the polysilicon gate is formed on the low-concentration impurity region and the polysilicon gate, and a planarization process is performed on the silicon oxide film by a CMP method. 3. The manufacturing method according to claim 2, wherein after the application, the silicon oxide film is patterned to form the sidewall oxide film.   The manufacturing method according to claim 3, wherein the planarizing process is performed until an upper surface of the polysilicon gate is exposed.   In the step (C), a silicon oxide film is formed on the low-concentration impurity region and the polysilicon gate, an SOG film is further formed thereon, and a total film of the silicon oxide film and the SOG film is formed. 3. The manufacturing method according to claim 2, wherein the sidewall oxide film is formed by flattening so that the thickness is larger than that of the polysilicon gate, and patterning the SOG film and the silicon oxide film.   6. The manufacturing method according to claim 5, wherein an etchback process is performed on the SOG film and the silicon oxide film before patterning the SOG film and the silicon oxide film.   The manufacturing method according to claim 6, wherein the etch back process is performed until an upper surface of the polysilicon gate is exposed.

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