[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI587396B - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

Info

Publication number
TWI587396B
TWI587396B TW102106054A TW102106054A TWI587396B TW I587396 B TWI587396 B TW I587396B TW 102106054 A TW102106054 A TW 102106054A TW 102106054 A TW102106054 A TW 102106054A TW I587396 B TWI587396 B TW I587396B
Authority
TW
Taiwan
Prior art keywords
film
semiconductor device
insulating film
manufacturing
fluorine
Prior art date
Application number
TW102106054A
Other languages
English (en)
Other versions
TW201401375A (zh
Inventor
Takenao Nemoto
Takehisa Saito
Yugo Tomita
Hirokazu Matsumoto
Akihide SHIROTORI
Akinobu Teramoto
Xun Gu
Original Assignee
Zeon Corp
Univ Tohoku
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zeon Corp, Univ Tohoku filed Critical Zeon Corp
Publication of TW201401375A publication Critical patent/TW201401375A/zh
Application granted granted Critical
Publication of TWI587396B publication Critical patent/TWI587396B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置之製造方法及半導體裝置
本發明係關於一種半導體裝置之製造方法及半導體裝置。
傳統上，已知有以鑲嵌製程技術所形成的配線結構。例如，習知的多層配線結構中，在層間絕緣膜和作為配線材料的Cu(銅)之間，形成有防止Cu朝絕緣膜擴散用的阻隔層(障壁金屬)。前述配線結構中，由於在絕緣膜與Cu之間設置有具既定厚度的阻隔層，肯定會產生電阻(接觸電阻)增高的配線延遲問題。關於此問題，下述非專利文獻1及2中，揭露有不在絕緣膜與Cu之間設置阻隔層的配線結構。
非專利文獻1：M.Tada, Het al., 「Barrier-metal-free (BMF),Cu Dual-damascene Interconnects with Cu-epi-contacts buried in Anti-diffusive, Low-k Organic film」, 2001 VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on, IEEE, 12-14 June 2001, pp.13-14。
非專利文獻2：Marianna Pantouvaki et al., 「Advanced Organic Polymer for the Aggressive Scaling of Low-k Materials」, Japanese Journal of Applied Physics, 2011, Volume 50, Issue 4, pp.04DB01-04DB01-5。
近來，為對應半導體裝置之微細化、高速化的需求，需要有能實現此需求的低介電率化(low-k)之絕緣膜。於此，在上述非專利文獻1所記載之結構中，採用Divinylsiloxane-bis-benzocyclobutene(二乙烯基矽氧烷-雙-苯並環丁烯，k=2.6)之有機膜作為絕緣膜，從配線延遲之觀點而言，更加需要低介電常數材料。又，在該絕緣膜中，其特性上，在250℃以上之高溫中實施退火處理時，Cu恐有自絕緣膜剝離的問題。
又，在上述非專利文獻2所記載之結構中，由於Cu肯定會擴散至絕緣 膜，因此無法避免依時性介電質崩潰(TDDB、Time-dependent dielectric breakdown)的發生。因此，在非專利文獻2所記載之結構中，難以獲得可靠性高的半導體裝置。
本發明為解決上述問題，目的為提供一種可達成提高絕緣膜與配線組件之密著性及可靠性的半導體裝置之製造方法及半導體裝置。
本發明之一觀點係一種半導體裝置之製造方法，係於絕緣膜以鑲嵌法(damascene)形成配線，包含有：形成添加氟之碳膜以作為該絕緣膜的步驟；於該絕緣膜形成有對應該配線之溝部的步驟；以及於該溝部填充作為配線組件之銅的步驟。
在該半導體裝置之製造方法中，於添加氟之碳所組成之絕緣膜處形成溝部，並於該溝部填充埋入作為配線組件之銅(以下稱為Cu)。如此一來，在半導體裝置之製造方法中，透過使用添加氟之碳膜作為絕緣膜，即使是不在絕緣膜與Cu之間設置障壁金屬層而將Cu直接埋入的結構，亦可抑制Cu擴散至絕緣膜。藉此，半導體裝置之製造方法可抑制TDDB的發生，達成提高半導體裝置之可靠性。又，在半導體裝置之製造方法中，由於將添加氟之碳與Cu結合，故在以高溫實施退火處理時亦可抑制Cu自絕緣膜剝離。因此，半導體裝置之製造方法可達成提高絕緣膜與Cu之密著性。
於一實施形態中，更包含對形成有溝部之絕緣膜施以電漿處理，來將絕緣膜之表面側進行改質的步驟。如此一來，在半導體裝置之製造方法中，透過在絕緣膜之表面實施電漿處理並將表面側進行改質，便可提高作為添加氟之碳膜之絕緣膜與Cu的密著性。
於一實施形態中，絕緣膜之表面側的改質係使該表面側之氟含有率產生變化。在半導體裝置之製造方法中，例如，透過改質來使絕緣膜之表面側的氟含有率減少，來於絕緣膜之表面側形成富碳層(含碳比例較含氟比例高之層)。藉此，在半導體裝置之製造方法中，便可提高添加氟之碳與Cu之結合。其結果，在半導體裝置之製造方法中，可進一步提高作為添加氟之碳膜的絕緣膜與Cu之密著性。
於一實施形態中，絕緣膜之表面側的改質係由包含氮以作為活性種之電漿處理來進行。如此一來，在半導體裝置之製造方法中，透過氮化電漿 處理來進行絕緣膜處理，便可良好地進行絕緣膜之表面的改質。
於一實施形態中，電漿處理之處理時間為4秒~60秒。
於一實施形態中，更包含於溝部內面形成氧化膜的步驟；且亦可於形成有氧化膜之溝部處填充銅。藉此，在半導體裝置之製造方法中，可獲得降低配線電阻的半導體裝置。
於一實施形態中，於形成添加氟之碳膜成膜的步驟中，作為成膜裝置，係使用具備有：形成處理空間的處理容器；微波產生器；將微波產生器所產生之微波進行放射的天線；設置於處理空間與天線之間的介電體窗；供給電漿激發用氣體的氣體供給部；以及供給形成添加氟之碳膜用的材料氣體之材料氣體供給部的成膜裝置；從氣體供給部供給電漿激發用之氣體，從天線放射微波以激發電漿，從材料氣體供給部供給該料氣體，藉由電漿使材料氣體進行反應而形成添加氟之碳膜。在半導體裝置之製造方法中，藉由如此般地形成添加氟之碳膜，便可獲得緻密且與Cu之密著性較高、耐熱性較高的添加氟之碳膜。
本發明之一觀點為一種半導體裝置，係於絕緣膜以鑲嵌法形成配線，具備有：作為添加氟之碳膜的絕緣膜；以及設置於絕緣膜，由埋入對應配線之溝部的銅所組成的配線組件。
該半導體裝置中，係於添加氟之碳所組成之絕緣膜的溝部，埋入有作為配線組件的銅(以下稱為Cu)。如此一來，半導體裝置中，透過使用添加氟之碳作為絕緣膜，即使是不在絕緣膜與Cu之間設置障壁金屬層而將Cu直接埋入的結構，由於添加氟之碳膜本身的Cu阻隔功能優良，因此可抑制Cu擴散至絕緣膜。藉此，半導體裝置中，可抑制TDDB的發生，達成提高半導體裝置之可靠性。又，半導體裝置中，由於添加氟之碳會與Cu結合，在以高溫實施退火處理時亦可抑制Cu自絕緣膜剝離。因此，半導體裝置可達成提高絕緣膜與Cu之密著性。
於一實施形態中，與銅相連接之絕緣膜的表面(形成Cu之面)側係藉由電漿處理進行改質。透過前述結構，在半導體裝置中，可確保進一步提高銅與絕緣膜之密著性。
於一實施形態中，絕緣膜之表面側係進行改質以使氟含有率產生變 化。透過前述結構，在半導體裝置中，例如，透過改質來使絕緣膜之表面側的氟含有率減少，可進一步提高作為添加氟之碳膜(形成Cu之面側係具有富碳層之膜)的絕緣膜與Cu之密著性。
於一實施形態中，絕緣膜之表面側的改質係由包含氮以作為活性種之電漿處理來進行。
根據本發明之一觀點，可達成提高絕緣膜與配線組件之密著性及可靠性。
10‧‧‧電漿處理裝置
12‧‧‧處理容器
12a‧‧‧側壁
12b‧‧‧底部
12h‧‧‧排氣孔
14‧‧‧基台
14a‧‧‧台部
14b‧‧‧聚焦環
14c‧‧‧靜電夾具
14d‧‧‧電極
14e‧‧‧絕緣膜
14f‧‧‧絕緣膜
14g‧‧‧冷媒室
16‧‧‧介電體窗組件
16a‧‧‧貫穿孔
16d‧‧‧凹部
18‧‧‧天線
18a‧‧‧慢波板
18b‧‧‧平面天線
18Aa‧‧‧槽孔
18Ab‧‧‧槽孔
20‧‧‧同軸導波管
20a‧‧‧外側導體
20b‧‧‧內側導體
22‧‧‧注射器
24‧‧‧配管組件
28‧‧‧O型環
28a‧‧‧支撐部
29‧‧‧按壓環組件
30‧‧‧微波產生器
30a‧‧‧調諧器
32‧‧‧導波管
34‧‧‧模式轉換器
36‧‧‧冷卻套管
40‧‧‧氣體供給系統(氣體供給部)
40a‧‧‧流量控制器
40b‧‧‧開關閥
42‧‧‧氣體供給部(材料氣體供給部)
42a‧‧‧氣體管線
42b‧‧‧氣體噴射孔
44‧‧‧氣體供給系統
44a‧‧‧氣體管線
44b‧‧‧開關閥
44c‧‧‧流量控制器
46‧‧‧筒狀支撐部
48‧‧‧筒狀支撐部
50‧‧‧排氣路徑
52‧‧‧折流板
54‧‧‧排氣管
56‧‧‧排氣裝置
58‧‧‧高頻電源
60‧‧‧匹配單元
62‧‧‧給電棒
64‧‧‧直流電源
66‧‧‧開關
68‧‧‧包覆線
70‧‧‧配管
72‧‧‧配管
74‧‧‧氣體供給管
100‧‧‧半導體裝置
102‧‧‧SiO2膜
104‧‧‧半導體基板
106‧‧‧CF膜(絕緣膜)
108‧‧‧SiCN膜
110‧‧‧SiO2膜
112‧‧‧光阻
114‧‧‧銅(配線組件)
118‧‧‧氧化膜
200‧‧‧半導體裝置
C‧‧‧溝部
S‧‧‧處理空間
W‧‧‧被處理基體
P‧‧‧配線圖樣(配線)
圖1係顯示用於一實施形態之半導體裝置製造的電漿處理裝置之圖式。
圖2係顯示圖1所示之平面天線一例的平面圖。
圖3係顯示半導體裝置的結構剖面之圖式。
圖4係顯示半導體裝置之製造步驟的流程圖。
圖5係顯示半導體裝置之製造步驟的圖式。
圖6係顯示SIMS之分析結果的圖表。
圖7係顯示電阻特性的圖表。
圖8係顯示靜電容量特性的圖表。
圖9係顯示其它實施形態之半導體裝置的結構剖面之圖式。
圖10係顯示圖9所示之在CF膜與Cu之間設置氧化膜的半導體裝置之電阻特性的圖表。
圖11係顯示其它形態之半導體裝置的SIMS分析結果的圖表。
以下，參考圖式詳細說明各種實施形態。另外，各圖式中對於相同或相當之部分係賦予相同的參考元件符號。
首先，說明用於一實施形態之半導體裝置製造方法的一步驟之電漿處理裝置。圖1係顯示一實施形態之電漿處理裝置的示意剖面圖。
圖1所示之電漿處理裝置10，係具備：處理容器12、基台14、介電體窗組件16、天線18、同軸導波管20、注射器22、及配管組件24。
處理容器12係形成有對被處理基體W進行電漿處理用的處理空間S。處理容器12可包含：側壁12a、及底部12b。側壁12a係具有於軸線X方 向上延伸的略筒狀。底部12b係設置於側壁12a之下端側。底部12b處設置有排氣用之排氣孔12h。側壁12a之上端部則具有開口。
透過支撐亦被稱為介電體窗之介電體窗組件16的支撐部28a，可開關地且氣密性地關閉側壁12a之上端部開口。該介電體窗組件16與側壁12a上端部之間介設有O型環28，以保持處理容器12為密閉。
電漿處理裝置10更具備有微波產生器30。微波產生器30係產生例如頻率2.45GHz的微波。微波產生器30具有調諧器30a。微波產生器30係經由導波管32及模式轉換器34而連接至同軸導波管20之上部。
同軸導波管20之另一端係沿軸線X往介電體窗組件16下方延伸並連接至處理容器12之上部。同軸導波管20係包含外側導體20a及內側導體20b。外側導體20a係具有沿軸線X方向延伸的筒狀。介電體窗組件16之上部處配置有平面天線18b。將慢波板18a以覆蓋平面天線18b般進行配置，並將冷卻套管36以覆蓋慢波板18a般進行配置。內側導體20b之下端係連接至作為金屬製槽孔板的平面天線18b。介電體窗組件16、平面天線18b、慢波板18a及冷卻套管36係以按壓環組件29支撐外周緣部。平面天線18b係經由按壓環組件29及支撐部28a形成接地。
慢波板18a具有略圓盤狀。慢波板18a係由例如石英或氧化鋁等介電體所構成。慢波板18a被夾持於平面天線18b與冷卻套管36下側面之間。因此，天線18由慢波板18a、平面天線18b、及冷卻套管36下側面所構成。冷卻套管36係冷卻平面天線18b、慢波板18a、及按壓環組件29，以防止因電漿的熱導致變形破損。
平面天線18b為形成有複數個槽孔的略圓板狀之金屬板。於一實施形態中，平面天線18b亦可為輻射狀槽孔天線。圖2係顯示圖1所示之平面天線一例的平面圖。平面天線18b處形成有複數槽孔對18A。複數槽孔對18A係於徑向上以既定間隔進行設置，又，於圓周方向上以既定間隔進行配置。複數槽孔對18A的每一對係包含二個槽孔18Aa及18Ab。槽孔18Aa與槽孔18Ab係相互地於交叉或正交方向上進行延伸。微波產生器30所產生之微波會通過同軸導波管20而傳播至平面天線18b，經由慢波板18a呈放射狀進行傳播，而從槽孔對18A經由介電體窗組件16導入處理容器12 內。
介電體窗組件16具有略圓盤狀，例如，由石英或氧化鋁所構成。介電體窗組件16係於軸線X方向上面對基台14般進行設置，又，設置於平面天線18b正下方。介電體窗組件16係讓接收來自天線18之微波穿透並導入處理空間S內。藉此，於介電體窗組件16正下方產生電場，於處理空間S內產生電漿。如此一來，根據電漿處理裝置10，可不施加磁場而使用微波以產生電漿。
介電體窗組件16之下側面可劃分形成有凹部16d。凹部16d係繞軸線X而呈環狀般設置，並具有錐狀。該凹部16d係設置來用以促使藉由所導入之微波產生駐波，而有助於有效率地產生微波電漿。
電漿處理裝置10中，內側導體20b具有沿軸線X上延伸的筒狀。該內側導體20b之內部插入有配管組件24。配管組件24之一端係連接氣體供給系統40。氣體供給系統40係由稱為質流控制器的流量控制器40a及開關閥40b所構成。於一實施形態中，來自氣體供給系統40之處理氣體係經由配管組件24供給至注射器22。來自配管組件24之處理氣體係經由注射器22、及介電體窗組件16所形成的貫穿孔16a而供給至處理空間S。
又，電漿處理裝置10更具備其它氣體供給部42。氣體供給部42係包含氣體管線42a。氣體管線42a係於介電體窗組件16與基台14之間繞軸線X而呈環狀般延伸。氣體管線42a處設置有朝軸線X方向噴射氣體的複數個氣體噴射孔42b。該氣體供給部42係連接至氣體供給系統44。
氣體供給系統44係包含氣體管線44a、開關閥44b、及稱為質流控制器的流量控制器44c。氣體供給部42之氣體管線42a係經由流量控制器44c、開關閥44b、及氣體管線44a供給處理氣體。另外，氣體管線44a係貫穿處理容器12之側壁12a。氣體供給部42之氣體管線42a係經由該氣體管線44a支撐於側壁12a。
設置基台14，使得天線18與該基台14之間包夾形成處理空間S。該基台14上載置有被處理基體W。於一實施形態中，基台14係包含台部14a、聚焦環14b、及靜電夾具14c。
台部14a係支撐於筒狀支撐部46。筒狀支撐部46係以絕緣性材料所構 成，自底部12b垂直朝上延伸。又，筒狀支撐部46之外周緣係設置有導電性筒狀支撐部48。筒狀支撐部48係沿筒狀支撐部46外周緣並自處理容器12之底部12b垂直朝上延伸。該筒狀支撐部46與側壁12a之間形成有環狀之排氣路徑50。
排氣路徑50之上部安裝有設置複數個貫穿孔之環狀折流板52。成膜裝置之情況中亦可不設置折流板。排氣孔12h之下部係經由排氣管54連接至排氣裝置56。排氣裝置56具有渦輪分子幫浦等真空幫浦。透過排氣裝置56，可使處理容器12內之處理空間S均勻地減壓至期望真空度。
台部14a亦可作為高頻電極。台部14a係經由匹配單元60及給電棒62電性連接有RF偏壓用之高頻電源58。高頻電源58係將適合用以控制吸引至被處理基體W之離子能量的特定頻率，例如以特定功率輸出13.65MHz之高頻電力。較佳地為400kHz至60MHz之間。匹配單元60收納有對高頻電源58側之阻抗，與主要為電極、電漿、處理容器12等負載側阻抗之間進行整合用的匹配器。該匹配器中包含有自偏壓生成用之阻隔電容器。
台部14a之上側面設置有靜電夾具14c。靜電夾具14c係以靜電吸附力保持被處理基體W。靜電夾具14c之徑向外側設置有環狀般環繞被處理基體W周圍的聚焦環14b。靜電夾具14c包含電極14d、絕緣膜14e、及絕緣膜14f。電極14d係由導電膜所構成，並設置於絕緣膜14e與絕緣膜14f之間。電極14d係經由開關66及包覆線68電性連接有高壓直流電源64。藉由直流電源64所施加之直流電壓以產生庫侖力，使得靜電夾具14c可吸附保持被處理基體W。
台部14a之內部設置有於圓周方向上延伸的環狀冷媒室14g。於該冷媒室14g，係透過冷卻器單元(未圖示)經由配管70、72而循環供給有既定溫度之冷媒，例如，冷卻水。藉由冷媒之溫度，經由氣體供給管74將靜電夾具14c之導熱氣體，例如，He氣體供給至靜電夾具14c上側面與被處理基體W內面之間。
其次，說明使用上述電漿處理裝置10所製造之半導體裝置。圖3係顯示一實施形態之半導體裝置的結構剖面的圖式。如圖3所示，於半導體裝置100中，以鑲嵌製程技術(鑲嵌法)形成配線圖樣P。關於半導體裝置 100之配線圖樣P，係於形成在未圖示之半導體基板(被處理基體W)表面的SiO2膜102上隔著另一絕緣膜104所形成之作為絕緣膜的CF膜(添加氟之碳膜：k=2.1)106處，直接埋入作為配線組件之Cu(銅)114。於圖3中，Cu114係沿深度方向上進行延伸。另外，於圖3中顯示僅配設有一道Cu114的樣態，但實際之半導體裝置100中，係間隔既定間距(例如，約200nm)般複數地配設有Cu114。
接著，說明上述半導體裝置100之製造方法。圖4係顯示半導體裝置之製造步驟的流程圖。圖5係顯示半導體裝置之製造步驟的示意圖。
如圖4所示，首先，於SiO2半導體基板102上藉由上述電漿處理裝置10形成SiCN膜104(步驟S01、圖5(a))。SiCN膜104之膜厚例如約50nm。SiCN膜104係藉由氣體供給部42及氣體供給系統40，將三甲基矽烷氣體及Ar氣體供給至處理空間S，以產生包含矽、碳、及氫之活性種的電漿，在實施不供給該氮氣之處理約5秒後，將氮氣供給至處理空間S並產生氮活性種而進行成膜。
其次，以上述電漿處理裝置10在SiCN膜104上形成作為絕緣膜的CF膜106(步驟S02、圖5(a))。將供給至電漿處理裝置10之處理空間S的C5F8氣體活性化並電漿化，形成活性種，而堆積於半導體基板102表面以形成CF膜106。藉由電漿處理裝置10來形成CF膜106，於上方側之電漿處理空間下方側會形成有存在活性種的成膜空間，由於藉由所謂的軟性(soft)活性種來形成CF膜106，可獲得緻密且與Cu之密著性較高，耐熱性較高的CF膜106。CF膜106之膜厚例如約500nm。
接著，於CF膜106上形成SiCN膜108(圖5(b))。SiCN膜108係以與上述相同之方法所形成。SiCN膜108之膜厚例如約50nm。另外，SiCN膜108可為SiC膜及SiCN膜之層積結構。
接著，於SiCN膜108上形成SiO2膜110。SiO2膜110之膜厚例如約50nm。SiO2膜110係將矽烷氣體與氧氣電漿化，藉由該電漿進行成膜。然後，於SiO2膜110上形成光阻112，例如藉由KrF準分子雷射之步進機進行曝光，並實施光刻製程(步驟S03)。其後，藉由CF4氣體實施乾蝕刻(步驟S04)，藉此，如圖5(d)所示，於CF膜106形成對應配線圖樣P的溝 部C。
接著，使用本實施形態之電漿裝置1，藉由N2氣體對形成有溝部C之CF膜106進行電漿處理(氮化電漿處理)(步驟S05)。此時，電漿處理之條件可為：微波功率2500W、高頻電源58之RF輸出功率10W、處理時間4秒。另外，電漿處理之處理時間可適當地設定在4秒~60秒之範圍內。透過電漿處理，使得存在於CF膜106之表面側(定義有溝部C之表面側)的氟含有率會產生變化，即藉由移除氟來使其減少，以對CF膜106之表面側進行改質。即，於CF膜106之表面係形成富碳層。然後，以稀釋氫氟酸(DHF)實施清洗(洗淨)(步驟S06)，以除去溝部C內之蝕刻殘渣或氧化膜系之硬遮罩，其後，為除去水分，可例如以350℃之處理空間S的溫度實施2小時的退火處理(步驟S07)。步驟S07亦可以其它腔室之退火裝置進行退火。
接著，藉由濺鍍在溝部C形成作為配線材料(金屬)的Cu後，進一步藉由電解金屬鍍覆法來形成，而於CF膜106之溝部C處填充埋入Cu114(步驟S08、圖5(e))。另外，可使用濺鍍、電解金屬鍍覆法、無電解鍍覆法及CVD法中任一方法，或者該等方法中至少2個以上方法來進行Cu之填充。其後，藉由CMP(Chemical Mechanical Polishing)法，將埋入於溝部C處之部分以外的Cu除去，而使表面平坦化(步驟S09、圖5(f))。接著，最後，形成表面保護膜(未圖示)，例如氧化膜或氮化膜。
另外，上述方法中雖於電漿處理中使用N2氣體對CF膜106之表面實施氮化電漿處理，但於電漿處理中亦可使用SiH4(矽烷)氣體、氫電漿。於電漿處理中所使用之氣體只要係能減少CF膜106之表面側的F(氟)者即可。
又，於上述例中雖使用Ar氣體作為產生電漿之氣體，亦可使用其它稀有氣體，例如He(氦)氣、Ne(氖)氣、Kr(氪)氣體、Xe(氙)氣等。CF膜106之原料氣體不限定於C5F8氣體，亦可使用CF4氣體、C2F6氣體、C3F8氣體、C3F6氣體、及C4F8氣體等。又，進行SiCN膜108成膜時，為獲得氮活性種的氣體並不限定於氮氣，亦可為氨氣。
又，進行SiCN膜108成膜時所使用之矽有機化合物並不限定於三甲基 矽烷氣體，亦可使用其它有機化合物。其具體範例為：CH3SiH3、(CH3)2SiH2、(CH3)3SiH、(CH3)4Si、(CH3)2Si(OC2H5)2、(CH3)2Si(OCH3)2、CH3Si(OC3H5)3、CH3Si(OCH3)3、(HCH3SiO)4〔環狀構造〕、((CH3)3Si)2O、(H(CH3)2Si)2O、(H2CH3Si)2O、((CH3)2SiO)3、(CH3ASiO)3、((CH3)2SiO)4、(CH3ASiO)4等。另外，最後3個化合物為環狀構造，「A」為乙烯基(CH-CH3)。
如以上說明，本實施形態中，係採用CF膜106作為絕緣膜，於該CF膜106藉由乾蝕刻形成溝部C之後，將Cu114埋入於溝部C之前實施氮化電漿處理。如此一來，藉由對CF膜106實施氮化電漿處理，移除CF膜106之表面側的氟(F)，而形成富碳層，來對CF膜106之表面側進行改質。藉此，使得CF膜106表面之濕潤性更好，使CF膜106與Cu114接觸結合，達成提高CF膜106與Cu114之密著性。
圖6係顯示SIMS(Secondary Ion Mass Spectrometry：二次離子質譜分析法)之分析結果的圖表。圖6中，橫軸係表示深度〔nm〕，縱軸係表示濃度〔atoms/cm3〕、二次離子強度〔counts/sec〕。圖6所示之SIMS分析係對於在Si基板上依序層積有氧化膜、CF膜及Cu的樣本來實施，於CF膜實施30秒的氮化電漿處理。圖6中，線L1係表示初始狀態之Cu，線L2係表示退火後之Cu，線L3係表示初始狀態之F(氟)，線L4係表示退火後之F，線L5係表示初始狀態之氧化膜(ox)，線L6係表示退火後之氧化膜。
如圖6所示，初始狀態之Cu與退火後之Cu顯示為相同特性，可確認Cu幾乎不朝CF膜(表面富含碳之膜)進行熱擴散。又，亦確認同樣地F不朝Cu進行擴散。如此一來，半導體裝置100中，藉由以絕緣膜表面作為富含碳之CF膜106，可抑制Cu114朝CF膜106進行擴散，藉此，可抑制TDDB(Time-Dependent Dielectric Breakdown)的發生。其結果，可達成提高半導體裝置100之可靠性。
圖7係顯示電阻特性的圖表。圖7中，橫軸係表示電阻〔ohm〕，縱軸係表示機率分布〔%〕。又，圖7中，本實施形態之半導體裝置100特性以「■」表示，設置有障壁金屬層(Ti/TiN/Ti)之習知半導體裝置特性以「▽」 表示。圖8係顯示靜電容量特性的圖表。圖8中，橫軸係表示靜電容量(線路電容)〔pF〕，縱軸係表示機率分布〔%〕。又，圖8中，本實施形態之半導體裝置100特性以「■」表示，設置有障壁金屬層之習知半導體裝置特性以「▽」表示。
如圖7所示，與具備障壁金屬層的習知半導體裝置相比，例如以機率分布為50%觀察時，半導體裝置100的電阻降低約25%。又，半導體裝置100中，關於靜電容量，可獲得與具備障壁金屬層的習知半導體裝置相同的特性。藉此，半導體裝置100中可改善因配線電阻及靜電容量所造成的配線延遲。
本發明並不限定於上述實施形態。例如，上述實施形態中，雖說明了於半導體基板上設置有配線圖樣P之形態的一例，但在具有多層配線結構之情況中，例如在形成有層間絕緣膜(CF膜)及配線(Cu)之下層配線圖樣上，亦可形成上層之配線圖樣P。此時，配線圖樣P之Cu114係藉由貫孔與下層配線(Cu)電性連接。
又，除了上述實施形態，在CF膜106與Cu114之間亦可設置極薄之氧化膜或碳膜。圖9係顯示其它實施形態之半導體裝置的結構剖面圖。如圖9所示，半導體裝置200係在CF膜106與Cu114之間設置有氧化膜118。氧化膜118例如為aCSiO膜(非晶碳氧化矽膜、Amorphous carbon silicon oxide film)。從Cu之阻隔性及低電阻的觀點來看，氧化膜118之厚度較佳地為1nm至15nm以下，更佳地為3~10nm。如此一來，藉由在CF膜106與Cu114之間設置有氧化膜118，因為極薄而可為低電阻，亦可降低配線電阻，且，可進一步抑制Cu114朝CF膜106進行擴散。能以例如三甲基矽烷(TMS)等有機矽烷系化合物氣體，與氧氣、NO2等含有氧之氣體的電漿來形成氧化膜118。又，藉由2丁烯等碳氫化合物氣體之電漿生成碳膜。
圖10係顯示圖9所示之在CF膜106與Cu114之間設置氧化膜118的半導體裝置之電阻特性的圖表。圖10中，橫軸係表示電阻〔ohm〕，縱軸係表示機率分布〔%〕。又，圖10中，在CF膜106與Cu114之間設置有氧化膜118的半導體裝置200特性以「○」表示，設置有障壁金屬層的習知半導體裝置特性以「▽」表示。如圖10所示，與具備障壁金屬層的半導體裝置 相比，例如以機率分布為50%觀察時，在CF膜106與Cu114之間設置有氧化膜118的半導體裝置200之電阻則降低約25%。藉此，可降低半導體裝置200中的配線延遲。
又，圖9所示之半導體裝置200中，在形成氧化膜108之前，可實施氮化電漿處理，亦可不實施氮化電漿處理。
又，上述實施形態(圖3所示之半導體裝置100)中，係在將Cu114埋入CF膜106之溝部C前實施氮化電漿處理，但亦可不實施氮化電漿處理。在前述結構的情況中，由於CF膜106自身具有阻隔功能，因此可抑制Cu114朝CF膜106的擴散。
圖11係顯示其它形態之半導體裝置的SIMS分析結果的圖表。與圖6相同地，圖11所示之SIMS分析係對在Si基板上依序層積有氧化膜、CF膜、及Cu的樣本來實施。圖11中，線L1係表示初始狀態之Cu，線L2係表示退火後之Cu，線L3係表示初始狀態之F(氟)，線L4係表示退火後之F，線L5係表示初始狀態之氧化膜(ox)，線L6係表示退火後之氧化膜。
如圖11所示，不對CF膜實施氮化電漿處理的情況，亦即，縱使是將Cu直接埋入CF膜的結構，仍幾乎沒有確認到Cu之熱擴散。因此，即使是不於CF膜106實施氮化電漿處理的情況，亦可抑制TDDB的發生，達成提高可靠性。
10‧‧‧電漿處理裝置
12‧‧‧處理容器
12a‧‧‧側壁
12b‧‧‧底部
12h‧‧‧排氣孔
14‧‧‧基台
14a‧‧‧台部
14b‧‧‧聚焦環
14c‧‧‧靜電夾具
14d‧‧‧電極
14e‧‧‧絕緣膜
14f‧‧‧絕緣膜
14g‧‧‧冷媒室
16‧‧‧介電體窗組件
16a‧‧‧貫穿孔
16d‧‧‧凹部
18‧‧‧天線
18a‧‧‧慢波板
18b‧‧‧平面天線
20‧‧‧同軸導波管
20a‧‧‧外側導體
20b‧‧‧內側導體
22‧‧‧注射器
24‧‧‧配管組件
28‧‧‧O型環
28a‧‧‧支撐部
29‧‧‧按壓環組件
30‧‧‧微波產生器
30a‧‧‧調諧器
32‧‧‧導波管
34‧‧‧模式轉換器
36‧‧‧冷卻套管
40‧‧‧氣體供給系統(氣體供給部)
40a‧‧‧流量控制器
40b‧‧‧開關閥
42‧‧‧氣體供給部(材料氣體供給部)
42a‧‧‧氣體管線
42b‧‧‧氣體噴射孔
44‧‧‧氣體供給系統
44a‧‧‧氣體管線
44b‧‧‧開關閥
44c‧‧‧流量控制器
46‧‧‧筒狀支撐部
48‧‧‧筒狀支撐部
50‧‧‧排氣路徑
52‧‧‧折流板
54‧‧‧排氣管
56‧‧‧排氣裝置
58‧‧‧高頻電源
60‧‧‧匹配單元
62‧‧‧給電棒
64‧‧‧直流電源
66‧‧‧開關
68‧‧‧包覆線
70‧‧‧配管
72‧‧‧配管
74‧‧‧氣體供給管
S‧‧‧處理空間
W‧‧‧被處理基體

Claims (9)

  1. 一種半導體裝置之製造方法，係於絕緣膜以鑲嵌法(damascene)形成配線，包含有：形成添加氟之碳膜以作為該絕緣膜的步驟；於該絕緣膜形成有對應該配線之溝部的步驟；於該溝部填充作為配線組件之銅的步驟；以及對形成有該溝部之該絕緣膜以電漿處理，將該絕緣膜之表面側進行改質的步驟。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中該絕緣膜之該表面側的改質係使該表面側之氟含有率產生變化。
  3. 如申請專利範圍第1或2項之半導體裝置之製造方法，其中該絕緣膜之該表面側的改質係由包含氮以作為活性種之電漿處理來進行。
  4. 如申請專利範圍第1或2項之半導體裝置之製造方法，其中該電漿處理之處理時間為4秒~60秒。
  5. 如申請專利範圍第1項之半導體裝置之製造方法，其中更包含於該溝部內面形成氧化膜的步驟；且於形成有該氧化膜之該溝部處填充該銅。
  6. 如申請專利範圍第1、2、5項中任一項之半導體裝置之製造方法，其中於形成該添加氟之碳膜的步驟中，作為成膜裝置係使用具備有：形成處理空間的處理容器；微波產生器；將該微波產生器所產生之微波進行放射的天線；設置於該處理空間與該天線之間的介電體窗；供給電漿激發用氣體的氣體供給部；以及供給形成該添加氟之碳膜用的材料氣體之材料氣體供給部的成膜裝置；從該氣體供給部供給電漿激發用之該氣體，從該天線放射微波以激發電漿，從該材料氣體供給部供給該材料氣體，藉由該電漿使該材料氣體進行反應而形成該添加氟之碳膜。
  7. 一種半導體裝置，係於絕緣膜以鑲嵌法形成配線，具備有： 作為添加氟之碳膜的該絕緣膜；以及設置於該絕緣膜，由埋入對應該配線之溝部的銅所組成的配線組件；與該銅相連接之該絕緣膜的表面側係藉由電漿處理進行改質。
  8. 如申請專利範圍第7項之半導體裝置之製造方法，其中該絕緣膜之該表面側係進行改質以使氟含有率產生變化。
  9. 如申請專利範圍第8項之半導體裝置之製造方法，其中該絕緣膜之該表面側的改質係由包含氮以作為活性種之電漿處理來進行。
TW102106054A 2012-02-22 2013-02-21 Semiconductor device manufacturing method and semiconductor device TWI587396B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012036424 2012-02-22

Publications (2)

Publication Number Publication Date
TW201401375A TW201401375A (zh) 2014-01-01
TWI587396B true TWI587396B (zh) 2017-06-11

Family

ID=49005824

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102106054A TWI587396B (zh) 2012-02-22 2013-02-21 Semiconductor device manufacturing method and semiconductor device

Country Status (4)

Country Link
US (1) US9543191B2 (zh)
JP (1) JP5935227B2 (zh)
TW (1) TWI587396B (zh)
WO (1) WO2013125647A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11195748B2 (en) * 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11164780B2 (en) 2019-06-07 2021-11-02 Applied Materials, Inc. Process integration approach for selective metal via fill

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486559B1 (en) * 1997-06-25 2002-11-26 Nec Corporation Copper wiring structure comprising a copper material buried in a hollow of an insulating film and a carbon layer between the hollow and the copper material in semiconductor device and method of fabricating the same
US20080254641A1 (en) * 2004-01-13 2008-10-16 Tokyo Electron Limited Manufacturing Method Of Semiconductor Device And Film Deposition System
TW200849474A (en) * 2007-05-22 2008-12-16 Rohm Co Ltd Semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165898A (en) * 1998-10-23 2000-12-26 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
US6803314B2 (en) * 2001-04-30 2004-10-12 Chartered Semiconductor Manufacturing Ltd. Double-layered low dielectric constant dielectric dual damascene method
JP4413556B2 (ja) * 2003-08-15 2010-02-10 東京エレクトロン株式会社 成膜方法、半導体装置の製造方法
JP4715207B2 (ja) * 2004-01-13 2011-07-06 東京エレクトロン株式会社 半導体装置の製造方法及び成膜システム
KR101185757B1 (ko) 2005-06-20 2012-09-25 고에키자이단호진 고쿠사이카가쿠 신고우자이단 층간 절연막 및 배선 구조와 그것들의 제조 방법
JP5120913B2 (ja) * 2006-08-28 2013-01-16 国立大学法人東北大学 半導体装置および多層配線基板
JP5261964B2 (ja) * 2007-04-10 2013-08-14 東京エレクトロン株式会社 半導体装置の製造方法
JP2009088267A (ja) * 2007-09-28 2009-04-23 Tokyo Electron Ltd 成膜方法、成膜装置、記憶媒体及び半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486559B1 (en) * 1997-06-25 2002-11-26 Nec Corporation Copper wiring structure comprising a copper material buried in a hollow of an insulating film and a carbon layer between the hollow and the copper material in semiconductor device and method of fabricating the same
US20080254641A1 (en) * 2004-01-13 2008-10-16 Tokyo Electron Limited Manufacturing Method Of Semiconductor Device And Film Deposition System
TW200849474A (en) * 2007-05-22 2008-12-16 Rohm Co Ltd Semiconductor device

Also Published As

Publication number Publication date
US20150041983A1 (en) 2015-02-12
WO2013125647A1 (ja) 2013-08-29
JPWO2013125647A1 (ja) 2015-07-30
JP5935227B2 (ja) 2016-06-15
TW201401375A (zh) 2014-01-01
US9543191B2 (en) 2017-01-10

Similar Documents

Publication Publication Date Title
KR101083211B1 (ko) 높은 선택도로 유전체 배리어층을 에칭하는 방법
US7662728B2 (en) Substrate processing method
TWI640040B (zh) 用於穩定蝕刻後界面以減少下一處理步驟前佇列時間問題的方法
US8383519B2 (en) Etching method and recording medium
US20090152686A1 (en) Film Forming Method for Dielectric Film
US9362111B2 (en) Hermetic CVD-cap with improved step coverage in high aspect ratio structures
TW200818269A (en) Method of forming film, film forming device and memory medium as well as semiconductor device
JP2009088267A (ja) 成膜方法、成膜装置、記憶媒体及び半導体装置
US20100132613A1 (en) Fabrication of low dielectric constant insulating film
KR20130041120A (ko) 층간 절연층 형성 방법 및 반도체 장치
TWI587396B (zh) Semiconductor device manufacturing method and semiconductor device
JP2008004841A (ja) 半導体装置及び半導体装置の製造方法
JP2004349458A (ja) フッ素添加カーボン膜の形成方法
JP5710606B2 (ja) アモルファスカーボンのドーピングによるフルオロカーボン（ＣＦｘ）の接合の改善
JP2005260060A (ja) レジスト除去装置及びレジスト除去方法、並びにそれを用いて製造した半導体装置
JP2006073612A (ja) レジスト除去方法
CN100541736C (zh) 基板处理方法
TWI505360B (zh) 用於氟碳化物膜之金屬碳化物阻障層的形成方法
JP5304759B2 (ja) 成膜方法及び半導体装置
KR20190015132A (ko) 피처리체를 처리하는 방법
KR100733440B1 (ko) 불소 첨가 카본막의 형성 방법
JP2006059848A (ja) レジスト除去方法及び半導体装置の製造方法
JP2005217373A (ja) 表面処理方法
JP2008028330A (ja) 半導体装置の製造方法及び半導体装置
WO2012129122A1 (en) Method for controlling dangling bonds in fluorocarbon films