JP5935227B2 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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- JP5935227B2 JP5935227B2 JP2014500927A JP2014500927A JP5935227B2 JP 5935227 B2 JP5935227 B2 JP 5935227B2 JP 2014500927 A JP2014500927 A JP 2014500927A JP 2014500927 A JP2014500927 A JP 2014500927A JP 5935227 B2 JP5935227 B2 JP 5935227B2
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Description
Claims (3)
- 絶縁膜にダマシン法にて配線を形成する半導体装置の製造方法であって、
前記絶縁膜としてフッ素添加カーボン膜を成膜する工程と、
前記絶縁膜に前記配線に対応する溝部を形成する工程と、
前記溝部が形成された前記絶縁膜をプラズマにて処理し、前記絶縁膜の表面側を改質する工程と、
配線部材である銅を、前記絶縁膜と当該銅とが接するように前記溝部に充填する工程と、を含み、
前記銅と接する前記絶縁膜の前記表面側の改質は、窒素を活性種として含むプラズマ処理により行い、
前記絶縁膜の前記表面側の改質では、当該表面側のフッ素の含有率を減少させる、半導体装置の製造方法。 - 前記プラズマ処理の処理時間は4秒〜60秒である、請求項1記載の半導体装置の製造方法。
- 前記フッ素添加カーボン膜を成膜する工程では、成膜装置として、
処理空間を形成する処理容器と、
マイクロ波発生器と、
前記マイクロ波発生器によって発生されるマイクロ波を放射するアンテナと、
前記処理空間と前記アンテナとの間に設けられた誘電体窓と、
プラズマ励起用のガスを供給するガス供給部と、
前記フッ素添加カーボン膜を形成するための材料ガスを供給する材料ガス供給部と、を備える成膜装置を用い、
前記ガス供給部からプラズマ励起用の前記ガスを供給させ、前記アンテナからマイクロ波を放射させてプラズマを励起させ、前記材料ガス供給部から前記材料ガスを供給させて、前記材料ガスを前記プラズマにより反応させて前記フッ素添加カーボン膜を形成する、請求項1又は2記載の半導体装置の製造方法。
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PCT/JP2013/054380 WO2013125647A1 (ja) | 2012-02-22 | 2013-02-21 | 半導体装置の製造方法及び半導体装置 |
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JP3031301B2 (ja) * | 1997-06-25 | 2000-04-10 | 日本電気株式会社 | 銅配線構造およびその製造方法 |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6803314B2 (en) * | 2001-04-30 | 2004-10-12 | Chartered Semiconductor Manufacturing Ltd. | Double-layered low dielectric constant dielectric dual damascene method |
JP4413556B2 (ja) | 2003-08-15 | 2010-02-10 | 東京エレクトロン株式会社 | 成膜方法、半導体装置の製造方法 |
JP4715207B2 (ja) * | 2004-01-13 | 2011-07-06 | 東京エレクトロン株式会社 | 半導体装置の製造方法及び成膜システム |
WO2005069367A1 (ja) * | 2004-01-13 | 2005-07-28 | Tokyo Electron Limited | 半導体装置の製造方法および成膜システム |
WO2006137384A1 (ja) * | 2005-06-20 | 2006-12-28 | Tohoku University | 層間絶縁膜および配線構造と、それらの製造方法 |
JP5120913B2 (ja) * | 2006-08-28 | 2013-01-16 | 国立大学法人東北大学 | 半導体装置および多層配線基板 |
JP5261964B2 (ja) * | 2007-04-10 | 2013-08-14 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP5089244B2 (ja) * | 2007-05-22 | 2012-12-05 | ローム株式会社 | 半導体装置 |
JP2009088267A (ja) * | 2007-09-28 | 2009-04-23 | Tokyo Electron Ltd | 成膜方法、成膜装置、記憶媒体及び半導体装置 |
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US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
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