TWI569333B - Method for fabricating semiconductor device - Google Patents

Description

Method for fabricating semiconductor components

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal-gate complementary metal oxide semiconductor (CMOS) transistor device and a method of fabricating the same.

As the size of semiconductor components continues to shrink, the conventional method utilizes a tunneling effect that reduces the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-K) materials have an effective reduction in physical limit thickness and are under the same equivalent oxide thickness (EOT). It effectively reduces the leakage current and achieves the equivalent capacitance to control the channel switch. It is used to replace the traditional germanium dioxide layer or the yttria layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching High-K gate dielectric layer. Control electrode.

However, how to continuously increase the efficiency of semiconductor components even if the high-k gate dielectric layer is used to replace the conventional germanium dioxide or yttrium oxide gate dielectric layer, and the metal gate with matching work function is substituted for the conventional polysilicon gate. And to ensure that its reliability is still the problem that the semiconductor industry wants to solve.

Therefore, the present invention discloses a method for fabricating a dual work function metal gate CMOS device to improve the overall performance of existing components.

A preferred embodiment of the invention discloses a method of fabricating a semiconductor device. First, a substrate is provided having a gate structure thereon, and then a first mask layer is formed on the surface of the substrate and sidewalls of the gate structure. Forming a second covering layer and covering the first covering layer, forming a third covering layer on the surface of the second covering layer, and performing an etching process to remove a portion of the third covering layer, the second covering layer and the first covering layer. The sidewall of the gate structure forms a first sidewall and a second sidewall. Finally, a contact etch stop layer (CESL) is formed on the surface of the substrate and covers the second sidewall, and the third mask layer has the same deposition conditions as the contact etch stop layer.

Another embodiment of the present invention discloses a semiconductor device including a substrate; a gate structure is disposed on the substrate; a first sidewall is disposed on a sidewall of the gate structure; and a second sidewall is disposed around the first sidewall a source/drain is disposed in the substrate on both sides of the second sidewall; and a contact etch stop layer is disposed on the surface of the substrate and covers the gate structure, and at least a portion of the second sidewall and the contact etch stop layer have The same chemical composition and / or physical properties.

Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention. In the present embodiment, the semiconductor device is preferably a CMOS transistor, and the preferred embodiment uses a gate-last process in conjunction with a high-k first process. As shown in FIG. 1, a substrate 100 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. A first region and a second region are defined on the substrate 100, such as a PMOS region 104 and an NMOS region 102, and a plurality of shallow trench isolations for providing electrical isolation of the two transistor regions are formed in the substrate 100 (shallow Trench isolation, STI) 106.

Then, an interfacial layer 108 made of a dielectric material such as an oxide or a nitride is formed on the surface of the substrate 100, and a high-k dielectric layer 110 and a barrier layer 112 are sequentially formed. A stacked film of a polysilicon layer 116 and a hard mask 118 is on the dielectric layer 108.

The high-k dielectric layer 110 may be one or more layers having a dielectric constant of substantially greater than 20. The high-k dielectric layer 110 of the present embodiment may include a metal oxide layer, such as a rare earth. Metal oxide layer, and optionally free hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum) Oxide, AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta ₂ O ₃ ), zirconium oxide (ZrO ₂ ), Zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (lead) Zirconate titanate, PbZr _x Ti _1-x O ₃ , PZT) and a group consisting of barium strontium titanate (BaxSr _1-x TiO ₃ , BST). The barrier layer 112 is preferably made of titanium nitride (TiN).

Then, as shown in FIG. 2, a patterned photoresist layer (not shown) is used as a mask to perform a pattern transfer process, and a part of the hard mask 118 and the polysilicon layer are removed by a single etching or successive etching step. 116, the barrier layer 112, the high-k dielectric layer 110 and the dielectric layer 108, and stripping the patterned photoresist layer to form a first gate structure 120 and a PMOS region 104 and the NMOS region 102, respectively The second gate structure 122 serves as a dummy gate structure.

The polysilicon layer 116 is used as a sacrificial layer, and may also be composed of a polycrystalline germanium material having no undoped, a polycrystalline germanium material having an N+ dopant, or an amorphous germanium material. The hard mask 118 is composed of cerium oxide (SiO ₂ ), cerium nitride (SiN), tantalum carbide (SiC) or cerium oxynitride (SiON).

Then, an ionic implantation process can be performed on the PMOS region 104 and the NMOS region 102 to form a lighter corresponding conductive type in the substrate 100 on both sides of the first gate structure 120 and the second gate structure 122, respectively. Doped with a drain 128.

Then, an offset spacer (not shown) is formed on the sidewalls of the first gate structure 120 and the second gate structure 122, and a selective epitaxial PMOS and/or NMOS is selectively performed. In the growth process, for example, a recess is formed in the substrate 100 on both sides of the sidewall of the PMOS region 104, and an epitaxial layer 132 is filled. In this embodiment, the epitaxial layer 132 preferably comprises germanium germanium, and may be formed in a single layer or multiple layers; when the epitaxial layer is grown, it may be doped in-situly, and the doping may be performed in a gradual manner (for example) , the bottom layer has no dopant, the first layer is lightly doped, the second layer is thicker, the third layer is rich, ... the top layer has no dopant or light dopant; the hetero atom (in this case) The concentration of germanium atoms can also be changed in a gradual manner, and the concentration thereof will vary depending on the lattice constant and the surface characteristics. However, the surface may be expected to have a lighter germanium atom concentration or no germanium atoms for subsequent germanium formation.

Then, the sidewall spacers are selectively removed, and then a first mask layer 162 is formed on the surface of the substrate 100 and covers the sidewalls of the first gate structure 120 and the second gate 122 and the top of the hard mask 118, respectively. The second cover layer 164 is on the surface of the first cover layer 162 and a third cover layer 166 on the surface of the second cover layer 164.

Then, as shown in FIG. 3, an etching process is performed to remove a portion of the third capping layer 166, the second capping layer 164, and the first capping layer 162 to form sidewalls of the first gate structure 120 and the second gate structure 122, respectively. A first sidewall 124 and a second sidewall 126. The first sidewall 12 includes an approximately L-shaped first capping layer 162, and the second sidewall 126 includes an approximately L-shaped second capping layer 164 and an etched third capping layer 166 spanning the L-shaped portion. Two cover layers 164.

In this embodiment, the first mask layer 162 preferably comprises tantalum nitride, the second mask layer 164 comprises tantalum oxide, and the third mask layer 166 comprises tantalum nitride, and the third mask layer 166 is preferably in the PMOS region. 104 and NMOS region 102 have different stresses, respectively.

Then, as shown in FIG. 4, an ionic implantation process can be performed on the PMOS region 104 and the NMOS region 102, respectively, to form a corresponding one of the first sidewall 124 and the substrate 100 on both sides of the second sidewall 126. Conductive source/drain 130.

The ion implantation of the dopant forming the source/drain 130 in this embodiment is performed after the epitaxial layer 132, but may be performed before the epitaxial layer 132 is formed according to the process requirements, or when the epitaxial layer is grown. The dopant of the source/drain 130 is doped in-situly.

Subsequently, a metal telluride process can be performed, for example, forming a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum or a combination thereof on the substrate 100 and covering the source/drain 130 and the epitaxial layer 132, and then reacting the metal layer with the source/drain 130 and the epitaxial layer 132 by using at least one rapid thermal anneal (RTP) process for the NMOS region 102 and the PMOS region 104 A surface of the substrate 100 and the epitaxial layer 132 respectively form a deuterated metal layer 134. Finally, the unreacted metal is removed.

A contact etch stop layer 136 is then formed on the surface of the substrate 100 and covers the second sidewall 126 of the first gate structure 120 and the second gate structure 122, and then an interlayer dielectric layer 138 is formed on the surface of the substrate 100 and covered. PMOS region 104 and NMOS region 102. In the present embodiment, the contact hole etch stop layer 136 is preferably made of tantalum nitride, and it can have different stresses in the PMOS region 104 and the NMOS region 102, for example, applying an appropriate ion cloth value process or UV. The heat treatment is performed to simultaneously adjust the stress of the third mask layer 166 of the second sidewall 126 and the contact hole etch stop layer 136 in the PMOS region 104 while adjusting the third mask layer 166 of the second sidewall 126 in the region of the NMOS region 102. The hole etches the stress of the stop layer 136, and the interlayer dielectric layer 138 is preferably composed of ruthenium oxide and may have a thickness of between 1,500 and 5,000 angstroms, preferably about 3,000 angstroms. In addition, in accordance with a preferred embodiment of the present invention, the third masking layer 166 and the contact hole etch stop layer 136 preferably have the same deposition conditions, such as pressure having the same primary deposition step during deposition, temperature of the primary deposition step, precursor The kind of the substance, the flow ratio of the driven gas to the reaction gas, and/or the bias power and the RF power. The difference between the two is that the thickness of the deposit is different, and the stress of the two will be slightly different due to the different thicknesses. Since the third mask layer 166 and the contact hole etch stop layer 136 are deposited under the same conditions during deposition, at least a portion of the first sidewall spacer 124 and the second sidewall spacer 126 formed subsequently have a contact hole etch stop layer 136. The same chemical composition and/or physical properties, for example, have the same bonding ratio, impurity content and/or density. Taking the tantalum nitride commonly used in the contact hole etch stop layer as an example, the impurity contains hydrogen and the impurity content is the atomic percentage of hydrogen in the tantalum nitride; the bonding ratio is, for example, the ratio of the Si-N bond to the N-H bond. The third capping layer 166 and the contact hole etch stop layer 136 preferably have the same bonding ratio or impurity content or density, or the third capping layer 166 has the same bonding ratio and impurity content as the contact hole etch stop layer 136. density.

A planarization process is then performed, such as by removing a portion of the interlayer dielectric layer 138 using a chemical mechanical polishing process until the contact etch stop layer 136 surface is exposed.

Then, as shown in FIG. 5, a portion of the contact hole etch stop layer 136 and the hard mask 118 are removed by etching, and another etching process is performed to vacate the PMOS region 104 and the polysilicon layer 116 of the NMOS region 102 for each region. A groove 140 is formed respectively. It should be noted that, in this embodiment, although the polycrystalline germanium layer of two regions is simultaneously hollowed out, the polycrystalline germanium layer of one of the regions may be first hollowed out to form a groove and filled with metal, and then another region is removed. The polysilicon layer is filled with metal.

Then, as shown in FIG. 6, a work function metal layer 144, 150 and a low-impedance conductive layer 152 are formed in the PMOS region 104 domain and the NMOS region 102, respectively, and fill the recess 140.

Then, one or more planarization processes are performed to planarize the NMOS and the PMOS, respectively, for example, using a chemical mechanical polishing process to remove a portion of the low-impedance conductive layer 152 and the work function metal layers 144, 150 for the PMOS region 104 and The NMOS regions 102 respectively form a first metal gate 154 and a second metal gate 156. It should be noted that the present invention provides a dual work function metal gate CMOS device and a fabrication method thereof, wherein the P-type work function metal layer 144 of the PMOS region 104 and the N-type work function metal layer 150 of the NMOS region 102 are preferably separated. This is well known to those skilled in the art and will not be described here. In addition, although the above description is simple for the material filled in the groove, the film structure on both sides of the N/P MOS may be different in order to adjust the work function and solve the problem of the integration of the N/P MOS processes. .

In the present embodiment, the P-type work function metal layer 144 is a metal that satisfies the required work function of the P-type transistor, such as titanium nitride (TiN) or tantalum carbide (TaC). But not limited to the above. The N-type work function metal layer 150 is a metal that satisfies the required work function of the N-type transistor, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl). Or aluminum bismuth (HfAl), but not limited to the above. In addition, the low-impedance conductive layer 152 includes aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), A composite metal layer such as titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN), but is not limited thereto.

It should be noted that, in the above embodiment, although the high-k first process is used to complete the fabrication of the semiconductor device, the spirit of the present invention can be applied to the post-high-k dielectric layer (high- k last) Process, which is also within the scope of the present invention.

For example, as shown in FIG. 7, a dummy gate structure as shown in FIG. 3 may be formed on the substrate 100, wherein the dummy gate includes only a dielectric layer 108, a polysilicon layer, and a hard mask. The cover does not have a high-k dielectric layer and a barrier layer. Then, the process of FIG. 4 is sequentially performed, including forming a first sidewall portion 124 and a second sidewall spacer 126 around the dummy gate, and forming the substrate in the substrate 100 on both sides of the first sidewall spacer 124 and the second sidewall spacer 126. Corresponding to the light-doped drain 128 and the source/drain region 130 of the conductive type, forming a contact etch stop layer 136 and the interlayer dielectric layer 138 on the surface of the dummy gate and the substrate 100, and removing portions by the planarization process The contact hole etch stop layer 136 and the interlayer dielectric layer 138 are contacted and the polysilicon layer or the like in the dummy gate is hollowed out. Then, as shown in FIG. 7, a high-k dielectric layer 110 and a barrier layer 112 are sequentially formed in the recesses 140 of the PMOS region 104 and the NMOS region 102, and then a N is formed according to the above embodiment. The work function metal layer 150 and a P-type work function metal layer 144 are formed on the NMOS region 102 and the PMOS region 104, forming a low-impedance conductive layer 152 on the P-type work function metal layer 144 and the N-type work function metal layer 150. The full recess 140 and another planarization process are performed to form a metal gate 154, 156 in the NMOS region 102 and the PMOS region 104, respectively.

In summary, since the entire gate structure and the source/drain are completed in the current process, a thinning action is usually performed on the second sidewall to remove the peripheral nitride layer in some of the second sidewalls. The invention is characterized in that the loading of the tantalum nitride and/or the loss of the germanium metal layer is performed. In the invention, the second sidewall is preferably formed by sequentially depositing a cap layer composed of hafnium oxide and a layer of tantalum nitride. The stress contact hole etch stop layer is then etched to remove a portion of the two material layers to form a second sidewall. Since the present invention employs a partial contact hole etch stop layer as the material of the second sidewall, it is possible to greatly reduce the overall etch stop layer of the subsequent contact hole covering the entire substrate surface without thinning the second sidewall. Thickness, and at the same time improve the problem of tantalum nitride load and loss of deuterated metal layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102. . . NMOS region

104. . . PMOS area

106. . . Shallow trench isolation

108. . . Dielectric layer

110. . . High dielectric constant dielectric layer

112. . . Barrier layer

114. . . Metal layer

116. . . Polycrystalline layer

118. . . Hard mask

120. . . First gate structure

122. . . Second gate structure

124. . . First side wall

126. . . Second side wall

128. . . Lightly doped bungee

130. . . Source/bungee

132. . . Epitaxial layer

134. . . Deuterated metal layer

136. . . Contact hole etch stop layer

138. . . Interlayer dielectric layer

140. . . Groove

144. . . P type work function metal layer

150. . . N-type work function metal layer

152. . . Low impedance conductive layer

154. . . First metal gate

156. . . Second metal gate

162. . . First cover

164. . . Second covering layer

166. . . Third covering layer

1 to 7 are schematic views showing a semiconductor device having a metal gate according to a preferred embodiment of the present invention.

100. . . Base

102. . . NMOS region

104. . . PMOS area

106. . . Shallow trench isolation

108. . . Dielectric layer

110. . . High dielectric constant dielectric layer

112. . . Barrier layer

124. . . First side wall

126. . . Second side wall

128. . . Lightly doped bungee

130. . . Source/bungee

132. . . Epitaxial layer

134. . . Deuterated metal layer

136. . . Contact hole etch stop layer

138. . . Interlayer dielectric layer

144. . . P type work function metal layer

150. . . N-type work function metal layer

152. . . Low impedance conductive layer

154. . . First metal gate

156. . . Second metal gate

162. . . First cover

164. . . Second covering layer

166. . . Third covering layer

Claims (21)

A method of fabricating a semiconductor device, comprising: providing a substrate having a gate structure; forming a first capping layer on the surface of the substrate and sidewalls of the gate structure; forming a second capping layer and covering the first a mask layer; forming a third mask layer on the surface of the second mask layer; performing an etching process to remove portions of the third mask layer, the second mask layer and the first mask layer to form sidewalls of the gate structure a first sidewall and a second sidewall; and a contact etch stop layer (CESL) is formed on the surface of the substrate and covers the second sidewall, wherein the third mask and the contact hole The etch stop layer is formed under the same deposition conditions, has the same chemical composition and/or physical properties, but has different thicknesses, and all have stress. The method of claim 1, wherein the first covering layer comprises tantalum nitride. The method of claim 1, wherein the second covering layer comprises cerium oxide. The method of claim 1, wherein the third covering layer comprises tantalum nitride. The method of claim 1, wherein the gate structure comprises a high-k dielectric layer and a polysilicon layer. The method of claim 1, wherein the deposition conditions comprise a precursor, a driven gas, a pressure, and a process power. The method of claim 1, wherein the forming the first sidewall and the second sidewall comprises: forming a source/drain on the substrate on both sides of the second sidewall; forming a dielectric layer An electric layer covers the contact hole etch stop layer; a portion of the dielectric layer is removed by a first planarization process to expose the contact hole etch stop layer; a recess is formed in the gate structure; and a work function metal is formed Forming a layer in the recess; forming a conductive layer on the work function metal layer and filling the recess; and performing a second planarization process to form a metal gate. A semiconductor device comprising: a substrate; a gate structure is disposed on the substrate; a first sidewall is disposed on a sidewall of the gate structure; and a second sidewall is disposed around the first sidewall; a source/drain is disposed in the substrate on both sides of the second sidewall; and a contact etch stop layer is disposed on the surface of the substrate and covering the gate structure, and at least a portion of the second sidewall is in contact with the gate The hole etch stop layer has the same chemical composition and/or physical properties but different thicknesses and has stress. The semiconductor device of claim 8, wherein the first sidewall includes tantalum nitride. The semiconductor device of claim 8, wherein the first sidewall sub-system is L-shaped. The semiconductor device of claim 8, wherein the second sidewall includes an L-type cover layer and a cover layer is disposed on the L-type cover layer. The semiconductor device of claim 11, wherein the L-type mask layer comprises ruthenium oxide. The semiconductor device of claim 11, wherein the mask layer comprises tantalum nitride. The semiconductor device of claim 11, wherein the masking layer has the same chemical composition and/or physical properties as the contact hole etch stop layer. The semiconductor device of claim 8, wherein the contact hole etch stop layer comprises tantalum nitride. The semiconductor device of claim 8, wherein the gate structure comprises a high-k dielectric layer, a work function metal layer, and a conductive layer. The semiconductor device of claim 16, wherein the high-k dielectric layer is U-shaped. The semiconductor device of claim 16, wherein the high-k dielectric layer is in a font shape. The semiconductor device of claim 8, wherein at least a portion of the second sidewall spacer has the same bonding ratio as the contact hole etch stop layer. The semiconductor device of claim 8, wherein at least a portion of the second sidewall has the same impurity content as the contact hole etch stop layer. The semiconductor device of claim 8, wherein at least a portion of the second sidewalls have the same density as the contact hole etch stop layer.