TW202420418A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a gate structure, a first spacer, a second spacer, an epitaxial layer and a capping layer. The gate structure is disposed on a substrate. The first spacer and the second spacer are around the gate structure, wherein the substrate includes an inclined surface directly connected with the second spacer. The epitaxial layer is disposed at two sides of the gate structure and covers the inclined surface. The capping layer is disposed on the epitaxial layer, wherein the capping layer includes a flat upper surface and an inclined sidewall connected with the flat upper surface.

Description

Semiconductor components

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a hole between a sidewall and a substrate by using a cleaning process.

In order to increase the carrier mobility of a semiconductor structure, one can choose to apply compressive stress or tensile stress to the gate channel. For example, if compressive stress needs to be applied, conventional technology often uses selective epitaxial growth (SEG) technology to form an epitaxial structure with the same lattice arrangement as the silicon substrate in a silicon substrate, such as a silicon germanium (SiGe) epitaxial structure. By using the characteristic that the lattice constant of the silicon germanium epitaxial structure is greater than the lattice of the silicon substrate, stress is generated in the channel region of the P-type metal oxide semiconductor transistor, increasing the carrier mobility in the channel region, and thereby increasing the speed of the metal oxide semiconductor transistor. On the other hand, if it is an N-type semiconductor transistor, a silicon carbide (SiC) epitaxial structure can be formed in the silicon substrate to generate tensile stress on the gate channel region.

In the current epitaxial growth process of forming MOS transistors with epitaxial layers, the epitaxial layers are usually grown first, then part of the interlayer dielectric layer is removed to form contact holes, and then metal materials are filled to form contact plugs. However, this process sequence is easy to damage the surface of the grown epitaxial layer and affect the operation of the device. Therefore, how to improve the existing process technology to solve the existing bottleneck is an important issue today.

An embodiment of the present invention discloses a semiconductor element, comprising a gate structure, a first sidewall, a second sidewall, an epitaxial layer and a cover layer. The gate structure is disposed on a substrate. The first sidewall and the second sidewall surround the gate structure, wherein the substrate comprises an inclined surface directly connected to the second sidewall. The epitaxial layer is disposed on both sides of the gate structure and covers the inclined surface. The cover layer is disposed on the epitaxial layer, wherein the cover layer comprises a flat upper surface and an inclined sidewall connected to the flat upper surface.

Please refer to Figures 1 to 6, which are schematic diagrams of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. As shown in Figure 1, a substrate 12 is first provided, and then gate structures 14 and 16 are formed on the substrate 12. In this embodiment, the gate structures 14 and 16 are preferably formed by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer process, removing part of the hard mask, part of the gate material layer, and the like by a single etching or successive etching steps. The material layer and a portion of the gate dielectric layer are formed, and then the patterned photoresist is stripped to form gate structures 14 and 16 consisting of at least a patterned gate dielectric layer 18, a patterned gate material layer 20 and a patterned hard mask 22 on the substrate 12, wherein the gate dielectric layer 18 and the gate material layer 20 preferably constitute a gate electrode. It should be noted that, in order to highlight the subsequent steps of forming an epitaxial layer between the gate structures 14 and 16, this embodiment mainly takes the formation of two gate structures 14 and 16 on the substrate 12 as an example, and only partial structures of the two gate structures 14 and 16 and the area between the two gate structures 14 and 16 are shown.

In the present embodiment, the substrate 12 is a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The gate dielectric layer 18 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN) or a high dielectric constant (high-k) material; the gate material layer 20 may include a conductive material such as a metal material, polysilicon or metal silicide; the hard mask 22 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC) and silicon oxynitride (SiON), but is not limited thereto.

In addition, in one embodiment, a plurality of doped wells (not shown) or a plurality of shallow trench isolations (STI) for electrical isolation may be formed in advance in the substrate 12. Furthermore, although the present embodiment takes a planar transistor as an example, in other variant embodiments, the semiconductor process of the present invention may also be applied to non-planar transistors, such as a fin field effect transistor (Fin-FET). In this case, the substrate 12 indicated in FIG. 1 corresponds to a fin structure formed on the substrate 12.

Then, at least one sidewall is formed on the sidewalls of the gate structures 14 and 16, and a lightly doped ion implantation is selectively performed. A rapid temperature annealing process is performed at a temperature of about 930° C. to activate the implanted dopants in the substrate 12, so as to form a lightly doped drain 24 in the substrate 12 on both sides of the sidewall. In this embodiment, the sidewall is preferably a composite sidewall, which may include a sidewall 26 disposed on the gate structure 14, 16 or the gate electrode sidewall, a sidewall 28 disposed on the sidewall of the sidewall 26, and a sidewall 30 disposed on the sidewall of the sidewall 28, wherein the innermost sidewall 26 preferably includes an I-shaped cross-section, the middle sidewall 28 preferably includes an L-shaped cross-section, and the outermost sidewall 30 preferably includes an I-shaped cross-section. In the present embodiment, the innermost sidewall 26 may include the same or different materials as the middle sidewall 28 and the outermost sidewall 30, respectively, and the sidewall 26 may include silicon oxide, silicon nitride, silicon oxynitride or silicon nitride carbide, while the middle sidewall 28 and the outermost sidewall 30 preferably include different materials, for example, the middle sidewall 28 preferably includes silicon oxide and the outermost sidewall 30 is preferably composed of silicon nitride.

Next, as shown in FIG. 2 , an etching process is performed to form a recess 32 in the substrate 12 on both sides of the sidewall 30. For example, the etching process may include first performing a dry etching step to pre-form an initial trench (not shown) in the substrate 12 on both sides of the gate structure 16, and then performing a wet etching process to isotropically enlarge the initial trench to form the recess 32. In an embodiment of the present invention, the wet etching process may selectively use an etching liquid such as ammonium hydroxide (NH ₄ OH) or tetramethylammonium hydroxide (TMAH). It is worth noting that the method of forming the groove 32 is not limited to the aforementioned dry etching combined with wet etching method, and can also be formed by single or multiple dry etching and/or wet etching methods. For example, in one embodiment, the groove 32 can have different cross-sectional shapes, such as arc, hexagon (hexagon; also known as sigma Σ) or octagon (octagon) cross-sectional shapes. This embodiment is illustrated with the hexagonal cross-sectional shape as the implementation mode, but is not limited to this. It is worth noting that the etching process performed in this stage preferably does not remove any sidewalls, so after the etching process is completed, the outer sidewalls of the sidewall 30 are still preferably aligned with the outermost sidewalls of the middle L-shaped sidewall 28.

As shown in FIG. 3 , a cleaning process 34 is then performed to slightly trim the side wall 30 and form a hole 36 between the side wall 30 and the substrate 12. In detail, the cleaning process 34 preferably removes the outermost part of the side wall 30 and the middle part of the side wall 28 at the same time, so that the thickness of the side wall 30 is slightly thinner and the horizontal part of the side wall 28 that originally presents an L-shape is slightly shrunk or even changed from an L-shaped cross section to an I-shaped cross section, so that the above-mentioned hole 36 is formed between the side wall 30 and the substrate 12. In other words, after the cleaning process 34, the outer side wall of the outer side wall 30 is preferably not aligned with the outer side wall of the middle side wall 28, and the side wall 30 can be selected to straddle the side wall 28 or not according to the shape of the middle side wall 28. For example, as shown in FIG. 3 , if the horizontal portion of the middle L-shaped side wall 28 is only slightly retracted but still presents an L-shape, the outer side wall 30 is preferably straddled on the horizontal portion of the L-shaped side wall 28. However, if the horizontal portion of the middle L-shaped side wall 28 is removed during the cleaning process and converted into an I-shape, the inner side wall of the outer side wall 30 will be preferably cut and converted into the outer side wall of the I-shaped side wall 28.

It should also be noted that the cleaning process 34 performed at this stage not only thins the thickness of the outermost sidewall 30, but also preferably removes a portion of the surface of the substrate 12 in contact with the L-shaped sidewall 28, so that the surface of the substrate 12 that originally presents a flat surface forms an inclined surface 38, wherein the angle between the inclined surface 38 and the upper surface of the substrate 12 (or the surface where the bottom of the sidewall 28 contacts the substrate 12) is preferably greater than 90 degrees but less than 180 degrees. In this embodiment, the cleaning solution used in the cleaning process 34 may include but is not limited to diluted hydrofluoric acid (dHF) and/or TMAH.

Then, as shown in FIG. 4 , a selective epitaxial growth (SEG) process is performed to form a selective buffer layer (not shown) and an epitaxial layer 40 in the groove 32. In the present embodiment, the overall shape of the epitaxial layer 40 is preferably approximately hexagonal (also known as sigma Σ), the top surface of the epitaxial layer 40 is preferably slightly higher than the surface of the substrate 12, and the sidewall of the epitaxial layer 40 preferably forms a protrusion 42 at the inclined surface 38 formed above, wherein the protrusion 42 is preferably approximately sawtooth-shaped and extends toward both sides of the epitaxial layer 40.

In a preferred embodiment of the present invention, the epitaxial layer 40 may have different materials according to different types of MOS transistors. For example, if the MOS transistor is a P-type transistor (PMOS), the epitaxial layer 40 may include germanium silicide (SiGe), germanium boron silicide (SiGeB) or germanium tin silicide (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type transistor (NMOS), the epitaxial layer 40 may include silicon carbide (SiC), silicon carbon phosphide (SiCP) or silicon phosphide (SiP). In addition, the selective epitaxial process can be formed in a single layer or multiple layers, and its foreign atoms (such as germanium atoms or carbon atoms) can also be changed in a gradual manner, but it is better to make the surface of the epitaxial layer 40 lighter or without germanium atoms to facilitate the subsequent formation of the metal silicide layer.

An ion implantation process is then performed to form a source/drain region 44 on a portion or all of the epitaxial layer 40. In another embodiment, the formation of the source/drain region 44 can also be performed in-situ in a selective epitaxial growth process, such as when the metal oxide semiconductor is a PMOS, forming a germanium silicon epitaxial layer 40 accompanied by implanting a P-type dopant; or when the metal oxide semiconductor is an NMOS, forming a silicon carbide epitaxial layer 40 accompanied by implanting an N-type dopant. This can omit the subsequent use of an additional ion implantation step to form the source/drain region 44 of the P-type/N-type transistor. In another embodiment, the doping of the source/drain region 44 may also be formed in a gradient manner.

As shown in FIG. 5 , a capping layer 46 is then formed on the epitaxial layer 40 and fills the hole 36. It is worth noting that, since the capping layer 46 made of silicon in this stage preferably grows and extends upward along the sidewall of the sidewall sub-layer 28 made of silicon oxide, and turns to grow when it contacts the heterogeneous interface such as the sidewall sub-layer 30 made of silicon nitride, the capping layer 46 finally formed preferably includes a flat upper surface 48, two inclined sidewalls 50 connected to the flat upper surface 48, and two vertical sidewalls 52 contacting the sidewall sub-layer and respectively connected to the two inclined sidewalls. According to the preferred embodiment of the present invention, the cover layer 46 grown in this way can provide more protection for the cover layer 46, and this design can also reduce the overlap capacitance (capacitance overlap, C _ov ) of the device.

Next, as shown in FIG. 6 , a contact hole etch stop layer (not shown) and an interlayer dielectric layer 54 are sequentially formed on each gate structure 14, 16, and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 54 and part of the contact hole etch stop layer and expose the gate material layer 20 made of polysilicon material, so that the upper surface of each hard mask 22 is flush with the upper surface of the interlayer dielectric layer 54.

A metal gate replacement process is then performed to convert the gate structures 14 and 16 into metal gates. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH ₄ OH) or tetramethylammonium hydroxide (TMAH) to sequentially remove the hard mask 22, the gate material layer 20, and even the gate dielectric layer 18 in the gate structures 14 and 16 to form a groove in the interlayer dielectric layer 54 (not shown). Thereafter, a selective dielectric layer 56 or a gate dielectric layer (not shown), a high dielectric constant dielectric layer 58, a work function metal layer 60 and a low resistance metal layer 62 are sequentially formed in each groove, and then a planarization process is performed, such as using CMP to remove part of the low resistance metal layer 62, part of the work function metal layer 60 and part of the high dielectric constant dielectric layer 58 to form gate structures 14, 16 formed by metal gates 64, 66. Taking the gate structure fabricated by the post high-k dielectric layer process in the present embodiment as an example, each gate structure 14 , 16 preferably includes a dielectric layer 56 or a gate dielectric layer (not shown), a U-shaped high-k dielectric layer 58 , a U-shaped work function metal layer 60 and a low-resistance metal layer 62 .

In the present embodiment, the high-k dielectric layer 58 includes a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT), barium strontium titanate (BaxSr _1-x TiO ₃ , BST), or a combination thereof.

The work function metal layer 60 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 60 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), tantalum aluminum (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 60 may be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 60 and the low resistance metal layer 58, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 62 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof.

Thereafter, part of the high dielectric constant dielectric layer 58, part of the work function metal layer 60 and part of the low resistance metal layer 62 may be selectively removed to form a groove (not shown), and then a hard mask 68 is filled into the groove and made flush with the surface of the interlayer dielectric layer 54, wherein the hard mask 68 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.

A contact plug process may then be performed to form contact plugs 70 that are electrically connected to the source/drain regions 44. In the present embodiment, the contact plugs 70 may be formed by first removing a portion of the interlayer dielectric layer 54 and a portion of the contact hole etch stop layer to form a contact hole (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact hole. A planarization process, such as CMP, is then used to remove a portion of the metal layer, a portion of the barrier layer, and even a portion of the interlayer dielectric layer 54 to form a contact plug 70 in the contact hole, wherein the upper surface of the contact plug 70 is preferably aligned with the upper surface of the interlayer dielectric layer 54. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum and copper, but is not limited thereto.

Please refer to FIG. 6 and FIG. 7 again, which are schematic diagrams of the structure of a semiconductor device according to different embodiments of the present invention. As shown in FIG. 6 and FIG. 7, the semiconductor device mainly includes gate structures 14 and 16 disposed on the substrate 12, sidewalls 26 disposed beside the gate structures 14 and 16, sidewalls 28 disposed on the sidewalls of the sidewalls 26, sidewalls 30 disposed on the sidewalls of the sidewalls 28, epitaxial layers 40 disposed on both sides of the gate structures 14 and 16, and a capping layer 46 disposed on the epitaxial layer 40.

From a detailed perspective, the side wall 26 of FIG. 6 includes an I-shaped cross-section, the side wall 28 includes an L-shaped cross-section, and the side wall 30 includes an I-shaped cross-section, wherein the lower surface of the side wall 30 is preferably higher than the lower surfaces of the side walls 26 and 28, and the lower surfaces of the side walls 26 and 28 are aligned with the lower surfaces of the gate structures 14 and 16, respectively. It should be noted that, although the side wall 28 disposed in the middle in this embodiment presents an L-shaped cross-section, according to an embodiment of the present invention, as shown in FIG. 7 , the side wall 28 disposed in the middle can also present an I-shaped cross-section like the left and right side walls 26 and 30, and in this case, the inner side wall of the side wall 30 disposed on the outer side is aligned with the outer side wall of the middle side wall 28, and the side wall 30 preferably does not straddle the side wall 28, and the lower surface of the side wall 30 is still higher than the lower surface of the side wall 28.

From the material perspective, the three sidewalls 26, 28, and 30 preferably include different materials, wherein the middle sidewall 28 preferably includes silicon oxide, the outer sidewall 30 preferably includes silicon nitride, and the inner sidewall 26 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride carbide according to process requirements.

In addition, the top surface of the epitaxial layer 40 is preferably slightly higher than the surface of the substrate 12, and the side wall of the epitaxial layer 40 preferably forms a protrusion 42 at the inclined surface 38 formed above, wherein the protrusion 42 and the side wall of the epitaxial layer 40 are preferably roughly saw-toothed and extend toward both sides of the epitaxial layer 40. In addition, the cover layer 46 disposed above the epitaxial layer 40 preferably includes a flat upper surface 48, two inclined side walls 50 connected to the flat upper surface 48, and two vertical side walls 52 contacting the side wall of the side wall sub-28 and respectively connected to the two inclined side walls 50. Since the covering layer 46 preferably penetrates directly below the side wall 30, a portion of the covering layer 46 preferably contacts the side wall 28 and the side wall 30 at the same time. In addition, compared with the two vertical side walls 52 of the covering layer 46 in FIG. 6 that do not align with the side walls of the side walls 28 and 30, the two vertical side walls 52 of the covering layer 46 in the embodiment of FIG. 7 preferably align with the outer side wall of the side wall 28.

Please refer to FIG. 8, which further discloses a schematic diagram of the structure of a semiconductor element of an embodiment of the present invention. As shown in FIG. 8, compared with the aforementioned embodiment in which the cover layer 46 includes a flat upper surface 48, two inclined side walls 50 connected to the flat upper surface, and two vertical side walls 52 contacting the side walls of the side wall sub-28, the present embodiment can slightly adjust the gas flow rate or formula when forming the cover layer 46 so that the cover layer 46 only includes a flat upper surface 48 and two inclined side walls 50 connected to the flat upper surface 48, and the two inclined side walls 50 preferably directly contact the side wall sub-28. Thus, the overall volume of the cover layer 46 of the present embodiment can be significantly smaller than that of the cover layer 46 of the previous embodiment, which means that the concentration of dopants such as boron in the cover layer 46 can be reduced accordingly, thereby improving the overlap capacitance (capacitance overlap, _Cov ) of the device. The above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

12: substrate                                       14: gate structure 16: gate structure                                18: gate dielectric layer 20: gate material layer                            22: hard mask 24: lightly doped drain                            26: sidewall 28: sidewall                                   30: sidewall 32: groove                                       34: cleaning process 36: hole                                     38: inclined surface 40: epitaxial layer                               42: protrusion 44: Source/Drain Region                         46: Capping Layer 48: Flat Top Surface                            50: Inclined Sidewalls 52: Vertical Sidewalls                           54: Interlayer Dielectric Layer 56: Dielectric Layer                                   58: High K Dielectric Layer 60: Work Function Metal Layer                         62: Low Impedance Metal Layer 64: Metal Gate                                66: Metal Gate 68: Hard Mask                               70: Contact Plug

Figures 1 to 6 are schematic diagrams of a method for manufacturing a semiconductor element according to a preferred embodiment of the present invention. Figure 7 is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention. Figure 8 is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention.

12: Base

14: Gate structure

16: Gate structure

24: Lightly doped drain

26: Sidewall

28: Sidewall

30: Sidewall

38: Inclined surface

40: Epitaxial layer

42: protrusion

44: Source/drain region

46: Covering layer

48: Flat upper surface

50: Leaning sidewall

52: Vertical side wall

54: Interlayer dielectric layer

56: Dielectric layer

58: High dielectric constant dielectric layer

60: Work function metal layer

62: Low impedance metal layer

64:Metal gate

66:Metal gate

68: Hard mask

70: Contact plug

Claims (13)

A semiconductor element comprises: A gate structure is disposed on a substrate; A first sidewall and a second sidewall surround the gate structure, wherein the substrate comprises an inclined surface directly connected to the second sidewall; An epitaxial layer is disposed on both sides of the gate structure and covers the inclined surface; and A cover layer is disposed on the epitaxial layer, wherein the cover layer comprises a flat upper surface and an inclined sidewall connected to the flat upper surface. The semiconductor element as described in item 1 of the patent application scope further comprises: The first sidewall is arranged beside the gate structure; The second sidewall is arranged on the outer sidewall of the first sidewall; and A third sidewall is arranged on the outer sidewall of the second sidewall. A semiconductor device as described in item 2 of the patent application, wherein the first side wall comprises an I shape, the second side wall comprises an L shape, and the third side wall comprises an I shape. A semiconductor device as described in item 3 of the patent application, wherein the lower surface of the third side wall is higher than the lower surface of the second side wall. A semiconductor device as described in item 3 of the patent application, wherein the lower surface of the first side wall is aligned with the lower surface of the gate structure. A semiconductor device as described in item 3 of the patent application, wherein the lower surface of the second side wall is aligned with the lower surface of the gate structure. A semiconductor device as described in claim 2, wherein the second sidewall comprises silicon oxide and the third sidewall comprises silicon nitride. As described in item 2 of the patent application scope, the cover layer directly contacts the second side wall and the third side wall. A semiconductor device as described in claim 1, wherein the capping layer comprises silicon. As described in item 1 of the patent application scope, the cover layer further includes a vertical side wall connected to the inclined side wall. A semiconductor device as described in item 2 of the patent application, wherein the third side wall sub-outer side wall is not aligned with the second side wall sub-outer side wall. As described in item 2 of the patent application scope, the side wall of the epitaxial layer forms a protrusion at the inclined surface, a part of the protrusion covers the inclined surface, and the protrusion is saw-toothed and extends outward. As described in item 2 of the patent application scope, the cover layer directly contacts the second side wall and the third side wall, and the cover layer further includes a vertical side wall connected to the inclined side wall.

Images