[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI473218B - 穿孔中介板及其製法與封裝基板及其製法 - Google Patents

穿孔中介板及其製法與封裝基板及其製法 Download PDF

Info

Publication number
TWI473218B
TWI473218B TW101126991A TW101126991A TWI473218B TW I473218 B TWI473218 B TW I473218B TW 101126991 A TW101126991 A TW 101126991A TW 101126991 A TW101126991 A TW 101126991A TW I473218 B TWI473218 B TW I473218B
Authority
TW
Taiwan
Prior art keywords
layer
interposer
conductive paste
conductive
line
Prior art date
Application number
TW101126991A
Other languages
English (en)
Other versions
TW201405734A (zh
Inventor
Tzyy Jang Tseng
Dyi Chung Hu
Ying Chih Chan
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW101126991A priority Critical patent/TWI473218B/zh
Priority to US13/845,625 priority patent/US8981570B2/en
Publication of TW201405734A publication Critical patent/TW201405734A/zh
Application granted granted Critical
Publication of TWI473218B publication Critical patent/TWI473218B/zh
Priority to US14/641,887 priority patent/US9337136B2/en
Priority to US14/641,901 priority patent/US9460992B2/en
Priority to US14/641,918 priority patent/US9224683B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

穿孔中介板及其製法與封裝基板及其製法
　　本發明係有關一種矽穿孔技術，尤指一種穿孔中介板及其製法與封裝基板及其製法。
　　隨著電子產業的蓬勃發展，電子產品在型態上趨於輕薄短小，在功能上則逐漸邁入高性能、高功能、高速度化的研發方向。第1圖係為習知覆晶式封裝結構1之剖視示意圖。
　　如第1圖所示，該封裝結構1之製程係先提供一具有第一表面10a及第二表面10b之封裝基板10，且於該封裝基板10之第一表面10a具有覆晶焊墊100；再藉由焊錫凸塊11電性連接半導體晶片12之電極墊120；接著，於該封裝基板10之第一表面10a與該半導體晶片12之間形成底膠13，以包覆該焊錫凸塊11；又於該封裝基板10之第二表面10b具有植球墊101，以藉由焊球14電性連接例如為印刷電路板之另一電子裝置(未表示於圖中)。
　　惟，該半導體晶片12已發展至關鍵尺寸為45nm以下之製程，故於後端製程(Back-End Of Line, BEOL)中，將採用極低介電係數(Extreme low-k dielectric, ELK)或超低介電係數(Ultra low-k, ULK)之介電材料，但該low-k之介電材料為多孔特性而易脆，以致於習知封裝結構1中，當進行覆晶封裝後，在信賴度熱循環測試中，將因該封裝基板10與該半導體晶片12之間的熱膨脹係數(thermal expansion coefficient, CTE)差異過大，導致該焊錫凸塊11易因熱應力不均而產生破裂，使該半導體晶片12產生破裂，造成產品可靠度不佳。
　　再者，隨著電子產品更趨於輕薄短小及功能不斷提昇之需求，該半導體晶片12之佈線密度愈來愈高，以奈米尺寸作單位，因而各該電極墊120之間的間距更小；然，習知封裝基板10之覆晶焊墊100之間距係以微米尺寸作單位，而無法有效縮小至對應該電極墊120之間距的大小，導致雖有高線路密度之半導體晶片12，卻未有可配合之封裝基板，以致於無法有效生產電子產品。
　　因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之缺失，遂於該封裝基板與半導體晶片之間增設一中介板（interposer），該中介板具有穿孔（Through-silicon via, TSV）及設於該穿孔上之線路重佈層（Redistribution layer, RDL），令該穿孔之一端電性結合間距較大之封裝基板之覆晶焊墊，而該線路重佈層電性結合間距較小之半導體晶片之電極墊，使該封裝基板可結合具有高佈線密度電極墊之半導體晶片，而達到整合高佈線密度之半導體晶片之目的。
　　本發明係提供一種穿孔中介板，係包括：一中介板本體，係具有相對之第一表面與第二表面，並具有連通該第一表面與該第二表面之複數貫穿孔；導電膠體，係形成於該貫穿孔中，且該導電膠體具有相對之第一端與第二端，該導電膠體之該第一端係凸出該中介板本體之該第一表面；以及線路重佈結構，係設於該中介板本體之該第二表面與該導電膠體之該第二端上，且該線路重佈結構電性連接該導電膠體之該第二端。
　　由上可知，本發明之穿孔中介板，係藉由該導電膠體之第一端凸出該中介板本體之第一表面，以增加該導電膠體之第一端與其它結構（如封裝基板或線路結構）的接觸面積，而強化該導電膠體之結合力，故可提升本發明之穿孔中介板之可靠度。
　　再者，本發明亦提供一種封裝基板，係包括：中介板，係具有相對之第一表面與第二表面，並具有連通該第一表面與該第二表面之複數導電膠體，該導電膠體具有相對之第一端與第二端，令該導電膠體之該第一端凸出該中介板之該第一表面，又該中介板之該第二表面上具有線路重佈結構，令該線路重佈結構電性連接該導電膠體之該第二端；封裝層，係包覆該中介板周圍及該第一表面；以及線路增層結構，係對應設於該中介板之該第一表面上方之該封裝層上，且令該線路增層結構電性連接該導電膠體之該第一端。
　　由上可知，本發明之封裝基板係藉由將該中介板嵌埋於該封裝層中，以降低整體封裝結構之厚度，且該中介板之熱膨脹係數與矽晶圓接近或者相同，可提高封裝後熱循環測試的信賴度，故相較於習知技術之覆晶式封裝基板，將半導體晶片結合於該封裝基板之中介板上，可提升產品之可靠度。
　　另外，本發明復提供該穿孔中介板之製法與該封裝基板之製法，如下所述。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。　
　　須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“頂”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
　　第2A至2H圖係為本發明之穿孔中介板(interposer)2之製法之剖視示意圖。
　　如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b之中介板本體20，且該第一與第二表面20a,20b上分別具有一第一與第二保護層200a,200b。
　　於本實施例中，該中介板本體20係為半導體材質之板體，如單晶矽、多晶矽、砷化鎵等，或為絕緣材質之板體，如玻璃、陶瓷如Al2 O3 或AlN等。
　　如第2B圖所示，形成連通該中介板本體20之第一與第二表面20a,20b且延伸至該第一保護層200a與該第二保護層200b之複數貫穿孔200。
　　如第2C圖所示，於各該貫穿孔200中形成導電膠體21，且該些導電膠體21具有相對之第一端21a與第二端21b。
　　於本實施例中，該導電膠體21係藉由塗佈填膠方式形成，且該導電膠體21之材質係為銅膠或複合銅（化鍍銅與銅膠）。
　　再者，若該中介板本體20為半導體材質時，可先於各該貫穿孔200之孔壁上形成例如二氧化矽的絕緣層（圖略），再形成該導電膠體21。
　　如第2D圖所示，移除該第一保護層200a，使該導電膠體21之第一端21a凸出該中介板本體20之第一表面20a。
　　如第2E圖所示，於該中介板本體20之第一表面20a與該導電膠體21之第一端21a上形成第一線路重佈結構22，且該第一線路重佈結構22電性連接該導電膠體21之第一端21a。
　　於本實施例中，該第一線路重佈結構22具有至少一重佈介電層220、及形成於該重佈介電層220上之重佈線路層221,221’，且部分該重佈線路層221’係電性連接該導電膠體21之第一端21a。
　　再者，該重佈線路層221係埋設於該重佈介電層220中。於其它實施例中，該重佈線路層221亦可形成於該重佈介電層220表面上。
　　又，該第一線路重佈結構22復具有形成於該重佈介電層220中之複數重佈導電盲孔222，且該重佈導電盲孔222係電性連接該重佈線路層221與該導電膠體21之第一端21a。亦即，本製程藉由線路溝槽之設計，使該第一線路重佈結構22可以該重佈導電盲孔222或該重佈線路層221’電性連接該導電膠體21之第一端21a，並無特別限制。
　　另外，於其它實施例中，該第一線路重佈結構22可為多層線路，而並不侷限於上述之單層線路。
　　如第2F圖所示，移除該第二保護層200b，使該導電膠體21之第二端21b外露於該中介板本體20之第二表面20b，且該導電膠體21之第二端21b係凸出該中介板本體20之第二表面20b。
　　如第2G圖所示，於該中介板本體20之第二表面20b與該導電膠體21之第二端21b上形成第二線路重佈結構24，且該第二線路重佈結構24電性連接該導電膠體21之第二端21b。
　　於本實施例中，該第二線路重佈結構24具有至少一重佈介電層240、及形成於該重佈介電層240上之重佈線路層241,241’，且部分該重佈線路層241’（即最內層）電性連接該導電膠體21之第二端21b。
　　再者，該第二線路重佈結構24復具有形成於部分該重佈介電層240中之複數重佈導電盲孔242，且該重佈導電盲孔242係電性連接該重佈線路層241,241’。
　　又，最內層之重佈介電層240之表面係與該導電膠體21之第二端21b表面齊平，使最內層之重佈線路層241’可直接接觸該導電膠體21之第二端21b表面，而能電性連接該導電膠體21之第二端21b，故最內層之重佈線路層241’不需透過該重佈導電盲孔242電性連接該導電膠體21之第二端21b。或者，最內層之重佈介電層240之表面係低於（圖未示）該導電膠體21之第二端21b表面，使該導電膠體21之第二端21b嵌入（圖未示）於最內層之重佈線路層241’。
　　另外，於該第二線路重佈結構之其它態樣中，該重佈線路層亦可嵌埋於該重佈介電層中。
　　如第2H圖所示，進行切單製程，即沿第2G圖所示之切割路徑L，以獲得複數個穿孔中介板2。
　　如第2H’圖所示，一般銅膠於成型柱體後具有孔洞結構，該孔洞結構於後續製程中容易殘留藥水並影響導電品質，故於另一實施例中，可於第2E圖之形成該第一線路重佈結構22的製程之前，於該導電膠體21之第一端21a上形成表面處理層210，以遮蓋該孔洞結構。
　　於本實施例中，該表面處理層210之厚度大於3um，且形成該表面處理層210之材質係為化學鍍鎳/金(Ni/Au)、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、或化鍍與電鍍銅合體之其中一者。
　　如第2I圖所示，係應用本發明所形成之封裝結構。於後續製程中，一半導體晶片4藉由第一焊錫凸塊40結合並電性連接該穿孔中介板2之第二線路重佈結構24最外側之電性接觸墊243，且於該穿孔中介板2之第一線路重佈結構22最外側之電性接觸墊223上藉由第二焊錫凸塊25電性連接封裝基板（圖略）。
　　本發明之穿孔中介板2,2’係設於該封裝基板與半導體晶片4之間，令該穿孔中介板2,2’之底端藉由第二焊錫凸塊25電性結合間距較大之封裝基板之焊墊，而該第二線路重佈結構24之電性接觸墊243藉由第一焊錫凸塊40電性結合間距較小之半導體晶片4之電極墊，再形成封裝膠體（圖略），使該封裝基板可結合具有高佈線密度電極墊之半導體晶片4，而達到整合高佈線密度之半導體晶片4之目的。故藉由該穿孔中介板2,2’，不僅可解決缺乏可配合之封裝基板的問題，且不會改變IC產業原本之供應鏈(supply chain)及基礎設備(infrastructure)。
　　再者，藉由該半導體晶片4設於該穿孔中介板2,2’上，且該穿孔中介板2,2’之熱膨脹係數與半導體晶片4之熱膨脹係數相同(CET均為2.6ppm)或相近，故可避免該半導體晶片4與該穿孔中介板2,2’之間的第一焊錫凸塊40破裂。因此，相較於習知技術之覆晶式封裝基板，將半導體晶片4結合於該穿孔中介板2,2’上，可提升產品之可靠度。
　　又，藉由該導電膠體21之第一端21a凸出該中介板本體20之第一表面20a，使該第一線路重佈結構22接觸該導電膠體21之第一端21a的面積得以增加，進而強化該導電膠體21與該第一線路重佈結構22之結合力，例如，該導電膠體21之第一端21a嵌入該重佈線路層221’或該重佈導電盲孔222。因此，可提升本發明之穿孔中介板2,2’之可靠度。
　　另外，該導電膠體21之第二端21b亦凸出該中介板本體20之第二表面20b，故亦能增加該第二線路重佈結構24與該導電膠體21之第二端21b之接觸面積，以強化該導電膠體21與該第二線路重佈結構24之結合力，因而可提升本發明之穿孔中介板2,2’之可靠度。
　　本發明復提供一種穿孔中介板2,2’，如第2H圖所示，係包括：一中介板本體20、複數導電膠體21、一第一線路重佈結構22以及一第二線路重佈結構24。
　　所述之中介板本體20係具有相對之第一表面20a與第二表面20b，並具有連通該第一與第二表面20a,20b之複數貫穿孔。
　　所述之導電膠體21係形成於該貫穿孔200中，且該導電膠體21具有相對之第一端21a與第二端21b，該導電膠體21之第一端21a係凸出該中介板本體20之第一表面20a，且該導電膠體21之第二端21b亦凸出該中介板本體20之第二表面20b。又於其它實施例中，該導電膠體21之第一端21a上係具有表面處理層210。
　　所述之第一線路重佈結構22係設於該中介板本體20之第一表面20a與該導電膠體21之第一端21a上，且該第一線路重佈結構22具有至少一重佈介電層220、形成於該重佈介電層220上之重佈線路層221,221’、及形成於該重佈介電層220中並電性連接部分該重佈線路層221之複數重佈導電盲孔222，且部分重佈線路層221’係電性連接該導電膠體之第一端，而部分重佈線路層221係藉由該重佈導電盲孔222電性連接該該導電膠體21之第一端21a。又於一實施例中，該重佈線路層221,221’係埋設於該重佈介電層220中。
　　所述之第二線路重佈結構24係設於該中介板本體20之第二表面20b與該導電膠體21之第二端21b上，且該第二線路重佈結構24具有至少一重佈介電層240、形成於該重佈介電層240上之重佈線路層241,241’、及形成於部分該重佈介電層240中並電性連接該重佈線路層241,241’之複數重佈導電盲孔242，且部分該重佈線路層241’電性連接該導電膠體21之第二端21b。
　　第3A至3J圖係為本發明之嵌埋有中介板3a之封裝基板3之製法之剖視示意圖。
　　如第3A圖所示，提供一具有相對之第一表面30a與第二表面30b之中介板本體30，且該中介板本體30之第一表面30a上具有保護層300a。
　　接著，形成連通該中介板本體30之第一與第二表面30a,30b且延伸至該保護層300a之複數貫穿孔300。
　　於本實施例中，該中介板本體30之材質選擇性同於前述實施例。
　　如第3B圖所示，於各該貫穿孔300中形成導電膠體31，且該些導電膠體31具有相對之第一端31a與第二端31b。
　　於本實施例中，該導電膠體31係藉由塗佈填膠方式形成，且該導電膠體31之第二端31b表面係與該中介板本體30之第二表面30b齊平。
　　如第3C圖所示，於該中介板本體30之第二表面30b上形成一線路重佈結構34，以形成複數個中介板3a，且該線路重佈結構34係電性連接該導電膠體31之第二端31b。
　　於本實施例中，該線路重佈結構34具有至少一重佈介電層340、及形成於該重佈介電層340上之重佈線路層341,341’，且部分該重佈線路層341’（即最內層）電性連接該導電膠體31之第二端31b。
　　再者，該線路重佈結構34復具有形成於該重佈介電層340中之複數重佈導電盲孔342，且該重佈導電盲孔342係電性連接該重佈線路層341,341’。
　　又，該導電膠體31之第二端31b表面與該中介板本體30之第二表面30b齊平，故最內層之重佈線路層341’可直接接觸該導電膠體31之第二端31b表面，而電性連接該導電膠體31之第二端31b，因而最內層之重佈線路層341’不需透過該重佈導電盲孔342電性連接該導電膠體31之第二端31b。
　　另外，該重佈線路層亦可嵌埋於該重佈介電層中。
　　如第3D圖所示，沿該中介板3a之邊緣（如第3C圖所示之切割路徑S）進行切割製程，以分離各該中介板3a。
　　如第3E圖所示，將該些中介板3a設於一承載件5之相對兩側5a,5b上，且以該線路重佈結構34面對該承載件5。之後，再移除該保護層300a，使該導電膠體31之第一端31a凸出該中介板3a之第一表面30a。
　　於本實施例中，於該承載件5同一側5a,5b上之該些中介板3a，其兩者之間具有間隔D。
　　如第3F圖所示，於該承載件5上形成封裝層33，以包覆該中介板3a周圍及其第一表面30a與該導電膠體31之第一端31a。
　　如第3G至3H圖所示，於對應該中介板3a之第一表面30a上方之封裝層33上形成一線路增層結構32，以形成兩組封裝基板單元3b，且該線路增層結構32電性連接該導電膠體31之第一端31a。
　　於本實施例中，該線路增層結構32具有至少一增層介電層320、形成於該增層介電層320上之增層線路層321、及形成於該增層介電層320中之複數增層導電盲孔322，且該增層導電盲孔322係電性連接該增層線路層321。
　　再者，部分增層線路層321’復埋設於該封裝層33中，如第3G圖所示，使該線路增層結構32藉由該封裝層33中之增層線路層321’電性連接該導電膠體31之第一端31a。於其它實施例中，可於第3F圖之製程中，使該導電膠體31之第一端31a表面與該封裝層33表面齊平，以於製作該線路增層結構32時，該增層線路層321”可形成於該封裝層33表面上，如第3G’圖所示，以電性連接該導電膠體31之第一端31a。
　　又，該增層線路層321係埋設於該增層介電層320中。於其它實施例中，該增層線路層321亦可形成於該增層介電層320表面上。
　　另外，該線路增層結構32與該線路重佈結構34係具有製程上之差異。該線路增層結構32係使用封裝基板製程之設備製作，而該線路重佈結構34係使用半導體晶圓製程之設備製作。
　　如第3I圖所示，移除該承載件5，以取得由多數封裝基板單元3b所排列成之整版面(panel)封裝基板，沿如切割路徑Y進行切單製程，以取得複數個封裝基板3。
　　如第3J圖所示，係應用本發明所形成之封裝結構：於後續製程中，至少一半導體晶片4藉由焊錫凸塊41結合並電性連接該封裝基板3之線路重佈結構34最外側之重佈線路層341部分表面（即覆晶焊墊），且於該封裝基板3之線路增層結構32最外側之增層線路層321部分表面（即植球墊）上藉由焊球35電性連接例如為印刷電路板之電子裝置（圖略）。
　　本發明之封裝基板3係藉由將該中介板3a嵌埋於該封裝層33中，以降低整體封裝結構之厚度。
　　再者，該封裝基板3與該中介板3a之間係藉由該線路增層結構32作電性連接，不僅能節省製作成本，且能提高電性。
　　又，該中介板3a之熱膨脹係數與矽晶圓接近或者相同，可提高封裝後熱循環測試的信賴度，故相較於習知技術之覆晶式封裝基板，將半導體晶片4結合於該封裝基板3之中介板3a上，可提升產品之可靠度。
　　另外，藉由該導電膠體31之第一端31a凸出該中介板3a之第一表面30a，使該線路增層結構32之增層線路層321’能直接接觸該導電膠體31之第一端31a，而不需藉由該增層導電盲孔322接觸該導電膠體31之第一端31a，故可省略盲孔對位製程以縮短製程時間，且可避免盲孔偏移而使電性連接不良之問題。因此，本發明之嵌埋有中介板3a之封裝基板3不僅可提升其可靠度，且可降低製作成本。
　　本發明復提供一種封裝基板3，如第3J圖所示，係包括：一中介板3a、一封裝層33以及線路增層結構32。
　　所述之中介板3a係具有相對之第一表面30a與第二表面30b，並具有連通該第一與第二表面30a,30b之複數導電膠體31，該導電膠體31具有相對之第一端31a與第二端31b，令該導電膠體31之第一端31a凸出該中介板3a之第一表面30a，又該中介板3a之第二表面30b上具有線路重佈結構34，令該線路重佈結構34電性連接該導電膠體31之第二端31b。
　　於本實施例中，該線路重佈結構34具有至少一重佈介電層340、形成於該重佈介電層340上之重佈線路層341,341’、及形成於該重佈介電層340中並電性連接該重佈線路層341,341’之複數重佈導電盲孔342，且該最內層之重佈線路層341’電性連接該導電膠體31之第二端31b。
　　所述之封裝層33係包覆該中介板3a周圍及該中介板3a之第一表面30a，亦即該中介板3a嵌埋於該封裝層33中。
　　於本實施例中，該封裝層33復包覆該導電膠體31之第一端31a頂面；於其它實施例中，該導電膠體31之第一端31a頂面係外露於該封裝層33表面，例如，該導電膠體31之第一端31a表面與該封裝層33表面齊平。
　　所述之線路增層結構32係對應設於該中介板3a之第一表面30a上方之封裝層33上，且令該線路增層結構32電性連接該導電膠體31之第一端31a。
　　於本實施例中，該線路增層結構32具有至少一增層介電層320、形成於該增層介電層320上之增層線路層321、及形成於該增層介電層320中並電性連接該增層線路層321之複數增層導電盲孔322，且該增層線路層321’復埋設於該封裝層33中，以電性連接該導電膠體31之第一端31a與增層導電盲孔322。於其它實施例中，該增層線路層321”可形成於該封裝層33表面上，以電性連接該導電膠體31之第一端31a。
　　綜上所述，本發明之穿孔中介板及其製法與封裝基板及其製法，主要藉由該導電膠體之第一端凸出該中介板之第一表面，以達到提升該穿孔中介板或封裝基板之可靠度。
　　再者，利用該穿孔中介板（或中介板）結合半導體晶片，因該穿孔中介板之熱膨脹係數與半導體晶片之熱膨脹係數相同，故可避免該半導體晶片與該穿孔中介板之間的焊錫凸塊破裂。因此，該穿孔中介板可提升產品之可靠度。
　　又，藉由穿孔中介板（或中介板）之設計，令該第一線路重佈結構（或線路增層結構）電性結合封裝基板的焊墊，而該第二線路重佈結構（或線路重佈結構）電性結合間距較小之半導體晶片電極墊，俾使該封裝基板可結合具有高佈線密度電極墊之半導體晶片，而達到封裝超低介電、細線路間距之半導體晶片之目的。
　　另外，將該中介板嵌埋於該封裝層中，以形成嵌埋有中介板之封裝基板，進而降低整體封裝結構之厚度。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1．．．封裝結構
10,3．．．封裝基板
10a,20a,30a．．．第一表面
10b,20b,30b．．．第二表面
100．．．覆晶焊墊
101．．．植球墊
11,41．．．焊錫凸塊
12,4．．．半導體晶片
120．．．電極墊
13．．．底膠
14,35．．．焊球
2,2’．．．穿孔中介板
20,30．．．中介板本體
200,300．．．貫穿孔
200a．．．第一保護層
200b．．．第二保護層
21,31．．．導電膠體
21a,31a．．．第一端
21b,31b．．．第二端
210．．．表面處理層
22．．．第一線路重佈結構
220,240,340．．．重佈介電層
221,221’,241,241’,341,341’．．．重佈線路層
222,242,342．．．重佈導電盲孔
223,243．．．電性接觸墊
24．．．第二線路重佈結構
25．．．第二焊錫凸塊
3a．．．中介板
3b．．．封裝基板單元
300a．．．保護層
32．．．線路增層結構
320．．．增層介電層
321,321’,321”．．．增層線路層
322．．．增層導電盲孔
33．．．封裝層
34．．．線路重佈結構
40．．．第一焊錫凸塊
5．．．承載件
5a,5b．．．兩側
L,S,Y．．．切割路徑
D．．．間隔
　　第1圖係為習知覆晶式半導體封裝結構的剖視示意圖；
　　第2A至2H圖係為本發明穿孔中介板之製法的剖視示意圖；其中，第2H’圖係為第2H圖之不同實施例；
　　第2I圖係為本發明穿孔中介板之後續應用的剖視示意圖；以及
　　第3A至3J圖係為本發明封裝基板之製法的剖視示意圖；其中，第3G’圖係為第3G圖之不同實施例。
2．．．穿孔中介板
20．．．中介板本體
20a．．．第一表面
20b．．．第二表面
21．．．導電膠體
21a．．．第一端
21b．．．第二端
22．．．第一線路重佈結構
220,240．．．重佈介電層
221,241,241’．．．重佈線路層
222,242．．．重佈導電盲孔
24．．．第二線路重佈結構

Claims (22)

  1. 一種穿孔中介板，係包括：一中介板本體，係具有相對之第一表面與第二表面，並具有連通該第一表面與該第二表面之複數貫穿孔；導電膠體，係形成於該貫穿孔中，且該導電膠體具有相對之第一端與第二端，該導電膠體之該第一端係凸出該中介板本體之該第一表面；以及第二線路重佈結構，係設於該中介板本體之該第二表面與該導電膠體之該第二端上，且該第二線路重佈結構具有內層重佈線路層直接接觸該導電膠體之該第二端。
  2. 如申請專利範圍第1項所述之穿孔中介板，其中，該第二線路重佈結構復具有形成於該內層重佈線路層上之至少一重佈介電層、及形成於該重佈介電層上之外層重佈線路層，且該外層重佈線路層電性連接該導電膠體之該第二端。
  3. 如申請專利範圍第2項所述之穿孔中介板，其中，該第二線路重佈結構復具有形成於該重佈介電層中之複數重佈導電盲孔，且該重佈導電盲孔係電性連接該外層重佈線路層及該內層重佈線路層。
  4. 如申請專利範圍第1項所述之穿孔中介板，其中，該導電膠體之該第二端係凸出該中介板本體之該第二表面。
  5. 如申請專利範圍第1項所述之穿孔中介板，復包括第一線路重佈結構，係設於該中介板本體之該第一表面與該 導電膠體之該第一端上，且該第一線路重佈結構電性連接該導電膠體之該第一端。
  6. 如申請專利範圍第5項所述之穿孔中介板，其中，該第一線路重佈結構具有至少一重佈介電層、及形成於該重佈介電層上之重佈線路層，且該重佈線路層電性連接至該導電膠體之該第一端。
  7. 如申請專利範圍第6項所述之穿孔中介板，其中，該第一線路重佈結構復具有形成於該重佈介電層中之複數重佈導電盲孔，且該重佈導電盲孔係電性連接該重佈線路層與該導電膠體之該第一端。
  8. 如申請專利範圍第1項所述之穿孔中介板，其中該導電膠體之該第一端上係具有表面處理層。
  9. 一種穿孔中介板之製法，係包括：提供一具有相對之第一表面與第二表面之中介板本體，且該第一表面與該第二表面上分別具有第一保護層與第二保護層：形成連通該中介板本體之該第一表面與該第二表面且延伸至該第一保護層之複數貫穿孔；於該貫穿孔中形成導電膠體，且該導電膠體具有相對之第一端與第二端；移除該第一保護層，使該導電膠體之該第一端凸出該中介板本體之該第一表面；於該中介板本體之該第一表面與該導電膠體之該第一端上形成第一線路重佈結構，且該第一線路重佈結構電性連接該導電膠體之該第一端；以及移除該第二保護層，使該導電膠體之該第二端外露 於該中介板本體之該第二表面。
  10. 如申請專利範圍第9項所述之穿孔中介板之製法，其中，該貫穿孔復延伸至該第二保護層，且於移除該第二保護層後，該導電膠體之該第二端係凸出該中介板本體之該第二表面。
  11. 如申請專利範圍第9項所述之穿孔中介板之製法，復包括於移除該第二保護層後，於該中介板本體之該第二表面與該導電膠體之該第二端上形成第二線路重佈結構，且該第二線路重佈結構電性連接該導電膠體之該第二端。
  12. 如申請專利範圍第9項所述之穿孔中介板之製法，復包括於形成該第一線路重佈結構前，於該導電膠體之該第一端上形成表面處理層。
  13. 一種封裝基板，係包括：中介板，係具有相對之第一表面與第二表面，並具有連通該第一表面與該第二表面之複數導電膠體，該導電膠體具有相對之第一端與第二端，令該導電膠體之該第一端凸出該中介板之該第一表面，又該中介板之該第二表面上具有線路重佈結構，令該線路重佈結構電性連接該導電膠體之該第二端；封裝層，係包覆該中介板周圍及該第一表面；以及線路增層結構，係對應設於該中介板之該第一表面上方之該封裝層上，且令該線路增層結構直接接觸該導電膠體之該第一端。
  14. 如申請專利範圍第13項所述之封裝基板，其中，該線路增層結構具有至少一增層介電層、及形成於該增層介 電層上之增層線路層，且該增層線路層係電性連接該導電膠體之該第一端。
  15. 如申請專利範圍第14項所述之封裝基板，其中，該增層線路層復埋設於該封裝層中。
  16. 如申請專利範圍第15項所述之封裝基板，其中，該線路增層結構復具有形成於該增層介電層中之複數增層導電盲孔，且該增層導電盲孔電性連接該增層線路層。
  17. 如申請專利範圍第13項所述之封裝基板，其中，該線路重佈結構具有至少一重佈介電層、及形成於該重佈介電層上之重佈線路層，且該重佈線路層電性連接該導電膠體之該第二端。
  18. 如申請專利範圍第17項所述之封裝基板之製法，其中，該線路重佈結構復具有形成於該重佈介電層中之複數重佈導電盲孔，且該重佈導電盲孔係電性連接該重佈線路層。
  19. 一種封裝基板之製法，係包括：提供具有相對之第一表面與第二表面之至少一中介板本體，且該第一表面上具有保護層：形成連通該中介板本體之該第一表面與該第二表面且延伸至該保護層之複數貫穿孔；於該貫穿孔中形成導電膠體，且該導電膠體具有相對之第一端與第二端；於該中介板本體之該第二表面上形成線路重佈結構，以形成中介板，且該線路重佈結構電性連接該導電膠體之該第二端；移除該保護層，使該導電膠體之該第一端凸出該中 介板之該第一表面；形成封裝層以包覆該中介板周圍及該第一表面；以及於對應該中介板之該第一表面上方之該封裝層上形成線路增層結構，且該線路增層結構電性連接該導電膠體之該第一端。
  20. 如申請專利範圍第19項所述之封裝基板之製法，其中，該中介板具有複數個時，係將該些中介板設於一承載件上，且以該線路重佈結構面對該承載件，再移除該保護層。
  21. 如申請專利範圍第20項所述之封裝基板之製法，復包括於形成該線路增層結構後，移除該承載件。
  22. 如申請專利範圍第20項所述之封裝基板之製法，復包括於形成該線路增層結構後，進行切單製程，以形成複數個封裝基板。
TW101126991A 2012-07-26 2012-07-26 穿孔中介板及其製法與封裝基板及其製法 TWI473218B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW101126991A TWI473218B (zh) 2012-07-26 2012-07-26 穿孔中介板及其製法與封裝基板及其製法
US13/845,625 US8981570B2 (en) 2012-07-26 2013-03-18 Through-holed interposer, packaging substrate, and methods of fabricating the same
US14/641,887 US9337136B2 (en) 2012-07-26 2015-03-09 Method of fabricating a through-holed interposer
US14/641,901 US9460992B2 (en) 2012-07-26 2015-03-09 Packaging substrate having a through-holed interposer
US14/641,918 US9224683B2 (en) 2012-07-26 2015-03-09 Method of fabricating packaging substrate having a through-holed interposer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101126991A TWI473218B (zh) 2012-07-26 2012-07-26 穿孔中介板及其製法與封裝基板及其製法

Publications (2)

Publication Number Publication Date
TW201405734A TW201405734A (zh) 2014-02-01
TWI473218B true TWI473218B (zh) 2015-02-11

Family

ID=49994101

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101126991A TWI473218B (zh) 2012-07-26 2012-07-26 穿孔中介板及其製法與封裝基板及其製法

Country Status (2)

Country Link
US (4) US8981570B2 (zh)
TW (1) TWI473218B (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473218B (zh) * 2012-07-26 2015-02-11 Unimicron Technology Corp 穿孔中介板及其製法與封裝基板及其製法
US20140242777A1 (en) * 2013-02-26 2014-08-28 Varughese Mathew Method for Bonding Semiconductor Devices
US9627250B2 (en) * 2013-03-12 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing
US9627285B2 (en) * 2014-07-25 2017-04-18 Dyi-chung Hu Package substrate
US9754849B2 (en) 2014-12-23 2017-09-05 Intel Corporation Organic-inorganic hybrid structure for integrated circuit packages
CN108780785A (zh) * 2016-03-30 2018-11-09 英特尔公司 混合微电子基底
TWI620253B (zh) * 2016-04-26 2018-04-01 Method for manufacturing conductive substrate
US9761535B1 (en) 2016-06-27 2017-09-12 Nanya Technology Corporation Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same
US9748167B1 (en) * 2016-07-25 2017-08-29 United Microelectronics Corp. Silicon interposer, semiconductor package using the same, and fabrication method thereof
US10643936B2 (en) * 2017-05-31 2020-05-05 Dyi-chung Hu Package substrate and package structure
US10687419B2 (en) 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US20190287872A1 (en) * 2018-03-19 2019-09-19 Intel Corporation Multi-use package architecture
EP3841850A4 (en) 2018-08-22 2022-10-26 Liquid Wire Inc. STRUCTURES WITH DEFORMABLE LADDERS
US20200156999A1 (en) 2018-11-16 2020-05-21 United States Gypsum Company Indicator for the sanding of joint compounds and spackles
US10790241B2 (en) 2019-02-28 2020-09-29 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
KR20240009535A (ko) * 2019-05-28 2024-01-22 리퀴드 와이어 인크. 분리형 구조체 및 분리형 센서 구조체
US11094635B2 (en) * 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
CN113035833B (zh) * 2021-05-28 2021-09-28 浙江集迈科微电子有限公司 多层布线转接板及其制备方法
CN113078133A (zh) * 2021-06-03 2021-07-06 浙江集迈科微电子有限公司 多层布线转接板及其制备方法
TWI812977B (zh) * 2021-07-16 2023-08-21 欣興電子股份有限公司 電路板強化結構及其製作方法
JP2023028871A (ja) * 2021-08-20 2023-03-03 新光電気工業株式会社 配線基板及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347513A (ja) * 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20080230264A1 (en) * 2007-03-19 2008-09-25 Mutual-Tek Industries Co., Ltd. Interconnection structure and method thereof
TW200931612A (en) * 2008-01-10 2009-07-16 Phoenix Prec Technology Corp Package substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5283104A (en) * 1991-03-20 1994-02-01 International Business Machines Corporation Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
US6323436B1 (en) * 1997-04-08 2001-11-27 International Business Machines Corporation High density printed wiring board possessing controlled coefficient of thermal expansion with thin film redistribution layer
AU2001234610A1 (en) * 2000-01-31 2001-08-07 Joseph L. Chovan Micro electro-mechanical component and system architecture
SG104293A1 (en) 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
CN2562369Y (zh) 2002-08-02 2003-07-23 威盛电子股份有限公司 弹力电性接触封装结构
JP2007311676A (ja) * 2006-05-22 2007-11-29 Sony Corp 半導体装置とその製造方法
US8183151B2 (en) * 2007-05-04 2012-05-22 Micron Technology, Inc. Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom
WO2009147936A1 (ja) * 2008-06-02 2009-12-10 イビデン株式会社 多層プリント配線板の製造方法
US7982298B1 (en) * 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8624370B2 (en) * 2009-03-20 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with an interposer and method of manufacture thereof
US8299366B2 (en) * 2009-05-29 2012-10-30 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
TWI418269B (zh) 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
TWI473218B (zh) * 2012-07-26 2015-02-11 Unimicron Technology Corp 穿孔中介板及其製法與封裝基板及其製法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347513A (ja) * 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20080230264A1 (en) * 2007-03-19 2008-09-25 Mutual-Tek Industries Co., Ltd. Interconnection structure and method thereof
TW200931612A (en) * 2008-01-10 2009-07-16 Phoenix Prec Technology Corp Package substrate

Also Published As

Publication number Publication date
US20150187692A1 (en) 2015-07-02
US9337136B2 (en) 2016-05-10
US9460992B2 (en) 2016-10-04
US9224683B2 (en) 2015-12-29
US20150179476A1 (en) 2015-06-25
US8981570B2 (en) 2015-03-17
US20140027925A1 (en) 2014-01-30
TW201405734A (zh) 2014-02-01
US20150179475A1 (en) 2015-06-25

Similar Documents

Publication Publication Date Title
TWI473218B (zh) 穿孔中介板及其製法與封裝基板及其製法
TWI476888B (zh) 嵌埋穿孔中介層之封裝基板及其製法
JP5396508B2 (ja) 介在層が埋め込まれたパッケージ基板及びその製造方法
TWI418269B (zh) 嵌埋穿孔中介層之封裝基板及其製法
TWI496270B (zh) 半導體封裝件及其製法
TWI587412B (zh) 封裝結構及其製法
TWI544599B (zh) 封裝結構之製法
KR20200037051A (ko) 집적 회로 패키지 및 방법
TWI483365B (zh) 封裝基板及其製法
CN103579145B (zh) 穿孔中介板及其制法与封装基板及其制法
TW201304641A (zh) 封裝基板及其製法
TWI455272B (zh) 半導體基板及其製法
TW201832297A (zh) 封裝堆疊構造及其製造方法
TWM455255U (zh) 具中介層之封裝基板及其封裝結構
CN108461454B (zh) 封装堆叠构造及其制造方法
TWI544593B (zh) 半導體裝置及其製法
TW201419428A (zh) 半導體封裝件之製法
TWI455271B (zh) 半導體元件結構及其製法
JP2004146728A (ja) 半導体装置とその製造方法
TW202435379A (zh) 電子封裝件及其封裝基板與製法
JP2022102370A (ja) 半導体装置及びその製造方法
TW201526184A (zh) 半導體裝置及其製法
TW201309125A (zh) 嵌埋晶片封裝件之封裝結構及其製法