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TWI418269B - 嵌埋穿孔中介層之封裝基板及其製法 - Google Patents

嵌埋穿孔中介層之封裝基板及其製法 Download PDF

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Publication number
TWI418269B
TWI418269B TW099143617A TW99143617A TWI418269B TW I418269 B TWI418269 B TW I418269B TW 099143617 A TW099143617 A TW 099143617A TW 99143617 A TW99143617 A TW 99143617A TW I418269 B TWI418269 B TW I418269B
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TW
Taiwan
Prior art keywords
layer
interposer
end surface
conductive
package substrate
Prior art date
Application number
TW099143617A
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English (en)
Other versions
TW201225762A (en
Inventor
Yu Shan Hu
Ti Chun Hu
Tzyy Jang Tseng
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW099143617A priority Critical patent/TWI418269B/zh
Priority to US13/074,467 priority patent/US8269337B2/en
Priority to CN201110104459.2A priority patent/CN102543927B/zh
Publication of TW201225762A publication Critical patent/TW201225762A/zh
Priority to US13/588,030 priority patent/US8709865B2/en
Application granted granted Critical
Publication of TWI418269B publication Critical patent/TWI418269B/zh

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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Description

嵌埋穿孔中介層之封裝基板及其製法
　　本發明係有關於一種封裝基板及其製法，尤指一種嵌埋穿孔中介層之封裝基板及其製法。
　　隨著電子產業的蓬勃發展，電子產品在型態上趨於輕薄短小，在功能上則逐漸邁入高性能、高功能、高速度化的研發方向。請參閱第1A圖，係為習知覆晶式封裝結構之剖視示意圖。
　　如第1A圖所示，該封裝結構之製程係先提供一具有核心板102、第一表面10a及第二表面10b之雙馬來醯亞胺-三氮雜苯(Bismaleimide-Triazine, BT)封裝基板10，且於該封裝基板10之第一表面10a具有覆晶焊墊100；再藉由焊錫凸塊11電性連接半導體晶片12之電性連接墊120；接著，於該封裝基板10之第一表面10a與該半導體晶片12之間形成底膠17，以包覆該焊錫凸塊11；又於該封裝基板10之第二表面10b具有植球墊101，以藉由焊球13電性連接例如為印刷電路板之另一電子裝置(未表示於圖中)。
　　然，因該半導體晶片12係屬尺寸為45nm以下之製程，故於後端製程(Back-End Of Line, BEOL)中，將採用超低介電係數(Extreme low-k dielectric, ELK) 或超低介電常數(Ultra low-k, ULK)之介電材料，但該low-k之介電材料為多孔特性易脆，以致於當進行覆晶封裝後，在信賴度熱循環測試，將因該封裝基板10與該半導體晶片12之間的熱膨脹係數(thermal expansion coefficient, CTE)差異過大，導致該焊錫凸塊11易因熱應力不均而產生破裂，使該半導體晶片12產生破裂，造成產品可靠度不佳。
　　再者，隨著電子產品更趨於輕薄短小及功能不斷提昇之需求，該半導體晶片12之佈線密度愈來愈高，以奈米尺寸作單位，因而各該電性連接墊120之間的間距更小；然，習知封裝基板10之覆晶焊墊100之間距係以微米尺寸作單位，而無法有效縮小至對應該電性連接墊120之間距的大小，導致雖有高線路密度之半導體晶片12，卻未有可配合之封裝基板，以致於無法有效生產電子產品。
　　請參閱第1B圖，為克服上述之問題，故於該封裝基板10與半導體晶片12’之間增設一矽中介層(Silicon interposer)14，該矽中介層14具有矽穿孔(Through-silicon via, TSV)140及設於該矽穿孔140頂端上之線路重佈層(Redistribution layer, RDL)141，令該矽穿孔140之底端藉由導電凸塊142電性結合間距較大之封裝基板10之覆晶焊墊100，而該線路重佈層141之最上層線路具有電極墊1410，以藉由焊錫凸塊11’電性結合間距較小之半導體晶片12’之電性連接墊120’，再形成封裝膠體18，使該封裝基板10可結合具有高佈線密度電性連接墊120’之半導體晶片12’，而達到整合高佈線密度之半導體晶片12’之目的。故藉由該矽中介層14，不僅可解決缺乏可配合之封裝基板的問題，且不會改變IC產業原本之供應鏈(supply chain)及基礎設備(infrastructure)。
　　再者，藉由該半導體晶片12’設於該矽中介層14上，且該矽中介層14之熱膨脹係數與半導體晶片12’之熱膨脹係數相同(CET均為2.6ppm)，故可避免該半導體晶片12’與該矽中介層14之間的焊錫凸塊11’破裂，有效使產品之可靠度提升。
　　然，藉由該矽中介層14雖解決該半導體晶片12與該封裝基板10之間的配合問題，但卻因增加該矽中介層14之厚度，導致整體結構之厚度增加，而無法滿足薄化之需求。
　　再者，於完成該矽中介層14之後，需再製作導電凸塊142以結合該封裝基板10，因製作導電凸塊142需將晶圓研磨到100微米以下的厚度，再進行導電凸塊142，而使用薄型晶圓之設備與材料均非常昂貴，導致成本大幅提高，而不利於量產。
　　因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明揭露一種嵌埋穿孔中介層之封裝基板，係包括：模封層，係具有相對之第一表面及第二表面；穿孔中介層，係嵌埋於該模封層中，且具有相對之第一側與第二側、及貫穿該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，且該第二側與該導電穿孔之第二端面與該模封層之第二表面齊平；線路重佈層，係嵌埋於該模封層中且設於該穿孔中介層之第一側與該導電穿孔之第一端面上，並電性連接該導電穿孔之第一端面，而該線路重佈層之最外層具有電極墊，該電極墊並外露於該模封層之第一表面；以及增層結構，係設於該模封層之第二表面上、該穿孔中介層之第二側與該導電穿孔之第二端面上，且具有複數導電盲孔，而部分之導電盲孔係對應電性連接該導電穿孔之第二端面。
　　前述之封裝基板中，該模封層之第一表面上具有第一開孔，以令該電極墊對應外露於該第一開孔，俾供作為覆晶連接晶片之連接點。
　　本發明復揭露一種嵌埋穿孔中介層之封裝基板之製法，係包括：提供一承載板；提供穿孔中介層及設於其上之線路重佈層，該穿孔中介層具有相對之第一側與第二側、及貫穿該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，該線路重佈層設於該穿孔中介層之第一側與該導電穿孔之第一端面上，且該線路重佈層電性連接該導電穿孔之第一端面，而該導電穿孔之第二端面與該第二側齊平，使該第二側與該導電穿孔之第二端面結合於該承載板上，又該線路重佈層之最外層具有電極墊；於該承載板與該線路重佈層上形成模封層，使該穿孔中介層嵌埋於該模封層中，且該模封層具有外露之第一表面及結合至該承載板上之第二表面；於該模封層之第一表面上形成金屬層；移除該承載板，以外露該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面；於該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面上形成增層結構，該增層結構具有複數導電盲孔，且部分之導電盲孔係對應電性連接該導電穿孔之第二端面；移除該金屬層，以外露該模封層之第一表面；以及於該模封層之第一表面上形成第一開孔，以令該電極墊對應外露於該第一開孔。
　　前述之封裝基板及其製法中，該增層結構復具有至少一介電層、及設於該介電層上之線路層，且各該導電盲孔設於該介電層中並電性連接該線路層與該導電穿孔之第二端面。復包括絕緣保護層，係設於該增層結構上，且該絕緣保護層具有複數第二開孔，以外露部份之線路層，俾供作為電性接觸墊。
　　依上述之結構及製法，復包括於該模封層之第一表面上形成天線結構或散熱片，且該散熱片具有開口，以外露出該線路重佈層之該些電極墊，並供收納電子元件。
　　依上述之結構及製法，復包括於該承載板上結合電子元件，且該電子元件嵌埋於該模封層中，並電性連接該增層結構或該晶片。又該電子元件係例如為主動元件、被動元件或整合型被動元件。
　　前述之封裝基板及其製法中，形成該穿孔中介層之材質係為單晶矽或多晶矽，該導電穿孔之側壁上則具有絕緣層，而該穿孔中介層與該線路重佈層之製程係包括：提供一基板，且於該基板上形成複數凹穴；於各該凹穴之側壁上與該基板上形成絕緣層，且該基板上之絕緣層定義為該第一側；於該凹穴中之絕緣層上形成金屬材，以形成該導電穿孔，且該導電穿孔之第一端面係外露於該第一側並與之齊平；於該第一側及該導電穿孔之第一端面上形成該線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有該電極墊；以及移除該凹穴下方之基板材料，以形成該穿孔中介層及該第二側，且該導電穿孔之第二端面係外露於該第二側。
　　前述之封裝基板及其製法中，形成該穿孔中介層之材質係為玻璃或陶瓷，而該穿孔中介層與該線路重佈層之製程係包括：提供一基板，且於該基板之其中一表面定義為該第一側，並於該第一側上形成複數凹穴；於該凹穴中形成金屬材，以形成該導電穿孔，且該導電穿孔之第一端面係外露於該第一側並與之齊平；於該第一側及該導電穿孔之第一端面上形成該線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有該電極墊；以及移除該凹穴下方之基板材料，以形成該穿孔中介層及該第二側，且該導電穿孔之第二端面係外露於該第二側。
　　前述之封裝基板及其製法中，該穿孔中介層之厚度較佳為75至150微米。
　　由上可知，本發明嵌埋穿孔中介層之封裝基板及其製法，主要藉由將該穿孔中介層嵌埋於該模封層中，以避免外側堆疊該穿孔中介層，因而可降低整體結構之厚度，且藉由於該模封層之第二表面上形成增層結構，故無需使用習知技術之核心板，亦可降低整體結構之厚度。
　　再者，因該穿孔中介層嵌埋於該模封層中，使該穿孔中介層可藉由該導電穿孔電性連接該增層結構之導電盲孔，因而無需製作如習知技術之導電凸塊，故可大幅降低製作成本，而有利於量產。
　　以下藉由特定的具體實施例說明本發明之實施方式， 熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　請參閱第2A至2F圖，係為本發明所揭露之嵌埋穿孔中介層之封裝基板的製法之剖視示意圖。
　　如第2A圖所示，首先，提供一承載板20、穿孔中介層(interposer)21及線路重佈層213。
　　所述之穿孔中介層21具有相對之第一側21a與第二側21b、及貫穿該第一側21a與第二側21b之複數導電穿孔210，該導電穿孔210於該第一側21a與第二側21b上分別具有第一端面210a與第二端面210b，且該導電穿孔210之第二端面210b係與該第二側21b齊平，使該第二側21b與該導電穿孔210之第二端面210b結合於該承載板20上。又該穿孔中介層21之厚度較佳為75至150微米(μm)。
　　所述之線路重佈層213係設於該穿孔中介層21之第一側21a與該導電穿孔210之第一端面210a上，且該線路重佈層213之最內層線路電性連接該導電穿孔210之第一端面210a，又該線路重佈層213之最外層線路具有電極墊211。
　　如第2B圖所示，於該承載板20與該線路重佈層213上形成模封層22，使該穿孔中介層21嵌埋於該模封層22中，且該模封層22具有外露之第一表面22a及結合至該承載板20上之第二表面22b。
　　如第2C圖所示，於該模封層22之第一表面22a上形成金屬層23。
　　如第2D圖所示，移除該承載板20，以外露該模封層22之第二表面22b、該穿孔中介層21之第二側21b與該導電穿孔210之第二端面210b。
　　如第2E圖所示，利用擴散型(fan-out)技術，於該模封層22之第二表面22b、該穿孔中介層21之第二側21b與該導電穿孔210之第二端面210b上形成增層結構24，該增層結構24具有複數導電盲孔242，且部分之導電盲孔242係對應電性連接該導電穿孔210之第二端面210b。
　　所述之增層結構24復具有至少一介電層240、及設於該介電層240上之線路層241，且各該導電盲孔242設於該介電層240中並電性連接該線路層241與該導電穿孔210之第二端面210b。又，於該增層結構24之最外側之介電層240與線路層241上形成絕緣保護層25，例如：防焊層，且該絕緣保護層25具有複數第二開孔250，以外露部份最外層之線路層241，俾供作為電性接觸墊243。
　　如第2F圖所示，移除該金屬層23，以外露該模封層22之第一表面22a，再於該模封層22之第一表面22a上形成第一開孔220，以令該電極墊211對應外露於該第一開孔220。
　　本發明之封裝基板，係藉由將該穿孔中介層21嵌埋於該模封層22中，相較於習知技術之外側堆疊矽中介層之結構，本發明有效降低整體結構之厚度，且因於該模封層22之第二表面22b上形成增層結構24，故無需使用習知技術之核心板，亦降低整體結構之厚度。
　　再者，因該穿孔中介層21嵌埋於該模封層22中，使該穿孔中介層21係藉由該導電穿孔210電性連接該增層結構24之導電盲孔242，故該穿孔中介層21無需於該導電穿孔210之第二端面210b上製作如習知技術之導電凸塊，因而有效降低製作成本，以利於量產。
　　請參閱第2G圖，係為本發明封裝基板之應用態樣；如第2G圖所示，將晶片27藉由焊錫凸塊271以覆晶方式電性連接於該線路重佈層213之電極墊211上，再於該電極墊211與該晶片27之間填入底膠270，且將該電性接觸墊243作為植球墊而於其上結合焊球26，以接置於例如為印刷電路板之另一電子裝置(圖未示)。其中，所述之晶片27亦可為堆疊式(multiple chips)或被動元件(passives component)，該被動元件可為電容、電感、電阻。
　　將晶片27結合於封裝基板之穿孔中介層21，相較於習知技術之覆晶式封裝基板，可提升產品之可靠度。
　　請參閱第3A至3D圖及第4A至4D圖，係顯示該穿孔中介層21之不同結構及其製程。
　　如第3A至3D圖所示，該穿孔中介層21之材質係為單晶矽(single crystal )或多晶矽(poly silicon )。
　　如第3A圖所示，提供一基板21’，且於該基板21’上形成複數凹穴210’。
　　如第3B圖所示，於各該凹穴210’之側壁上與該基板21’上形成絕緣層212，且該基板21’上之絕緣層212表面定義為該第一側21a；接著，於該凹穴210’中之絕緣層212上形成金屬材，以形成該導電穿孔210，且該導電穿孔210之第一端面210a係外露於該第一側21a並與之齊平。
　　如第3C圖所示，於該第一側21a及該導電穿孔210之第一端面210a上形成該線路重佈層213，該線路重佈層213之最內層線路電性連接該導電穿孔210之第一端面210a，且該線路重佈層213之最外層線路具有該電極墊211。
　　如第3D圖所示，進行薄化製程，移除該凹穴210’下方之基板21’材料(如第3C圖所示之假想線L下方)，以形成該穿孔中介層21及該第二側21b，且該導電穿孔210之第二端面210b係外露於該第二側21b。
　　於本製程中，係藉由該絕緣層212以避免該導電穿孔210與該穿孔中介層21之矽材導通，可避免造成短路。
　　如第4A至4D圖所示，該穿孔中介層21之材質可為玻璃(glass)、或例如為Al2 O3 或 AlN之陶瓷，其中，因陶瓷之熱膨脹係數(大約為3 ppm/℃)接近矽，故可採用之。
　　如第4A圖所示，提供一基板21’，且於該基板21’之其中一表面定義為該第一側21a，並於該第一側21a上形成複數凹穴210’。
　　如第4B圖所示，於該凹穴210’中形成金屬材，以形成該導電穿孔210，且該導電穿孔210之第一端面210a係外露於該第一側21a並與之齊平。
　　如第4C圖所示，於該第一側21a及該導電穿孔210之第一端面210a上形成該線路重佈層213，該線路重佈層213之最內層線路電性連接該導電穿孔210之第一端面210a，且該線路重佈層213之最外層線路具有該電極墊211。
　　如第4D圖所示，移除該凹穴210’下方之基板21’材料(如第4C圖所示之假想線L下方)，以形成該穿孔中介層21及該第二側21b，且該導電穿孔210之第二端面210b係外露於該第二側21b。
　　於本製程中，因該穿孔中介層21之玻璃材或陶瓷材矽為絕緣體，故無需於各該凹穴210’之側壁上形成絕緣層212。
　　於上述兩製程中，因該穿孔中介層21用於嵌埋於該模封層22中，故不需再於該導電穿孔210之第二端面210b上製作導電凸塊，因而降低製作成本。
　　再者，該穿孔中介層21之熱膨脹係數與矽晶圓接近或者相同，可提高封裝後熱循環測試的信賴度。
　　請一併參閱第5A、6A、7A圖與第5B、6B、7B圖，係為本發明嵌埋穿孔中介層21之封裝基板之其他實施例及其應用。
　　如第5A圖所示，於第2F圖所示之封裝基板中，於該模封層22之第一表面22a上形成天線結構29，且該天線結構29係埋設於介電材中。再者，形成該模封層22之前(第2B圖之製程之前)，可於該承載板20上結合具有電性連接墊300之第一電子元件30，使該第一電子元件30嵌埋於該模封層22中，且當形成該增層結構24時，該第一電子元件30可藉由該電性連接墊300電性連接該增層結構24之導電盲孔242。其中，該第一電子元件30係為主動元件(半導體晶片等)、被動元件(電容、電感、電阻)或整合型被動元件(Integrated Passive Device, IPD)。
　　如第5B圖所示，係為第5A圖所示之封裝基板之應用，將晶片27藉由焊錫凸塊271以覆晶方式電性連接於該線路重佈層213之電極墊211上，再於該電極墊211與該晶片27之間填入底膠270，且於該電性接觸墊243上結合焊球26，以接置於例如為印刷電路板之另一電子裝置(圖未示)。
　　如第6A圖所示，於第2F圖所示之封裝基板中，於形成該模封層22之前，亦可於該承載板20上結合具有電性連接墊300’之第二電子元件30’，使該第二電子元件30’嵌埋於該模封層22中，且可令該第二電子元件30’之電性連接墊300’對應外露於該模封層22之第三開孔221。其中，該第二電子元件30’係為主動元件(半導體晶片等)、被動元件(電容、電感、電阻)或整合型被動元件(IPD)。
　　如第6B圖所示，係為第6A圖所示之封裝基板之應用，將另一晶片27’藉由焊錫凸塊271以覆晶方式電性連接於該電極墊211與該第二電子元件30’之電性連接墊300’上，再於該封裝基板與該晶片27’之間填入底膠270，且於該電性接觸墊243上結合焊球26，以接置於例如為印刷電路板之另一電子裝置(圖未示)。
　　如第7A圖所示，於第2F圖所示之封裝基板中，該第一電子元件30嵌埋於該模封層22中，且於該模封層22之第一表面22a上形成散熱片31，該散熱片31具有開口310，以外露出該線路重佈層213之電極墊211，並供收納電子元件。
　　如第7B圖所示，係為第7A圖所示之封裝基板之應用，於該電極墊211上藉由焊錫凸塊271以覆晶方式電性連接兩晶片28，以令各該晶片28位於該開口310中，再於該開口310中、該散熱片31及該些晶片28上形成封裝膠體，如：散熱膠32，以包覆該些晶片28。
　　於上述各實施例及其應用之說明中，有關封裝基板中之各元件，如：天線結構29、第一電子元件30、第二電子元件30’或散熱片31，係可依需求作增設，並不僅限於上述型態，且於應用時，有關晶片27,27’,28之數量並無特別限制。
　　本發明復提供一種嵌埋穿孔中介層21之封裝基板，係包括：具有相對之第一表面22a及第二表面22b之模封層22、嵌埋於該模封層22中之穿孔中介層21、嵌埋於該模封層22中且設於該穿孔中介層21上之線路重佈層213、 以及設於該模封層22之第二表面22b上之增層結構24。
　　所述之模封層22之第一表面22a上具有第一開孔220。
　　所述之穿孔中介層21具有相對之第一側21a與第二側21b、及貫穿該第一側21a與第二側21b之複數導電穿孔210，該導電穿孔210於該第一側21a與第二側21b上分別具有第一端面210a與第二端面210b，且該第二側21b與該導電穿孔210之第二端面210b係與該模封層22之第二表面22b齊平。再者，形成該穿孔中介層21之材質係為玻璃、陶瓷、單晶矽或多晶矽，若為單晶矽或多晶矽，則該導電穿孔210之側壁上具有絕緣層212。
　　所述之線路重佈層213係設於該穿孔中介層21之第一側21a與該導電穿孔210之第一端面210a上，且該線路重佈層213之最內層線路電性連接該導電穿孔210之第一端面210a，而該線路重佈層213之最外層線路具有電極墊211，該電極墊211並對應外露於該模封層22之第一開孔220，俾供作為覆晶連接至少一晶片27,27’,28之連接點。
　　所述之增層結構24復設於該穿孔中介層21之第二側21b與該導電穿孔210之第二端面210b上，該增層結構24具有至少一介電層240、及設於該介電層240上之線路層241、以及設於該介電層240中並電性連接該線路層241與該導電穿孔210之第二端面210b之複數導電盲孔242。
　　所述之封裝基板復包括絕緣保護層25，係設於該增層結構24上，且該絕緣保護層25具有複數第二開孔250，以外露部份之線路層241，俾供作為電性接觸墊243，而結合焊球26。
　　所述之封裝基板復包括天線結構29，係設於該模封層22之第一表面22a上。
　　所述之封裝基板復包括第一電子元件30，係嵌埋於該模封層22中且電性連接該增層結構24。
　　所述之封裝基板復包括具有電性連接墊300’之第二電子元件30’，係嵌埋於該模封層22中，且令該第二電子元件30’之電性連接墊300’對應外露於該模封層22。
　　所述之封裝基板復包括散熱片31，係設於該模封層22之第一表面22a上，且該散熱片31具有開口310，以外露出該線路重佈層213之該些電極墊211，並供收納電子元件。
　　綜上所述，本發明嵌埋穿孔中介層之封裝基板及其製法，係藉由將穿孔中介層嵌埋於模封層中之技術，以避免堆疊該穿孔中介層及使用核心板，故有效降低整體結構之厚度。
　　再者，因該穿孔中介層嵌埋於該模封層中，使該穿孔中介層係藉由該導電穿孔電性連接該增層結構之導電盲孔，故該穿孔中介層無需於該導電穿孔之端面上製作導電凸塊，俾有效降低製作成本。
　　又，藉由該穿孔中介層結合晶片，可提升產品之可靠度。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10‧‧‧封裝基板
10a,22a‧‧‧第一表面
10b,22b‧‧‧第二表面
100‧‧‧覆晶焊墊
101‧‧‧植球墊
102‧‧‧核心板
11,11’,271‧‧‧焊錫凸塊
12,12’‧‧‧半導體晶片
120,120’,300,300’‧‧‧電性連接墊
13,26‧‧‧焊球
14‧‧‧矽中介層
140‧‧‧矽穿孔
141,213‧‧‧線路重佈層
1410,211‧‧‧電極墊
142‧‧‧導電凸塊
17,270‧‧‧底膠
18‧‧‧封裝膠體
20‧‧‧承載板
21‧‧‧穿孔中介層
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧導電穿孔
210a‧‧‧第一端面
210b‧‧‧第二端面
212‧‧‧絕緣層
21’‧‧‧基板
210’‧‧‧凹穴
22‧‧‧模封層
220‧‧‧第一開孔
221‧‧‧第三開孔
23‧‧‧金屬層
24‧‧‧增層結構
240‧‧‧介電層
241‧‧‧線路層
242‧‧‧導電盲孔
243‧‧‧電性接觸墊
25‧‧‧絕緣保護層
250‧‧‧第二開孔
27,27’,28‧‧‧晶片
29‧‧‧天線結構
30‧‧‧第一電子元件
30’‧‧‧第二電子元件
31‧‧‧散熱片
310‧‧‧開口
32‧‧‧散熱膠
L‧‧‧假想線
　　第1A圖係為習知覆晶封裝結構之剖視示意圖；
　　第1B圖係為習知具有矽中介層之封裝基板之剖視示意圖；
　　第2A至2F圖係為本發明嵌埋穿孔中介層之封裝基板的製法之剖視示意圖；第2G圖係為本發明嵌埋穿孔中介層之封裝基板之應用態樣；
　　第3A至3D圖係為本發明所述之嵌埋穿孔中介層之製程之剖視示意圖；
　　第4A至4D圖係為本發明所述之嵌埋穿孔中介層之另一製程態樣之剖視示意圖；
　　第5A、6A、7A圖係為本發明所述之嵌埋穿孔中介層之封裝基板之其他實施例；以及
　　第5B、6B、7B圖係為本發明所述之嵌埋穿孔中介層之封裝基板之不同應用態樣。
21‧‧‧穿孔中介層
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧導電穿孔
210a‧‧‧第一端面
210b‧‧‧第二端面
211‧‧‧電極墊
212‧‧‧絕緣層
213‧‧‧線路重佈層
22‧‧‧模封層
22a‧‧‧第一表面
22b‧‧‧第二表面
220‧‧‧第一開孔
24‧‧‧增層結構
240‧‧‧介電層
241‧‧‧線路層
242‧‧‧導電盲孔
25‧‧‧絕緣保護層
250‧‧‧第二開孔

Claims (23)

  1. 一種嵌埋穿孔中介層之封裝基板，係包括：
    　　模封層，係具有相對之第一表面及第二表面；
    　　穿孔中介層，係嵌埋於該模封層中，且具有相對之第一側與第二側、及貫穿該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，且該第二側與該導電穿孔之第二端面係與該模封層之第二表面齊平；
    　　線路重佈層，係嵌埋於該模封層中且設於該穿孔中介層之第一側與該導電穿孔之第一端面上，並電性連接該導電穿孔之第一端面，而該線路重佈層之最外層具有電極墊，該電極墊並外露於該模封層之第一表面；以及
    　　增層結構，係設於該模封層之第二表面上、該穿孔中介層之第二側與該導電穿孔之第二端面上，且具有複數導電盲孔，而部分之導電盲孔係對應電性連接該導電穿孔之第二端面。
  2. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該模封層之第一表面上具有第一開孔，以令該電極墊對應外露於該第一開孔，俾供作為覆晶連接晶片之連接點。
  3. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，形成該穿孔中介層之材質係為玻璃、陶瓷、單晶矽或多晶矽。
  4. 如申請專利範圍第3項所述之嵌埋穿孔中介層之封裝基板，其中，形成該穿孔中介層之材質為單晶矽或多晶矽，該導電穿孔之側壁上具有絕緣層。
  5. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該穿孔中介層之厚度為75至150微米。
  6. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該增層結構復具有至少一介電層、及設於該介電層上之線路層，且各該導電盲孔設於該介電層中並電性連接該線路層與該導電穿孔之第二端面。
  7. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，復包括絕緣保護層，係設於該增層結構上，且該絕緣保護層具有複數第二開孔，以外露部份之線路層，俾供作為電性接觸墊。
  8. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，復包括天線結構，係設於該模封層之第一表面上。
  9. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，復包括第一電子元件，係嵌埋於該模封層中且電性連接該增層結構。
  10. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，復包括具有電性連接墊之第二電子元件，係嵌埋於該模封層中，且令該第二電子元件之電性連接墊對應外露於該模封層。
  11. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，復包括散熱片，係設於該模封層之第一表面上，且該散熱片具有開口，以外露出該線路重佈層之該些電極墊，並供收納電子元件。
  12. 一種嵌埋穿孔中介層之封裝基板之製法，係包括：
    　　提供一承載板；
    　　提供穿孔中介層及設於其上之線路重佈層，該穿孔中介層具有相對之第一側與第二側、及貫穿該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，該線路重佈層設於該穿孔中介層之第一側與該導電穿孔之第一端面上，且該線路重佈層電性連接該導電穿孔之第一端面，而該導電穿孔之第二端面係與該第二側齊平，使該第二側與該導電穿孔之第二端面結合於該承載板上，又該線路重佈層之最外層具有電極墊；
    　　於該承載板與該線路重佈層上形成模封層，使該穿孔中介層嵌埋於該模封層中，且該模封層具有外露之第一表面及結合至該承載板上之第二表面；
    　　於該模封層之第一表面上形成金屬層；
    　　移除該承載板，以外露該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面；
    　　於該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面上形成增層結構，該增層結構具有複數導電盲孔，且部分之導電盲孔係對應電性連接該導電穿孔之第二端面；
    　　移除該金屬層，以外露該模封層之第一表面；以及
    　　於該模封層之第一表面上形成第一開孔，以令該電極墊對應外露於該第一開孔。
  13. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，形成該穿孔中介層之材質係為單晶矽或多晶矽，而該穿孔中介層與該線路重佈層之製程係包括：
    　　提供一基板，且於該基板上形成複數凹穴；
    　　於各該凹穴之側壁上與該基板上形成絕緣層，且該基板上之絕緣層定義為該第一側；
    　　於該凹穴中之絕緣層上形成金屬材，以形成該導電穿孔，且該導電穿孔之第一端面係外露於該第一側並與之齊平；
    　　於該第一側及該導電穿孔之第一端面上形成該線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有該電極墊；以及
    　　移除該凹穴下方之基板材料，以形成該穿孔中介層及該第二側，且該導電穿孔之第二端面係外露於該第二側。
  14. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，形成該穿孔中介層之材質係為玻璃或陶瓷，而該穿孔中介層與該線路重佈層之製程係包括：
    　　提供一基板，且於該基板之其中一表面定義為該第一側，並於該第一側上形成複數凹穴；
    　　於該凹穴中形成金屬材，以形成該導電穿孔，且該導電穿孔之第一端面係外露於該第一側並與之齊平；
    　　於該第一側及該導電穿孔之第一端面上形成該線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有該電極墊；以及
    　　移除該凹穴下方之基板材料，以形成該穿孔中介層及該第二側，且該導電穿孔之第二端面係外露於該第二側。
  15. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該穿孔中介層之厚度為75至150微米。
  16. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該增層結構復具有至少一介電層、及設於該介電層上之線路層，且各該導電盲孔設於該介電層中並電性連接該線路層與該導電穿孔之第二端面。
  17. 如申請專利範圍第16項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該增層結構上形成絕緣保護層，且該絕緣保護層具有複數第二開孔，以外露部份之線路層，俾供作為電性接觸墊。
  18. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該模封層之第一表面上形成天線結構。
  19. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該承載板上結合第一電子元件，且該第一電子元件嵌埋於該模封層中並電性連接該增層結構。
  20. 如申請專利範圍第19項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該第一電子元件係為主動元件、被動元件或整合型被動元件。
  21. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該承載板上結合具有電性連接墊之第二電子元件，該第二電子元件嵌埋於該模封層中，且令該第二電子元件之電性連接墊對應外露於該模封層。
  22. 如申請專利範圍第21項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該第二電子元件係為主動元件、被動元件或整合型被動元件。
  23. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該模封層之第一表面上形成散熱片，且該散熱片具有開口，以外露出該線路重佈層之該些電極墊，並供收納電子元件。
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