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TWI471946B - 薄膜電晶體 - Google Patents

薄膜電晶體 Download PDF

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Publication number
TWI471946B
TWI471946B TW99139500A TW99139500A TWI471946B TW I471946 B TWI471946 B TW I471946B TW 99139500 A TW99139500 A TW 99139500A TW 99139500 A TW99139500 A TW 99139500A TW I471946 B TWI471946 B TW I471946B
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TW
Taiwan
Prior art keywords
layer
thin film
oxide
film transistor
drain
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Application number
TW99139500A
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English (en)
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TW201222676A (en
Inventor
Hsin Hung Lin
Jung Fang Chang
Ker Yih Kao
Original Assignee
Innolux Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Innolux Corp filed Critical Innolux Corp
Priority to TW99139500A priority Critical patent/TWI471946B/zh
Priority to CN2011100372458A priority patent/CN102468340A/zh
Priority to CN201410742453.1A priority patent/CN104409360A/zh
Priority to US13/288,579 priority patent/US8890145B2/en
Publication of TW201222676A publication Critical patent/TW201222676A/zh
Priority to US14/478,124 priority patent/US9076872B2/en
Priority to US14/478,148 priority patent/US9368631B2/en
Priority to US14/478,172 priority patent/US9362408B2/en
Application granted granted Critical
Publication of TWI471946B publication Critical patent/TWI471946B/zh
Priority to US15/155,325 priority patent/US9601519B2/en

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  • Thin Film Transistor (AREA)

Description

薄膜電晶體
本發明係關於薄膜電晶體，更特別關於氧化物半導體作為通道層之結構及方法。
在薄膜電晶體(TFT)之製程中，氧化物半導體(oxide semiconductor)的開發愈來愈受到重視，在日商與韓商已是列為重點開發項目之一。氧化物半導體可為氧化鋅(ZnO)、氧化鎵鋅(GZO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化銦鋅(IZO)、及氧化銦鎵鋅(IGZO)等等。氧化物半導體用於元件製作上，已有背通道蝕刻(BCE)五道光罩製程、倒閘極共平面型五道光罩製程、與採用蝕刻停止層的六道光罩製程。上述製程中，六道光罩製程之蝕刻停止層可保護通道層，所得到的元件特性表現皆較五道光罩者為佳，但需多一道光罩。以五道光罩製程而言，倒閘極共平面型五道光罩製程可獨立定義各層，較不受蝕刻選擇特性限制，對面板製造商而言所需進行之變更最少，較具量產優勢。但以未來大面積面板所需之銅金屬製程搭配氧化物半導體技術組合，在保護層覆蓋銅金屬層前，需以還原氣氛之電漿(如氫氣電漿)將金屬表面之氧化物還原為銅。然而氧化物半導體對於還原氣氛電漿極為敏感，將造成元件失效。
綜上所述，目前亟需一種新穎製程，在不增加光罩數目的情況下，有效保護通道層不受後續製程如還原電漿損害。
本發明一實施例提供一種薄膜電晶體的形成方法，包括形成閘極於基板上；形成閘極介電層於閘極與基板上；形成源極/汲極於閘極兩側的閘極介電層上；形成氧化物半導體層於源極/汲極與閘極介電層上；形成絕緣蓋層於氧化物半導體層上；以及圖案化絕緣層與氧化物半導體層，形成絕緣蓋層覆蓋通道層。
本發明另一實施例提供一種薄膜電晶體，包括閘極位於基板上；閘極介電層位於閘極與基板上；源極/汲極位於閘極兩側的閘極介電層上；通道層位於閘極中間部份的閘極介電層上，且通道層接觸源極/汲極；以及絕緣蓋層覆蓋通道層，其中通道層包括氧化物半導體。
下列說明中的實施例將揭露如何形成並使用薄膜電晶體。必需理解的是，這些實施例提供多種可行的發明概念，並可應用於多種特定內容中。特定實施例僅用以說明形成及使用實施例的特定方式，並非用以侷限本發明的範圍。
如第1A圖所示，形成圖案化金屬層12於基板10上。基板10可為透光(如玻璃、石英、或類似物)或不透光(如晶圓、陶瓷、或類似物)之剛性無機材質，亦可為塑膠、橡膠、聚酯、或聚碳酸酯等可撓性有機材質。在某些實施例中的基板10採用透光材質，最後形成的薄膜電晶體可應用於穿透式、半穿反、或反射式液晶顯示器。在其他實施例中的基板10採用不透光或透光性不佳的材質，最後形成的薄膜電晶體只能應用於反射式液晶顯示器，或自發光顯示器上。
上述圖案化金屬層12之材質可為金屬、合金、或上述之多層結構。在某些實施例中，圖案化金屬層12為鉬、鋁、銅、鈦等單層或多層組合的金屬或合金。圖案化金屬層12之形成方法可為形成金屬層於基板10上，再以微影圖案化製程搭配蝕刻法形成圖案化金屬層12。金屬層之形成方法可為物理氣相沉積法(PVD)、濺鍍法、或類似方法。微影圖案化製程可為下述步驟：塗佈光阻如旋塗法、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影、沖洗、乾燥如硬烘烤、其他合適製程、或上述之組合。此外，微影之曝光製程可改用其他方法如無光罩微影、電子束直寫、或離子束直寫。蝕刻製程可為乾蝕刻、濕蝕刻、或上述之組合。雖然在後述之第1C圖中，圖案化金屬層12只作為薄膜電晶體之閘極以及與之相連的閘極線，但圖案化金屬層12亦可作為接觸墊、儲存電容之下電極、或其他元件，端視需要而定。
如第1B圖所示，接著形成介電層14於圖案化金屬層12上。介電層14之組成可為有機材質如有機矽氧化合物，或無機材質如氮化矽、氧化矽、氮氧化矽、碳化矽、氧化鋁、氧化鉿、或上述材質之多層結構。介電層14之形成方法可為化學氣相沉積法(CVD)如電漿增強式CVD(PECVD)、低壓CVD(LPCVD)、次常壓CVD(SACVD)、物理氣相沉積(PVD)、或類似技術。雖然在後述之第1C圖中，介電層14僅作為薄膜電晶體閘極介電層，但介電層14亦可作為儲存電容之電容介電層或其他元件，端視需要而定。可以理解的是，第1C圖中剖面線A-A’之剖視圖即第1B圖所示之結構。
如第2A圖所示，形成另一金屬層16於介電層14上。金屬層16之材質可為金屬、合金、或上述之多層結構。在某些實施例中，金屬層16為銅或銅合金。在其他實施例中，金屬層16不含銅，比如鉬/鋁/鉬之多層結構、或鉬/鋁/鈦多層或單層金屬或合金。金屬層16之形成方法可為電鍍法、無電電鍍法、PVD、濺鍍法、或類似方法。
如第2B圖所示，形成圖案化光阻層18於金屬層16上，其形成方法可為微影圖案化製程如上述，在此不贅述。以圖案化光阻層18作遮罩蝕刻金屬層16，即形成源極16A與汲極16B。蝕刻方法可為乾蝕刻、濕蝕刻、或上述之組合。之後可移除圖案化光阻層18，移除方法可為濕式去光阻剝膜液去除或光阻灰化。雖然在後述之第2C圖中，金屬層16在圖案化後作為薄膜電晶體之源極/汲極16A/16B與源極線，但亦可作為其他線路或其他元件，端視需要而定。可以理解的是，第2C圖中剖面線A-A’之剖視圖即第2B圖移除圖案化光阻層18後所示之結構。
如第3A圖所示，形成氧化物半導體層32於第2B圖移除圖案化光阻層18後之結構上，再形成絕緣層34於氧化物半導體層32上。在一實施例中，氧化物半導體層32之組成可為氧化鋅、氧化銦、銦鎵鋅氧化物、或氧化錫。在其他實施例中，氧化物半導體層32可為氧化鋅、氧化銦、銦鎵鋅氧化物、氧化錫、氧化鎵、氧化鋁、及氧化鈦中至少兩者之組合。氧化物半導體層32之形成方法可為CVD如PECVD、LPCVD、SACVD、物理與氣相沉積(PVD)、溶液合成方式沉積、或類似方法。在本發明一實施例中，絕緣層34之組成可為有機材料如壓克力系材料，其形成方法可為旋轉塗佈法、狹縫塗佈法、浸泡法、或其他類似方法。在本發明另一實施例中，絕緣層34之組成可為無機材料如氧化矽、氮化矽、氮氧化矽、氧化鋁、氧化鈦、氧化鉿、或氮化鋁，其形成方法可為濺鍍法、CVD如PECVD、LPCVD、或SACVD、或類似沉積方法。在其他實施例中，絕緣層34之組成為鈍化金屬層如氧化鋁、氧化鈦、氮化鈦、或其他氧化或氮化的金屬層，其形成方法係先形成金屬層於氧化物半導體體層32上，再以氧氣或氮氣鈍化金屬層。不過值得注意的是，鈍化金屬層需考慮到物質本性。舉例來說，氧化鋁與氮化鋁均為絕緣材料，因此鋁的鈍化方式可為氧化或氮化。另一方面，氧化鈦為絕緣材料但氮化鈦仍為導電材料，因此鈦的鈍化方式只能採用氧化而不能採用氮化。上述步驟需於等壓如真空中進行。在本發明一實施例中，形成氧化物半導體層32與絕緣層34之步驟均位於同一反應腔中進行。在本發明其他實施例中，形成氧化物半導體層32與絕緣層34之步驟係於等壓系統中的不同反應腔中進行。
如第3B圖所示，形成圖案化光阻層36於絕緣層34上，其形成方法可為微影圖案化製程如上述，在此不贅述。接著以一段蝕刻製程移除未被圖案化光阻層36覆蓋之絕 緣層34與氧化物半導體層32，形成絕緣蓋層37覆蓋通道層38。上述之一段蝕刻製程可為乾蝕刻如烷類、氫氣、氬氣、與鹵酸等混合氣體，或濕蝕刻如氫氟酸。最後移除圖案化光阻層36，即形成第3C圖所示之結構。
第4A圖至4D圖與第3A圖至3C圖之製程類似，唯一差異在於第4A至4D圖形成絕緣蓋層37與通道層38之蝕刻製程為分段蝕刻製程而非一段蝕刻製程。舉例來說，可先進行第一道蝕刻製程，移除未被圖案化光阻層36遮罩之絕緣層34以形成絕緣蓋層37，如第4C圖所示。接著再進行第二道蝕刻製程，移除未被圖案化光阻層36遮罩之氧化物半導體層32以形成通道層38，再移除圖案化光阻層36如第4D圖所示。第一道蝕刻製程與第二道蝕刻製程可針對氧化物半導體層32與絕緣層34之蝕刻選擇性，分別採用不同的乾蝕刻或濕蝕刻條件。舉例來說，可採用一般蝕刻氧化物的氣體乾蝕刻絕緣層34，再採用草酸或鋁酸濕蝕刻氧化物半導體層32。不論採用一段或分段蝕刻製程，最後都應形成絕緣蓋層37覆蓋通道層38之結構。可以理解的是，第3D圖之剖面線A-A’之剖視圖即第3C或第4D圖所示之結構。
在第3C圖及第4D圖之結構中，絕緣蓋層37之下表面與通道層38之上表面兩者之寬度實質上相等。但在其他實施例中，絕緣蓋層37之下表面寬度可略大於或略小於通道層38之上表面寬度，且兩者之寬度差距約介於0μm至2μm之間。不論如何，絕緣蓋層37之下表面較佳與通道層38之上表面的寬度一致。若寬度差距若超過2μm，將不利後續製程。
接著可形成保護層52於第3C圖(或第4D圖)之結構上。保護層52之組成可為氮化矽、氧化矽、氮氧化矽、碳化矽、氧化鋁、氧化鈦、氧化鉿、或上述材質之多層結構，其形成方式可為CVD、PECVD、或PVD。在本發明一實施例中，在形成保護層52之前，會先以還原性電漿(如氫氣電漿)處理第3C圖(或第4圖)之結構表面，以增加保護層52之接著性。特別是在源極/汲極16A/16B之組成含銅時，通道層38之形成步驟如微影及蝕刻會氧化源極/汲極16A/16B的表面，因此更需以還原製程如氫氣使源極/汲極16A/16B表面之氧化銅還原為銅。若通道層38上方未覆蓋絕緣蓋層37，上述的還原性電漿及/或還原製程均會還原通道層38之氧化物半導體，使其形成導體並破壞元件功能。
接著以微影圖案化製程形成圖案化光阻(未圖示)，再以圖案化光阻為遮罩進行蝕刻製程，即形成接觸孔54如第5A圖所示。可以理解的是，第5B圖之剖面線A-A’之剖視圖即第5A圖所示之結構。
如第6A圖所示，形成導電圖案62於第5A圖所示之結構上。導電圖案62係形成於保護層52上作為畫素電極，並經由接觸孔54電性連接至汲極16B。導電圖案62之形成方法為先形成導電層後，再以微影圖案化製程與蝕刻製程圖案化導電層，至此完成薄膜電晶體。若薄膜電晶體係應用於穿透式LCD中，導電圖案62之組成可為銦錫氧化物(ITO)、銦鋅氧化物(IZO)、鋁鋅氧化物(AZO)、鎘錫氧化物(CTO)、氧化錫(SnO2 )、或氧化鋅(ZnO)等透明導電材料。若薄膜電晶體係應用於反射式LCD中，導電圖案62之組成可為鋁、金、錫、銀、銅、鐵、鉛、鉻、鎢、鉬、釹、上述之氮化物、上述之氧化物、上述之氮氧化物、上述之合金、或上述之組合。此外，反射式的導電圖案62之表面呈現凹凸狀，以增加光線之反射及散射之效果。若薄膜電晶體係應用於半穿反LCD中，則分別採用透明組成或反射組成於穿透區或反射區中。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
A-A’．．．剖面線
10．．．基板
12．．．圖案化金屬層
14．．．閘極介電層
16．．．金屬層
16A．．．源極
16B‧‧‧汲極
18、36‧‧‧圖案化光阻層
32‧‧‧氧化物半導體層
34‧‧‧絕緣層
37‧‧‧絕緣蓋層
38‧‧‧通道層
52‧‧‧保護層
54‧‧‧接觸孔
62‧‧‧導電圖案
第1A-1B、2A-2B、3A-3C、4A-4D、5A及6A圖係本發明某些實施例中，薄膜電晶體之製程剖視圖；以及
第1C、2C、3D、5B及6B圖係本發明某些實施例中，薄膜電晶體之製程上視圖。
10‧‧‧基板
12‧‧‧圖案化金屬層
14‧‧‧閘極介電層
16A‧‧‧源極
16B‧‧‧汲極
37‧‧‧絕緣蓋層
38‧‧‧通道層
52‧‧‧保護層
62‧‧‧導電圖案

Claims (7)

  1. 一種薄膜電晶體，包括：一閘極位於一基板上；一閘極介電層位於該閘極與該基板上；一源極/汲極位於該閘極兩側的該閘極介電層上；一通道層位於該閘極中間部份的閘極介電層上，且該通道層接觸該源極/汲極；以及一絕緣蓋層覆蓋該通道層，其中該通道層包括一氧化物半導體，且該絕緣蓋層的下表面寬度小於該通道層的上表面寬度。
  2. 如申請專利範圍第1項所述之薄膜電晶體，其中該絕緣蓋層包括一有機材料或一無機材料。
  3. 如申請專利範圍第2項所述之薄膜電晶體，其中該有機材料包括壓克力系材料。
  4. 如申請專利範圍第2項所述之薄膜電晶體，其中該無機材料包括氧化矽、氮化矽、氮氧化矽、氧化鋁、氧化鈦、氧化鉿、或氮化鋁。
  5. 如申請專利範圍第1項所述之薄膜電晶體，其中該絕緣蓋層之下表面與該通道層之上表面兩者之間的寬度差距大於0μm且小於或等於2μm。
  6. 如申請專利範圍第1項所述之薄膜電晶體，更包括：一保護層位於該絕緣蓋層、該源極/汲極、與該閘極介電層上；一接觸孔穿過該保護層以露出部份該汲極；以及一導電圖案位於該保護層上以作為一畫素電極，且該 導電圖案經該接觸孔接觸該汲極。
  7. 如申請專利範圍第1項所述之薄膜電晶體，其中該源極/汲極之材料包括銅。
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