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TWI338342B - - Google Patents

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Publication number
TWI338342B
TWI338342B TW096120517A TW96120517A TWI338342B TW I338342 B TWI338342 B TW I338342B TW 096120517 A TW096120517 A TW 096120517A TW 96120517 A TW96120517 A TW 96120517A TW I338342 B TWI338342 B TW I338342B
Authority
TW
Taiwan
Prior art keywords
mold
resin
cavity
electronic component
substrate
Prior art date
Application number
TW096120517A
Other languages
English (en)
Chinese (zh)
Other versions
TW200811968A (en
Inventor
Hiroki Okamoto
Original Assignee
Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Towa Corp filed Critical Towa Corp
Publication of TW200811968A publication Critical patent/TW200811968A/zh
Application granted granted Critical
Publication of TWI338342B publication Critical patent/TWI338342B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
TW096120517A 2006-08-25 2007-06-07 Resin sealing apparatus for electronics parts TW200811968A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006228941A JP5128095B2 (ja) 2006-08-25 2006-08-25 電子部品の樹脂封止成形装置

Publications (2)

Publication Number Publication Date
TW200811968A TW200811968A (en) 2008-03-01
TWI338342B true TWI338342B (ja) 2011-03-01

Family

ID=39129145

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096120517A TW200811968A (en) 2006-08-25 2007-06-07 Resin sealing apparatus for electronics parts

Country Status (4)

Country Link
JP (1) JP5128095B2 (ja)
KR (1) KR100848746B1 (ja)
CN (1) CN100536100C (ja)
TW (1) TW200811968A (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6027569B2 (ja) * 2014-03-26 2016-11-16 エムテックスマツムラ株式会社 中空パッケージの製造方法および中空パッケージ
JP6298719B2 (ja) * 2014-06-09 2018-03-20 Towa株式会社 樹脂封止装置及び樹脂封止方法
JP6549531B2 (ja) * 2016-06-30 2019-07-24 Towa株式会社 樹脂成形装置及び樹脂成形品の製造方法
EP4181185A4 (en) 2020-07-28 2023-09-13 Huawei Technologies Co., Ltd. POWER MODULE AND PRODUCTION FORM AND DEVICE

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3304513B2 (ja) * 1993-06-29 2002-07-22 アピックヤマダ株式会社 放熱体付半導体装置及びその製造方法
SG50009A1 (en) * 1996-03-14 1998-06-15 Towa Corp Method of sealing electronic component with molded resin
JPH11274196A (ja) 1998-03-26 1999-10-08 Seiko Epson Corp 半導体装置の製造方法およびモールドシステム並びに半導体装置
JP4273592B2 (ja) 1999-10-08 2009-06-03 株式会社デンソー 樹脂封止型半導体装置の製造方法
JP2003197664A (ja) * 2001-12-28 2003-07-11 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器

Also Published As

Publication number Publication date
JP2008053509A (ja) 2008-03-06
CN100536100C (zh) 2009-09-02
TW200811968A (en) 2008-03-01
KR100848746B1 (ko) 2008-07-25
JP5128095B2 (ja) 2013-01-23
KR20080018791A (ko) 2008-02-28
CN101131946A (zh) 2008-02-27

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