TWI382506B - Method and structure of multi-chip stack having central pads with upward active surfaces - Google Patents
Method and structure of multi-chip stack having central pads with upward active surfaces Download PDFInfo
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Description
本發明係有關於半導體裝置,特別係有關於一種中央銲墊型晶片之主動面朝上堆疊方法與構造。The present invention relates to semiconductor devices, and more particularly to an active face-up stacking method and configuration for a center pad type wafer.
目前在半導體之封裝結構中,允許將多個相同記憶體容量之晶片封裝在同一封裝體內,以達到兩倍或兩倍以上容量之功能,例如:將兩個記憶體容量為512M之晶片結合封裝而得到一個記憶體容量為1024M之封裝構造,即所謂的「多晶片模組封裝」(Multi-Chip Module package,MCM package)。傳統的半導體晶片如不是中央銲墊(central pad)型晶片就是周圍銲墊(peripheral pad)型晶片,一般而言,採用中央銲墊型晶片通常適合達到半導體元件的高速度運作。惟現今產業上,主動面朝上的多晶片堆疊等各種封裝產品係可採用覆線膠層(Film Over Wire,FOW),作為晶片間隔之填充與保護銲線,然大部分都僅止於周圍銲墊型晶片的應用,對於中央銲墊型晶片卻有著無法廣泛的應用問題,這是因為連接中央銲墊的銲線係為長銲線,有著過高線弧並且在晶片之間的銲線長度更長,使得長銲線容易碰觸到上下晶片造成短路以及長銲線甩線的風險。Currently, in a semiconductor package structure, a plurality of chips having the same memory capacity are allowed to be packaged in the same package to achieve a function of twice or more than a capacity, for example, a wafer-bonded package having two memory capacities of 512M. A package structure having a memory capacity of 1024 M is obtained, which is a so-called "Multi-Chip Module package" (MCM package). A conventional semiconductor wafer, such as a central pad type wafer, is a peripheral pad type wafer. Generally, a center pad type wafer is generally suitable for achieving high speed operation of a semiconductor element. However, in today's industry, various package products such as multi-chip stacks with active face-up are available with Film Over Wire (FOW) as the filling and protection bonding wires for wafer spacers, but most of them only end around. The application of pad-type wafers has a wide range of application problems for central pad type wafers because the bonding wires connecting the central pads are long bonding wires, which have excessively high arcs and bond wires between the wafers. The longer length makes the long wire easy to touch the upper and lower wafers causing short circuit and long wire bonding risk.
為了使中央銲墊型晶片達到以晶片正面堆疊之多晶片堆疊封裝,一種習知的中央銲墊型晶片之主動面朝上堆疊方法已揭示於證書號數第I250597號專利案「在晶片堆疊之間膠合銲線之多晶片封裝方法」。如第1圖所示,第一晶片120設置於基板110,再將一第一黏晶膠層130形成於第一晶片120之主動面121,但須為圖案化以使該第一黏晶膠層130顯露出該第一晶片120之銲墊122。接著,進行一打線步驟,藉由複數個長銲線140電性連接該第一晶片120至基板110。在黏晶操作以設置第二晶片150時,一第二黏晶膠層160(即覆線膠層(Film Over Wire,FOW))可預先形成於第二晶片150之背面152,該第二晶片150之主動面151係具有中央銲墊153。當該第二晶片150取放至該第一黏晶膠層130上,經施壓與加熱以使該第一黏晶膠層130與該第二黏晶膠層160共同包覆該些長銲線140。然而,該第一黏晶膠層130在第一晶片120之主動面121留有一中央空隙,並且第二黏晶膠層160必須能發揮降低該些長銲線140線弧的功能導致其流動性過差,使得該第二黏晶膠層160無法如預期般地完全填滿此一中央空隙,晶片間黏著強度不佳,造成在封裝時於產品內部產生空洞,甚至導致產品在可靠度測試時產生爆裂之情形。In order to achieve a central pad type wafer in a multi-wafer stack package stacked on the front side of the wafer, a conventional method of actively stacking the center pad type wafer is disclosed in the certificate No. I250597 "on the wafer stacking". Multi-chip package method for inter-bonded wire bonding." As shown in FIG. 1 , the first wafer 120 is disposed on the substrate 110 , and a first adhesive layer 130 is formed on the active surface 121 of the first wafer 120 , but must be patterned to make the first adhesive. The layer 130 exposes the pads 122 of the first wafer 120. Next, a wire bonding step is performed to electrically connect the first wafer 120 to the substrate 110 by a plurality of long bonding wires 140. When the die bonding operation is performed to set the second wafer 150, a second adhesive layer 160 (ie, a Film Over Wire (FOW)) may be formed in advance on the back surface 152 of the second wafer 150, the second wafer. The active surface 151 of 150 has a center pad 153. When the second wafer 150 is taken onto the first adhesive layer 130, the first adhesive layer 130 and the second adhesive layer 160 are coated together to form the long solder. Line 140. However, the first adhesive layer 130 has a central gap in the active surface 121 of the first wafer 120, and the second adhesive layer 160 must function to reduce the line arc of the long bonding wires 140 to cause fluidity. Too bad, the second adhesive layer 160 can not completely fill the central void as expected, the adhesion between the wafers is not good, resulting in voids inside the product during packaging, and even when the product is tested for reliability. The situation of bursting.
另一種習知的中央銲墊型晶片之主動面朝上堆疊方法與構造,揭示於證書號數第I258823號專利案「半導體多晶片封裝及製造方法」,主要係由下晶片、絕緣支撐結構、長銲線以及上晶片所組成,其中絕緣支撐結構係呈圖案狀局部配置於下晶片之主動面上,而位於下晶片之中間銲墊的外側,例如條狀或丘狀,用以直接支撐上晶片,在上下晶片之間提供絕緣空間,但須顯露下晶片之中間銲墊。在打線之後,在下晶片之主動面另額外提供一覆線膠材(即所稱之間隙物材料)。其中覆線膠材係局部塗佈於該下晶片之主動面上,以局部包覆長銲線。在黏晶操作中,以熱壓合將上晶片黏合至下晶片上,維持一段時間以使得覆線膠材被下壓而向周邊膠擴散。然黏晶的時間甚短,不足以提供良好膠擴散現象,使膠擴散的方向不可控制,並且膠擴散的範圍為不規則。因此,須黏晶時進行膠擴散之覆線膠材具有低落的有效黏晶面積與不佳的黏晶強度。此外,在絕緣支撐結構之阻礙下,會減少覆線膠材在上下晶片之間的空隙填充效果,在絕緣支撐結構之邊緣易產生空隙,降低了整個封裝產品的可靠度,在黏設上晶片時更有密封絕緣支撐結構的困難。Another conventional method and structure for the active face-up stacking of a central pad type wafer is disclosed in the "Semiconductor Multi-Wafer Package and Manufacturing Method" of the No. I258823 patent, which is mainly composed of a lower wafer, an insulating support structure, The long bonding wire and the upper wafer are formed, wherein the insulating supporting structure is partially disposed on the active surface of the lower wafer in a pattern, and is located outside the intermediate pad of the lower wafer, for example, strip or mound for direct support The wafer provides an insulating space between the upper and lower wafers, but the intermediate pads of the lower wafer must be exposed. After the wire is applied, an additional layer of glue (the so-called spacer material) is additionally provided on the active surface of the lower wafer. The covering glue is partially coated on the active surface of the lower wafer to partially coat the long bonding wire. In the die bonding operation, the upper wafer is bonded to the lower wafer by thermocompression bonding for a period of time so that the overlying adhesive material is pressed down to diffuse toward the peripheral glue. However, the time of the sticky crystal is very short, which is not enough to provide good gel diffusion, so that the direction of diffusion of the glue is uncontrollable, and the range of gel diffusion is irregular. Therefore, the coated glue which is required to carry out the diffusion of the glue at the time of sticking has a low effective effective crystal area and a poor adhesive strength. In addition, under the hindrance of the insulating support structure, the gap filling effect between the upper and lower wafers of the overlying adhesive material is reduced, and the gap is easily generated at the edge of the insulating support structure, thereby reducing the reliability of the entire packaged product, and the wafer is bonded. It is more difficult to seal the insulating support structure.
為了解決上述之問題,本發明之主要目的係在於提供一種中央銲墊型晶片之主動面朝上堆疊方法與構造,有較佳的有效黏晶面積與黏晶強度,並可以改變晶片間長銲線的線弧形狀為更低更平坦,不需要具有特殊高硬度的銲線,也不會有碰觸上晶片背面的風險。此外,上下晶片之間有較佳的密封效果,能防止於產品內部產生空洞,並具有黏晶作業的便利性。In order to solve the above problems, the main object of the present invention is to provide an active face-up stacking method and structure of a center pad type wafer, which has a better effective die area and a die bond strength, and can change the long inter-wafer soldering. The line arc shape of the wire is lower and flatter, does not require a wire with a particularly high hardness, and there is no risk of touching the back side of the wafer. In addition, there is a better sealing effect between the upper and lower wafers, which prevents voids inside the product and has the convenience of die bonding operation.
本發明之次一目的係在於提供一種中央銲墊型晶片之主動面朝上堆疊方法與構造,在黏晶之後能使長銲線得到完善的保護,可增加晶片之間的黏著強度以及增加銲線在晶片上焊點的固著力,進而降低了長銲線甩線之情況發生。A second object of the present invention is to provide an active face-up stacking method and structure of a central pad type wafer, which can provide perfect protection of the long bonding wire after the bonding, can increase the adhesion strength between the wafers and increase the welding. The fixing force of the wire on the solder joint on the wafer, which in turn reduces the occurrence of long wire bonding.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種中央銲墊型晶片之主動面朝上堆疊方法,主要包含有以下步驟:提供一複合式黏晶膠帶,具有一第一黏著層與一第二黏著層,該第一黏著層係較薄於該第二黏著層。貼附該複合式黏晶膠帶至一第一晶片,以該第一黏著層黏附該第一晶片之背面。提供一第二晶片,該第二晶片係已設置於一基板上,該第二晶片之主動面係設有複數個中央銲墊,並經由複數個第一銲線電性連接至該基板。進行一黏晶操作,使該第一晶片設置至該第二晶片之主動面之上,在黏晶操作中,該第二黏著層係較軟於該第一黏著層,以局部密封該些第一銲線,並且藉由該第一黏著層的阻隔以降低該些第一銲線之弧高,令該些第一銲線不碰觸至該第一晶片之背面。本發明另揭示依照上述方法所製成之中央銲墊型晶片之主動面朝上堆疊構造。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses an active face-up stacking method for a central pad type wafer, which mainly comprises the following steps: providing a composite adhesive crystal tape having a first adhesive layer and a second adhesive layer, the first adhesive layer Thinner than the second adhesive layer. The composite adhesive tape is attached to a first wafer, and the first adhesive layer is adhered to the back surface of the first wafer. A second wafer is provided. The second wafer is disposed on a substrate. The active surface of the second wafer is provided with a plurality of central pads, and is electrically connected to the substrate via a plurality of first bonding wires. Performing a die bonding operation to set the first wafer over the active surface of the second wafer. In the die bonding operation, the second adhesive layer is softer than the first adhesive layer to partially seal the first a bonding wire, and by blocking the first adhesive layer to lower the arc height of the first bonding wires, so that the first bonding wires do not touch the back surface of the first bonding chip. The present invention further discloses an active face-up stacking configuration of a center pad type wafer fabricated in accordance with the above method.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在提供第二晶片之後與進行黏晶操作之前,可另包含之步驟為:塗佈一液態狀絕緣層於該第二晶片之主動面,並使該絕緣層覆蓋該些第一銲線在該些中央銲墊上的焊點,再使該絕緣層固化。In the above-mentioned active face-up stacking method of the central pad type wafer, after the second wafer is provided and before the die bonding operation, the method further includes: coating a liquid insulating layer on the second wafer The active surface is covered, and the insulating layer covers the solder joints of the first bonding wires on the central solder pads, and then the insulating layer is cured.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,該第二黏著層係可黏附該絕緣層,藉由該絕緣層的阻隔,令該些第一銲線不碰觸至該第二晶片之主動面。In the above-mentioned active face-up stacking method of the central pad type wafer, the second adhesive layer can adhere the insulating layer, and the first bonding wire does not touch the first layer by the barrier of the insulating layer. The active surface of the two wafers.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,該液態狀絕緣層係可選自於底部填充膠與液態環氧化合物之其中之一,而具有能佈滿該第二晶片之主動面的流動性。In the active face-up stacking method of the central pad type wafer, the liquid insulating layer may be selected from one of an underfill and a liquid epoxy compound, and has a second wafer. The mobility of the active surface.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,該液態狀絕緣層的塗佈方法係可選自於點劃膠與噴灑之其中之一。In the above-described active face-up stacking method of the center pad type wafer, the liquid-like insulating layer coating method may be selected from one of dashing and spraying.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,可在黏晶操作中,使該些第一銲線受到擠壓而呈多彎曲狀,使該些第一銲線之上弧區碰觸至該第一黏著層,並且該些第一銲線之下弧區碰觸至該絕緣層。In the above-mentioned active face-up stacking method of the central pad type wafer, in the die bonding operation, the first bonding wires may be squeezed to have a multi-bend shape, so that the first bonding wires are arc-shaped. The area touches the first adhesive layer, and the arc areas below the first bonding wires touch the insulating layer.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在黏晶操作中,使該第二黏著層係可較軟於該第一黏著層的方法係為預先固化該第一黏著層。In the above-described active face-up stacking method of the center pad type wafer, in the die bonding operation, the method of making the second adhesive layer softer than the first adhesive layer is to pre-cure the first adhesive layer. .
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在黏晶操作中,使該第二黏著層係可較軟於該第一黏著層的方法係使該第一黏著層的玻璃態轉移溫度高於該第二黏著層的玻璃態轉移溫度。In the above-described active face-up stacking method of the center pad type wafer, in the die bonding operation, the method of making the second adhesive layer softer than the first adhesive layer is to make the glass of the first adhesive layer The state transition temperature is higher than the glass transition temperature of the second adhesive layer.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,該第一晶片與該第二晶片係可為實質相同,而具有相同尺寸與功能,並且該第一晶片之主動面亦設有複數個中央銲墊。In the above-described active face-up stacking method of the central pad type wafer, the first wafer and the second wafer system may be substantially the same, and have the same size and function, and the active surface of the first wafer is also provided. A plurality of central pads.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在黏晶操作之後,可另包含之步驟為:形成複數個第二銲線,係電性連接該第一晶片之中央銲墊至該基板。In the active face-up stacking method of the central pad type wafer, after the die bonding operation, the method further comprises the steps of: forming a plurality of second bonding wires electrically connecting the central pads of the first wafer To the substrate.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在形成第二銲線之後,可另包含之步驟為:設置複數個線固定件於該第一晶片之主動面上,以固定該些第二銲線。In the above-mentioned active face-up stacking method of the central pad type wafer, after the second bonding wire is formed, the method further includes the steps of: providing a plurality of wire fixing members on the active surface of the first wafer to fix The second bonding wires.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在形成第二銲線之後,可另包含之步驟為:形成一封膠體於該基板上,以密封該第一晶片、該第二晶片、該些第一銲線及該些第二銲線。In the above-mentioned active face-up stacking method of the central pad type wafer, after the second bonding wire is formed, the method further includes the steps of: forming a gel on the substrate to seal the first wafer, the first Two wafers, the first bonding wires and the second bonding wires.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在形成該封膠體之後,可另包含之步驟為:設置複數個銲球於該基板之下表面。In the active face-up stacking method of the central pad type wafer, after the sealing body is formed, the method further includes the step of: setting a plurality of solder balls on the lower surface of the substrate.
在前述之中央銲墊型晶片之主動面朝上堆疊方法中,在貼附該複合式黏晶膠帶之步驟係可實施於晶圓等級,其中該第一晶片係為在晶圓中之一未切割晶粒。In the above-described active face-up stacking method of the central pad type wafer, the step of attaching the composite adhesive tape can be implemented at a wafer level, wherein the first wafer is one of the wafers. Cutting the grains.
由以上技術方案可以看出,本發明之中央銲墊型晶片之主動面朝上堆疊方法與構造,具有以下優點與功效:It can be seen from the above technical solution that the active face-up stacking method and structure of the central pad type wafer of the present invention has the following advantages and effects:
一、可藉由提供複合式黏晶膠帶作為其中一技術手段,由於複合式黏晶膠帶具有第一黏著層與第二黏著層,在黏晶操作中,第二黏著層係較軟於第一黏著層,以局部密封長銲線,並且藉由第一黏著層的阻隔以降低長銲線之弧高,令長銲線不碰觸至上晶片之背面。第二黏著層提供較佳的有效黏晶面積與黏晶強度。因此,可以改變晶片間長銲線的線弧形狀為更低更平坦,不需要具有特殊高硬度的銲線,也不會有碰觸上晶片背面的風險。First, by providing a composite adhesive tape as one of the technical means, since the composite adhesive tape has a first adhesive layer and a second adhesive layer, in the die bonding operation, the second adhesive layer is softer than the first The adhesive layer is used to partially seal the long bonding wire, and the barrier of the first adhesive layer is used to lower the arc height of the long bonding wire so that the long bonding wire does not touch the back surface of the upper wafer. The second adhesive layer provides a better effective die area and die bond strength. Therefore, the shape of the line arc of the long wire between the wafers can be changed to be lower and flatter, the wire having a particularly high hardness is not required, and there is no risk of touching the back side of the wafer.
二、可藉由提供複合式黏晶膠帶與塗佈液態狀絕緣層作為其中一技術手段,由於塗佈液態狀絕緣層於第二晶片之主動面,並使絕緣層覆蓋銲線在中央銲墊上的焊點,故在黏晶之後可增加第二黏著層的黏著強度以及增加長銲線在晶片上焊點的固著力,進而降低了長銲線甩線之情況發生。Second, by providing a composite adhesive tape and coating a liquid insulating layer as one of the technical means, since the liquid insulating layer is coated on the active surface of the second wafer, and the insulating layer covers the bonding wire on the central pad The solder joints can increase the adhesion strength of the second adhesive layer and increase the fixing force of the long solder wire on the wafer after the adhesion, thereby reducing the occurrence of the long bond wire.
三、可藉由提供複合式黏晶膠帶與塗佈液態狀絕緣層作為其中一技術手段,由於第二黏著層能提供較佳的有效黏晶面積與黏晶強度,使得第一晶片與第二晶片之間有較佳的密封效果,能防止於產品內部產生空洞。Third, by providing a composite adhesive tape and coating a liquid insulating layer as one of the technical means, since the second adhesive layer can provide a better effective die area and die bond strength, the first wafer and the second wafer There is a better sealing effect between the wafers to prevent voids inside the product.
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例,一種中央銲墊型晶片之主動面朝上堆疊方法舉例說明於第2A至2K圖之元件截面示意圖。詳細步驟說明如下所示。In accordance with an embodiment of the present invention, an active face-up stacking method for a center pad type wafer is illustrated in a cross-sectional view of the elements of FIGS. 2A-2K. The detailed steps are explained below.
首先,請參閱第2A圖所示,提供一複合式黏晶膠帶210,具有一第一黏著層211與一第二黏著層212,該第一黏著層211係較薄於該第二黏著層212。該第一黏著層211與該第二黏著層212係具有不同的黏膠特性與作用,兩黏著層可具有不相同的固化溫度,例如該第一黏著層211之固化溫度低於該第二黏著層212之固化溫度;或者,兩黏著層具有不同的固化模式,例如該第一黏著層211可為光固化性,該第二黏著層212可為熱固化性。在一較佳實施例中,該第一黏著層211係可選自切割黏膠(Dicing Die Adhesive Film,DDAF),而該第二黏著層212係可選自覆線膠層(Film Over Wire,FOW),能在室溫下呈固態膜片型態為較佳。在不同實施例中,該第一黏著層211與/或該第二黏著層212過於膠液狀,可在該第二黏著層212之下貼附一可撕離承載膜(圖未繪出),以便於進行該複合式黏晶膠帶210之傳輸與貼附作業。另在黏晶操作時,該第一黏著層211之材質須較硬於該第二黏著層212。詳細而言,該第一黏著層211之主要作用包含:(1)黏著上晶片之晶背、(2)改變以降低打線弧高、與(3)保護長銲線以避免接觸上晶片之晶背。而該第二黏著層212之主要作用包含:(1)黏著下晶片、(2)包覆與固定長銲線在晶片間之線弧、與(3)覆蓋絕緣層。First, as shown in FIG. 2A, a composite adhesive tape 210 is provided, which has a first adhesive layer 211 and a second adhesive layer 212. The first adhesive layer 211 is thinner than the second adhesive layer 212. . The first adhesive layer 211 and the second adhesive layer 212 have different adhesive properties and functions, and the two adhesive layers may have different curing temperatures. For example, the curing temperature of the first adhesive layer 211 is lower than the second adhesive. The curing temperature of the layer 212; or, the two adhesive layers have different curing modes, for example, the first adhesive layer 211 may be photocurable, and the second adhesive layer 212 may be thermosetting. In a preferred embodiment, the first adhesive layer 211 can be selected from Dicing Die Adhesive Film (DDAF), and the second adhesive layer 212 can be selected from a Film Over Wire (Film Over Wire). FOW) is preferably a solid film type at room temperature. In different embodiments, the first adhesive layer 211 and/or the second adhesive layer 212 are too glued, and a peelable carrier film may be attached under the second adhesive layer 212 (not shown). In order to facilitate the transfer and attachment of the composite adhesive tape 210. In the case of the die bonding operation, the material of the first adhesive layer 211 must be harder than the second adhesive layer 212. In detail, the main functions of the first adhesive layer 211 include: (1) adhering the crystal back of the wafer, (2) changing to lower the arc height of the wire, and (3) protecting the long wire to avoid contact with the crystal of the wafer. Back. The main functions of the second adhesive layer 212 include: (1) adhering the lower wafer, (2) coating and fixing the long bonding wire between the wafers, and (3) covering the insulating layer.
請參閱第2B圖所示,貼附該複合式黏晶膠帶210至一第一晶片220,以該第一黏著層211黏附該第一晶片220之背面221。在本實施例中,在貼附該複合式黏晶膠帶210之步驟係可實施於晶圓等級,其中該第一晶片220係為在晶圓中之一未切割晶粒,並且該晶圓已完成所需積體電路的製作。在該步驟之後,該第一黏著層211可為半固化或完全固化。Referring to FIG. 2B, the composite adhesive tape 210 is attached to a first wafer 220, and the first adhesive layer 211 is adhered to the back surface 221 of the first wafer 220. In this embodiment, the step of attaching the composite adhesive tape 210 can be implemented at a wafer level, wherein the first wafer 220 is an uncut die in the wafer, and the wafer has Complete the production of the required integrated circuit. After this step, the first adhesive layer 211 may be semi-cured or fully cured.
再如第2C圖所示,藉由一刀具224切割該晶圓,以分離該第一晶片220。此時,該第一晶片220係已貼附有該複合式黏晶膠帶210,該第二黏著層212為外露。As further shown in FIG. 2C, the wafer is diced by a cutter 224 to separate the first wafer 220. At this time, the first die 220 is attached with the composite adhesive tape 210, and the second adhesive layer 212 is exposed.
請參閱第2D圖所示,提供一第二晶片230,該第二晶片230係已設置於一基板240上,該第二晶片230之主動面231係設有複數個中央銲墊232,並經由複數個第一銲線250電性連接至該基板240,故該些第一銲線250可視為長銲線。其中,該些第一銲線250係可為金線。在本實施例中,如第2B、2D與2H圖所示,該第一晶片220與該第二晶片230係可為實質相同,而具有相同尺寸與功能,並且該第一晶片220之主動面223亦設有複數個中央銲墊222。在一較佳實施例中,該第二晶片230係可藉由一黏晶層233黏合該第二晶片230之背面與該基板240之上表面。該些第一銲線250係具有一打線弧高。在此所稱之「弧高」係指該些第一銲線250之線弧最高點至該第二晶片230之主動面231之間的高度。由於該第一黏著層211在黏晶過程中須發揮能壓迫該些第一銲線250往下以降低弧高之作用。故在本步驟中包含的打線製程中,毋須考慮該些第一銲線250之打線弧高,不會限制到打線製程的產能。As shown in FIG. 2D, a second wafer 230 is provided. The second wafer 230 is disposed on a substrate 240. The active surface 231 of the second wafer 230 is provided with a plurality of central pads 232. A plurality of first bonding wires 250 are electrically connected to the substrate 240, so the first bonding wires 250 can be regarded as long bonding wires. The first bonding wires 250 may be gold wires. In this embodiment, as shown in FIGS. 2B, 2D, and 2H, the first wafer 220 and the second wafer 230 can be substantially the same, and have the same size and function, and the active surface of the first wafer 220 223 also has a plurality of central pads 222. In a preferred embodiment, the second wafer 230 is bonded to the back surface of the second wafer 230 and the upper surface of the substrate 240 by a die bonding layer 233. The first bonding wires 250 have a one-line arc height. The term "arc height" as used herein refers to the height between the highest point of the line arc of the first bonding wires 250 to the active surface 231 of the second wafer 230. Since the first adhesive layer 211 is required to press the first bonding wires 250 downward to reduce the arc height during the die bonding process. Therefore, in the wire bonding process included in this step, it is not necessary to consider the arcing height of the first bonding wires 250, and the production capacity of the wire bonding process is not limited.
在該些第一銲線250形成之後,接著如第2E圖所示,可藉由一噴頭261塗佈一液態狀絕緣層260於該第二晶片230之主動面231,並使該絕緣層260覆蓋該些第一銲線250在該些中央銲墊232上的焊點(或稱線頭、結球端),再使該絕緣層260固化。詳細而言,該絕緣層260之主要作用包含:(1)保護銲線頭、(2)防止長銲線碰觸晶片表面而短路、(3)增進對覆線膠層的黏著力。在一實施例中,可藉由加熱或照射UV光方式使該絕緣層260係可為完全固化或局部固化。在本實施例中,該絕緣層260係可選自於底部填充膠與液態環氧化合物之其中之一,而具有能佈滿該第二晶片230之主動面231的高流動性,並且該絕緣層260係形成有一不平整面,以增強黏著強度。更具體地,該液態狀絕緣層260的塗佈方法係可選自於點劃膠與噴灑之其中之一,以使該液態狀絕緣層260可以完全覆蓋該第二晶片230之主動面231。並且當該絕緣層260固化之後,還能用以固定該些第一銲線250之線頭,以防止該些第一銲線250碰觸至該第二晶片230之主動面231,而造成短路之情形。此外,能夠避免以印刷方法形成而壓傷該些第一銲線250,也能避免該些第一銲線250在該主動面231上的線弧部份會沾染過多的絕緣材料。After the first bonding wires 250 are formed, as shown in FIG. 2E, a liquid insulating layer 260 is applied to the active surface 231 of the second wafer 230 by a showerhead 261, and the insulating layer 260 is applied. The solder joints (or wire ends, ball ends) of the first bonding wires 250 on the central pads 232 are covered, and the insulating layer 260 is cured. In detail, the main functions of the insulating layer 260 include: (1) protecting the wire bond head, (2) preventing the long wire from touching the surface of the wafer and short-circuiting, and (3) improving the adhesion to the wire coating layer. In one embodiment, the insulating layer 260 can be fully cured or partially cured by heating or irradiating UV light. In this embodiment, the insulating layer 260 may be selected from one of an underfill and a liquid epoxy compound, and has a high fluidity capable of covering the active surface 231 of the second wafer 230, and the insulation Layer 260 is formed with an uneven surface to enhance adhesion strength. More specifically, the coating method of the liquid insulating layer 260 may be selected from one of dashing and spraying, so that the liquid insulating layer 260 may completely cover the active surface 231 of the second wafer 230. And after the insulating layer 260 is cured, the wire ends of the first bonding wires 250 can be fixed to prevent the first bonding wires 250 from contacting the active surface 231 of the second wafer 230, thereby causing a short circuit. The situation. In addition, it is possible to avoid the formation of the first bonding wire 250 by the printing method, and it is also possible to prevent the wire portion of the first bonding wire 250 on the active surface 231 from being contaminated with excessive insulating material.
請參閱第2F至2H圖所示,進行一黏晶操作,使該第一晶片220設置至該第二晶片230之主動面231之上。如第2F圖所示,在黏晶操作的開始過程中,該第二黏著層212係較軟於該第一黏著層211,該些第一銲線250可嵌入該第二黏著層212,以被局部密封,並且該些第一銲線250會開始受到該第一黏著層211向下壓迫而產生彎曲。接著,在黏晶操作的中間過程中,如第2G圖所示,該第一晶片220持續下壓,藉由該第一黏著層211的阻隔以降低該些第一銲線250之弧高,令該些第一銲線250不碰觸至該第一晶片220之背面221,並逐漸降低整體的彎曲幅度。再如第2H圖所示,將該第一晶片220以該第二黏著層212黏合至該絕緣層260上,以完成上述黏晶操作。此時,如第2H圖所示,該些第一銲線250受到擠壓而呈多彎曲狀,使該些第一銲線250之上弧區碰觸至該第一黏著層211,並且該些第一銲線250之下弧區碰觸至該絕緣層260。較佳地,由於該第二黏著層212係可黏附該絕緣層260,藉由該絕緣層260的阻隔,令該些第一銲線250不碰觸至該第二晶片230之主動面231。此外,由於該第二黏著層212受熱之後會轉化成一種膠稠態之膠體,可提供較佳的有效黏晶面積與黏晶強度,能夠與該液態狀絕緣層260緊密地黏合,故可增加該第二黏著層212與該絕緣層260之間的黏著力,以強化整體結構。在一較佳實施例中,在黏晶操作中,使該第二黏著層212係較軟於該第一黏著層211的方法係可為預先固化該第一黏著層211,例如實施在上述貼附步驟之後。在另一變化實施例中,在黏晶操作中,使該第二黏著層212係較軟於該第一黏著層211的方法係可使該第一黏著層211的玻璃態轉移溫度高於該第二黏著層212的玻璃態轉移溫度,使得在黏晶溫度時,該第一黏著層211相對於該第二黏著層212有著更高的流動性與濕潤性。因此,藉由該第一黏著層211、該第二黏著層212與該絕緣層260之組合,能使該第一銲線250得到較佳的保護,黏晶後線弧控制在該第二黏著層212內而更加平整,不至於與該第一晶片220之背面與該第二晶片230之主動面產生短路,也降低了甩線的風險。Referring to FIGS. 2F to 2H, a die bonding operation is performed to place the first wafer 220 over the active surface 231 of the second wafer 230. As shown in FIG. 2F, during the start of the die bonding operation, the second adhesive layer 212 is softer than the first adhesive layer 211, and the first bonding wires 250 may be embedded in the second adhesive layer 212 to The portion is sealed, and the first bonding wires 250 are initially pressed by the first adhesive layer 211 to be bent. Then, in the intermediate process of the die bonding operation, as shown in FIG. 2G, the first wafer 220 is continuously pressed down, and the arc of the first bonding wires 250 is lowered by the barrier of the first adhesive layer 211. The first bonding wires 250 are not touched to the back surface 221 of the first wafer 220, and the overall bending amplitude is gradually reduced. As shown in FIG. 2H, the first wafer 220 is bonded to the insulating layer 260 by the second adhesive layer 212 to complete the above-mentioned die bonding operation. At this time, as shown in FIG. 2H, the first bonding wires 250 are pressed to be multi-bent, so that the arc regions above the first bonding wires 250 touch the first adhesive layer 211, and the The arc regions below the first bonding wires 250 touch the insulating layer 260. Preferably, since the second adhesive layer 212 can adhere to the insulating layer 260, the first bonding wires 250 do not touch the active surface 231 of the second wafer 230 by the barrier of the insulating layer 260. In addition, since the second adhesive layer 212 is converted into a colloidal colloid after being heated, it can provide a better effective crystallite area and a cohesive strength, and can be closely adhered to the liquid insulating layer 260, thereby increasing The adhesion between the second adhesive layer 212 and the insulating layer 260 is to strengthen the overall structure. In a preferred embodiment, the method of making the second adhesive layer 212 softer than the first adhesive layer 211 in the die bonding operation may be pre-curing the first adhesive layer 211, for example, in the above paste. After the steps are attached. In another variation, in the die bonding operation, the method of making the second adhesive layer 212 softer than the first adhesive layer 211 is such that the glass transition temperature of the first adhesive layer 211 is higher than the The glass transition temperature of the second adhesive layer 212 is such that the first adhesive layer 211 has higher fluidity and wettability with respect to the second adhesive layer 212 at the die bonding temperature. Therefore, the first bonding wire 250 can be better protected by the combination of the first adhesive layer 211, the second adhesive layer 212 and the insulating layer 260, and the bonding line arc is controlled at the second bonding. The layer 212 is more flat and does not cause a short circuit with the back surface of the first wafer 220 and the active surface of the second wafer 230, which also reduces the risk of twisting.
更進一步地,如第2I圖所示,在黏晶操作之後,可另包含之步驟為:形成複數個第二銲線270,係電性連接該第一晶片220之該些中央銲墊222至該基板240。接著,如第2J圖所示,在形成該些第二銲線270之後,可另包含之步驟為:設置複數個線固定件271於該第一晶片220之主動面上,以固定該些第二銲線270。該些線固定件271可為糊狀團塊,以固定該些第二銲線270之一線段。藉由該些線固定件271能補強該些第二銲線270之整體結構,以避免在後續製程中產生甩線之問題。Further, as shown in FIG. 2I, after the die bonding operation, the method further includes: forming a plurality of second bonding wires 270 electrically connected to the central pads 222 of the first wafer 220 to The substrate 240. Then, as shown in FIG. 2J, after the second bonding wires 270 are formed, the method further includes: providing a plurality of wire fixing members 271 on the active surface of the first wafer 220 to fix the first Second weld line 270. The wire fixing members 271 may be paste-like agglomerates to fix one of the second bonding wires 270. The wire fixing members 271 can reinforce the overall structure of the second bonding wires 270 to avoid the problem of twisting wires in subsequent processes.
再如第2K圖所示,在形成第二銲線270之後,可另包含之步驟為:形成一封膠體280於該基板240上,以密封該第一晶片220、該第二晶片230、該些第一銲線250及該些第二銲線270。詳細而言,該封膠體280係可完全覆蓋於該基板240之上表面。最後,在形成該封膠體280之後,可另包含之步驟為:設置複數個銲球241於該基板240之下表面(如第3圖所示),即完成本發明之中央銲墊型晶片之主動面朝上堆疊構造。As shown in FIG. 2K, after the second bonding wire 270 is formed, the method further includes: forming a glue 280 on the substrate 240 to seal the first wafer 220, the second wafer 230, and the Some first bonding wires 250 and the second bonding wires 270. In detail, the encapsulant 280 can completely cover the upper surface of the substrate 240. Finally, after forming the encapsulant 280, the method further includes: setting a plurality of solder balls 241 on the lower surface of the substrate 240 (as shown in FIG. 3), that is, completing the central pad type wafer of the present invention. The active face is stacked upwards.
在本發明中,利用提供該複合式黏晶膠帶作為其中一技術手段,由於該複合式黏晶膠帶210係由雙層結構所構成,在黏晶操作該第一黏著層211與該第二黏著層212分別表現出較硬與較軟的材料特性,故在黏晶操作中,該第二黏著層212能嵌埋該些第一銲線250,以局部密封該些第一銲線250,並進一步黏接到該絕緣層260或是該第二晶片230。此外,藉由該第一黏著層211的阻隔以降低該些第一銲線250之弧高,使得該些第一銲線250不碰觸至該第一晶片220之背面。也就是說,本發明能利用在黏晶過程中該第一黏著層211較硬的材質特性,壓迫該些第一銲線250往下,自然地降低該些第一銲線250之弧高。因此,可以改變該第一銲線250的線弧形狀為更低更平坦,不需要具有特殊高硬度的銲線,也不會有碰觸該第一晶片220之背面221的風險。而該第二黏著層212能提供較佳的有效黏晶面積與黏晶強度,並且在有限的厚度中有效包覆該些第一銲線250,能降低多晶片堆疊高度。In the present invention, by providing the composite adhesive tape as one of the technical means, since the composite adhesive tape 210 is composed of a two-layer structure, the first adhesive layer 211 and the second adhesive are operated at the die bonding operation. The layer 212 exhibits a relatively hard and soft material property, so that the second adhesive layer 212 can embed the first bonding wires 250 to partially seal the first bonding wires 250 during the die bonding operation. Further bonding to the insulating layer 260 or the second wafer 230. In addition, the arc of the first bonding wires 250 is lowered by the barrier of the first adhesive layer 211 such that the first bonding wires 250 do not touch the back surface of the first wafer 220. That is, the present invention can utilize the harder material properties of the first adhesive layer 211 during the die bonding process, and press the first bonding wires 250 downward to naturally lower the arc height of the first bonding wires 250. Therefore, the shape of the line arc of the first bonding wire 250 can be changed to be lower and flatter, the bonding wire having a particularly high hardness is not required, and there is no risk of touching the back surface 221 of the first wafer 220. The second adhesive layer 212 can provide a better effective die area and a die bond strength, and effectively coat the first bond wires 250 in a limited thickness, thereby reducing the multi-wafer stack height.
此外,由於塗佈該液態狀絕緣層260於該第二晶片230之主動面231,並使該絕緣層260覆蓋該些第一銲線250在該些中央銲墊232上的焊點,增加該些第一銲線250在該第二晶片230上焊點的固著力,並增加與該第二黏著層212的黏著強度,亦能降低了該些第一銲線250甩線之情況發生。更進一步地,由於該複合式黏晶膠帶210與該絕緣層260係為無縫隙地面對面的緊密黏合,免除了以往容易於產品內部產生空洞之問題,大幅地增加了產品的良率,更不會在後續的線性測試中發生爆裂之情況。In addition, since the liquid insulating layer 260 is coated on the active surface 231 of the second wafer 230, and the insulating layer 260 covers the solder joints of the first bonding wires 250 on the central pads 232, the The adhesion of the first bonding wires 250 on the second wafer 230 and the adhesion strength to the second bonding layer 212 can also reduce the occurrence of the first bonding wires 250. Further, since the composite adhesive tape 210 and the insulating layer 260 are closely adhered to each other without gaps, the problem of easily creating voids inside the product is eliminated, and the yield of the product is greatly increased, and A burst will occur in subsequent linear tests.
本發明還揭示使用前述方法所製成之中央銲墊型晶片之主動面朝上堆疊構造舉例說明於第3圖。該中央銲墊型晶片之主動面朝上堆疊構造主要包含一複合式黏晶膠帶210、一第一晶片220以及一第二晶片230。該複合式黏晶膠帶210係具有一第一黏著層211與一第二黏著層212,該第一黏著層211係較薄於該第二黏著層212。在一較佳實施例中,該第一黏著層211係可為切割黏膠(Dicing Die Adhesive Film,DDAF),而設於該第二黏著層212與該第一黏著層211之間,並且該第二黏著層212係可為覆線膠層(Film Over Wire,FOW),故該第一黏著層211之材質係較硬於該第二黏著層212。該第二黏著層212可作為應力緩衝層,以避免拉傷該些第一銲線250。在本實施例中,該複合式黏晶膠帶210係完整包覆於該第一晶片220之背面221,並藉由該第一黏著層211保護該第一晶片220之背面221,以避免可能的損傷。The present invention also discloses an active face-up stack configuration of a center pad type wafer fabricated using the foregoing method, which is illustrated in FIG. The active face-up stacking structure of the center pad type wafer mainly comprises a composite die bonding tape 210, a first wafer 220 and a second wafer 230. The composite adhesive tape 210 has a first adhesive layer 211 and a second adhesive layer 212. The first adhesive layer 211 is thinner than the second adhesive layer 212. In a preferred embodiment, the first adhesive layer 211 is a Dicing Die Adhesive Film (DDAF), and is disposed between the second adhesive layer 212 and the first adhesive layer 211, and The second adhesive layer 212 can be a Film Over Wire (FOW), so the material of the first adhesive layer 211 is harder than the second adhesive layer 212. The second adhesive layer 212 can serve as a stress buffer layer to avoid straining the first bonding wires 250. In this embodiment, the composite adhesive tape 210 is completely covered on the back surface 221 of the first wafer 220, and the back surface 221 of the first wafer 220 is protected by the first adhesive layer 211 to avoid possible damage.
該第二晶片230係設置於一基板240上,該第二晶片230之主動面231係設有複數個中央銲墊232,並經由複數個第一銲線250電性連接至該基板240。其中,該第一晶片220設置至該第二晶片230之主動面231之上,該第二黏著層212係較軟於該第一黏著層211,以局部密封該些第一銲線250,藉由該第一黏著層211的阻隔以降低該些第一銲線250之弧高,令該些第一銲線250不碰觸至該第一晶片220之背面221。在一較佳實施例中,該第一晶片220與該第二晶片230係可為實質相同,而具有相同尺寸與功能,並且該第一晶片220之主動面223亦設有複數個中央銲墊222。The second wafer 230 is disposed on a substrate 240. The active surface 231 of the second wafer 230 is provided with a plurality of central pads 232 and electrically connected to the substrate 240 via a plurality of first bonding wires 250. The first wafer 220 is disposed on the active surface 231 of the second wafer 230. The second adhesive layer 212 is softer than the first adhesive layer 211 to partially seal the first bonding wires 250. The arc of the first bonding wires 250 is lowered by the first adhesive layer 211 to prevent the first bonding wires 250 from contacting the back surface 221 of the first wafer 220. In a preferred embodiment, the first wafer 220 and the second wafer 230 can be substantially the same, and have the same size and function, and the active surface 223 of the first wafer 220 is also provided with a plurality of central pads. 222.
在本發明中,可另包含一以液態塗佈之絕緣層260,形成於該第二晶片230之主動面231,該絕緣層260覆蓋該些第一銲線250在該些中央銲墊232上的焊點並予以固化。詳細而言,該些第一銲線250係可呈多彎曲狀,該些第一銲線250之上弧區碰觸至該第一黏著層211,並且該些第一銲線250之下弧區碰觸至該絕緣層260。此外,該第二黏著層212係可黏附該絕緣層260,藉由該絕緣層260的阻隔,令該些第一銲線250不碰觸至該第二晶片230之主動面231。較佳地,該液態狀絕緣層260係可選自於底部填充膠與液態環氧化合物之其中之一,而具有能佈滿該第二晶片230之主動面231的流動性。因此,該絕緣層260係可完全覆蓋該第二晶片230之主動面231,經固化之後,更可固定該些第一銲線250,以防止該些第一銲線250碰觸至該第二晶片230之主動面231,而造成短路之情況。In the present invention, an insulating layer 260 coated in a liquid state may be further formed on the active surface 231 of the second wafer 230. The insulating layer 260 covers the first bonding wires 250 on the central pads 232. Solder joints and cure. In detail, the first bonding wires 250 may be in a plurality of curved shapes, the arc regions of the first bonding wires 250 touch the first adhesive layer 211, and the first bonding wires 250 are under the arc. The area touches the insulating layer 260. In addition, the second adhesive layer 212 can adhere to the insulating layer 260. The first bonding wire 250 does not touch the active surface 231 of the second wafer 230 by the barrier of the insulating layer 260. Preferably, the liquid insulating layer 260 is selected from one of an underfill and a liquid epoxy compound, and has fluidity capable of filling the active surface 231 of the second wafer 230. Therefore, the insulating layer 260 can completely cover the active surface 231 of the second wafer 230. After curing, the first bonding wires 250 can be further fixed to prevent the first bonding wires 250 from contacting the second surface. The active surface 231 of the wafer 230 causes a short circuit condition.
更進一步地,在本實施例中,可另包含複數個第二銲線270、複數個線固定件271、一封膠體280以及複數個銲球241。該些第二銲線270係可電性連接該第一晶片220之中央銲墊222至該基板240。該些線固定件271係設置於該第一晶片220之主動面223上,以固定該些第二銲線270,故能補強該些第二銲線270之結構,以避免產生甩線之情況。該封膠體280係可形成於該基板240上,以密封該第一晶片220、該第二晶片230、該些第一銲線250及該些第二銲線270。此外,該些銲球241係可設置於該基板240之下表面,以使該中央銲墊型晶片之主動面朝上堆疊構造能對外連接。Further, in this embodiment, a plurality of second bonding wires 270, a plurality of wire fixing members 271, a glue body 280, and a plurality of solder balls 241 may be further included. The second bonding wires 270 are electrically connected to the central pad 222 of the first wafer 220 to the substrate 240 . The wire fixing members 271 are disposed on the active surface 223 of the first wafer 220 to fix the second bonding wires 270, so that the structures of the second bonding wires 270 can be reinforced to avoid the occurrence of twisted wires. . The encapsulant 280 can be formed on the substrate 240 to seal the first wafer 220, the second wafer 230, the first bonding wires 250, and the second bonding wires 270. In addition, the solder balls 241 can be disposed on the lower surface of the substrate 240 such that the active surface-up stack configuration of the center pad type wafer can be externally connected.
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
110...基板110. . . Substrate
120...第一晶片120. . . First wafer
121...主動面121. . . Active surface
122...銲墊122. . . Solder pad
130...第一黏晶膠層130. . . First adhesive layer
140...長銲線140. . . Long wire
150...第二晶片150. . . Second chip
151...主動面151. . . Active surface
152...背面152. . . back
153...銲墊153. . . Solder pad
160...第二黏晶膠層160. . . Second sticky layer
210...複合式黏晶膠帶210. . . Composite adhesive tape
211...第一黏著層211. . . First adhesive layer
212...第二黏著層212. . . Second adhesive layer
220...第一晶片220. . . First wafer
221...背面221. . . back
222...中央銲墊222. . . Central pad
223...主動面223. . . Active surface
224...刀具224. . . Tool
230...第二晶片230. . . Second chip
231...主動面231. . . Active surface
232...中央銲墊232. . . Central pad
233...黏晶層233. . . Binder layer
240...基板240. . . Substrate
241...銲球241. . . Solder ball
250...第一銲線250. . . First wire bond
260...絕緣層260. . . Insulation
261...噴頭261. . . Nozzle
270...第二銲線270. . . Second wire
271...線固定件271. . . Wire fastener
280...封膠體280. . . Sealant
第1圖:為習知的一種中央銲墊型晶片之主動面朝上堆疊方法繪示在設置上層晶片時之截面示意圖。Fig. 1 is a schematic cross-sectional view showing a conventional in-plane stacking method for a conventional center-type wafer.
第2A至2K圖:依據本發明之一具體實施例的中央銲墊型晶片之主動面朝上堆疊方法在過程中之元件截面示意圖。2A to 2K are cross-sectional views showing the components in the process of the active face-up stacking method of the center pad type wafer according to an embodiment of the present invention.
第3圖:依據本發明之一具體實施例的中央銲墊型晶片之主動面朝上堆疊構造之截面示意圖。Figure 3 is a cross-sectional view showing the active face-up stacking configuration of a center pad type wafer in accordance with an embodiment of the present invention.
210...複合式黏晶膠帶210. . . Composite adhesive tape
211...第一黏著層211. . . First adhesive layer
212...第二黏著層212. . . Second adhesive layer
220...第一晶片220. . . First wafer
221...背面221. . . back
222...中央銲墊222. . . Central pad
223...主動面223. . . Active surface
230...第二晶片230. . . Second chip
231...主動面231. . . Active surface
232...中央銲墊232. . . Central pad
233...黏晶層233. . . Binder layer
240...基板240. . . Substrate
250...第一銲線250. . . First wire bond
260...絕緣層260. . . Insulation
Claims (14)
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TW200623291A (en) * | 2004-12-31 | 2006-07-01 | Chipmos Technologies Inc | Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips |
US20060226520A1 (en) * | 2005-03-28 | 2006-10-12 | Atsushi Yoshimura | Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component |
TW200921873A (en) * | 2007-11-09 | 2009-05-16 | Powertech Technology Inc | Chip-to-substrate interconnection device with wire-bonding |
TW200926389A (en) * | 2007-12-13 | 2009-06-16 | Powertech Technology Inc | Back-to-back stacked multi-chip package and method for fabricating the same |
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TW200623291A (en) * | 2004-12-31 | 2006-07-01 | Chipmos Technologies Inc | Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips |
US20060226520A1 (en) * | 2005-03-28 | 2006-10-12 | Atsushi Yoshimura | Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component |
TW200921873A (en) * | 2007-11-09 | 2009-05-16 | Powertech Technology Inc | Chip-to-substrate interconnection device with wire-bonding |
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