TW201114008A - Fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure - Google Patents

Abstract

Disclosed are a fabricating method of back-to-back chip assembly with flip-chip and wire-bonding connections and its structure. According to the fabricating method, a substrate is provided, and the upper surface of the substrate is covered by a solder mask having a guide slot to simultaneously exposure bump pads and wire-bonded fingers on the substrate. A lower chip is bonded on the substrate to connect with the bump pads. An upper chip is back-to-back stacked on the lower chip. A plurality of bonding wires are formed to electrically connect the upper chip with the fingers of the substrate. After wire-bonding, an underfill material is formed between the substrate and the lower chip to encapsulate the bumps of the lower chip and to fill in the guide slot to cover the fingers and partially encapsulate the bonding wires. Accordingly, there can be protected the solder joints on the substrate to avoid drop out, and further reduced the dimension of the package.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer semiconductor device, and more particularly to a back-to-back wafer combination method and structure for a flip chip bonding. [Prior Art] Multi-chip package (MCP) technology is widely used in the field of semiconductor packaging. Based on the practical needs of semiconductor packages, such as packaging multiple identical functional functional chips into a multi-chip with more memory capacity. The module, or a plurality of electronic functions and different chip packages are integrated into a system package (system & package) having a system operation function, and must be individually wired-bonding and flip chip depending on the type of the chip (flip_chip) ) to be packaged. At present, in the semiconductor industry, due to the better reliability and performance of flip chip (flip _chjp) technology, there is a trend to replace wire_b〇nding technology. However, because the wire bonding technology can achieve higher production, and even develop a wafer stacking technology in which the flip chip and the wire bonding technology coexist, the conventionally known flip chip plus wire wafer stacking technology has a process of flip chip bonding and filling. The glue is used to complete the placement of the lower wafer, and the wafer is attached and bonded. Therefore, the primer will retain a little glue width around the flip chip on the substrate, and the wire bonding pad is placed on the periphery of the substrate outside the dispensing width to avoid being covered by the primer, so that the package size cannot be reduced. The reduction in the rate further increases the manufacturing cost. Referring to FIG. 1 , a conventional flip-chip bonding back-to-back wafer assembly structure 100 mainly includes a substrate 11 , a lower wafer 201114008 wafer 120 , an upper wafer 130 , a plurality of bonding wires 140 , and a The underfill 150 and the adhesive 16 (the substrate 11 has a plurality of bump pads 1 Π and a plurality of wire bonding fingers 112, and a solder resist layer 113 is further disposed on the surface of the substrate no. The 120 series has a plurality of bumps 121, and the bumps 121 are flip-chip bonded to the bump pads 111. The upper wafers 130 are attached back-to-back to the back surface of the lower wafer j 2〇 and The bonding wires 140 are electrically connected to the bonding pads 13 of the upper wafer 13 to the bonding wires 112. The underfill 15 is disposed at the bottom of the lower wafer 120 to cover the bumps 121. Protecting the active surface of the lower wafer 120. The encapsulant 16 is used to seal the upper wafer 13A, the lower wafer 12G and the underfill film. More specifically, the flip chip bonding back-to-back wafer assembly structure 1 Back-to-back wafer combination in accordance with flip chip bonding as shown in Figure 2 The method comprises the following steps: a step of "providing a substrate", a step 12 of "flip-chip bonding of the lower wafer", a step 13 of "primer filling", and a step of "stacking the wafer on the back-to-back" 14. The step of "bonding the upper wafer" and the step 16 of "forming the encapsulant". In detail, the step u 疋 φ ζ is supplied to the substrate 110, and the lower wafer 12 is slid to the The substrate 110 is broadcasted, 舳, _ _ 仃 step 13, the underfill 150 is filled into the bottom of the lower wafer i 2 , to protect only the active surface of the lower wafer 1 20 and seal the convex surface 1〇1 21, but can not be covered in the T14 of the wire-to-wire =: T14, the upper wafer - to the next = line 2: on. After completing step 14, only use the - wire technology to stare at step 15 The fresh wire 140 is electrically connected to the upper wafer 130 201114008 and the substrate 110. Finally, step 16 is performed to form the encapsulant 160 on the substrate 11 to complete the packaging process. Therefore, the conventional implementation is performed first. The underfill is filled and then the upper die is connected by a wire, in order to make the wire bonding process Smoothly, the underfill 15 15 is not covered to the wire bonding fingers 11 2 when filling, so the substrate 11 must take into account the required dispensing width of the underfill 150. The iv 2 is disposed on the periphery of the substrate 110 outside the dispensing width, so that the package size cannot be reduced, which increases the overall manufacturing cost. The main purpose of the present invention is to provide a back-to-back connection of a flip chip connection. The wafer assembly method and structure can protect the wire bonding pads on the substrate to avoid falling off. The second object of the present invention is to provide a back-to-back wafer combination method and structure for flip chip bonding, and no padding is required around the substrate. The width of the glue formed by the glue, even if the wire is connected by the underfill, will not cause the wire to fail, and even more enhance the reliability and effectively reduce the package size. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a back-to-back wafer assembly method for flip chip bonding, which mainly comprises the following steps: providing a substrate having a plurality of bump pads and a plurality of wire bonding fingers on an upper surface thereof, and an anti-fresh layer covering the upper surface The solder resist layer has a flow guiding groove system and simultaneously exposes the bump pads and the wire bonding fingers. Flip chip bonding -= y 〇 underlying the substrate, the lower wafer has a plurality of bumps bonded to the bump bumps of the 201114008, electrically connecting the lower wafer and the substrate. Back-to-back stack m day μ the lower wafer' The upper wafer has a plurality of solder fillets. The wire is formed into a plurality of bonding wires, and the bonding pads are connected to the wires to electrically connect the upper wafer and the substrate. After the back-to-back stacking and wire-bonding (4) described above, a bottom-filled knee is formed between the substrate and the lower wafer, and the underfill seals the bumps and fills the guide P# groove to cover the wires. Fingers are placed and partially sealed. this

The invention further discloses a construction made in accordance with the above combined method. The object of the present invention and its technical problems can be further realized by adopting technical measures. In the back-to-back wafer assembly method just described, after the underfill is formed, the winter+ can be further included, the step of forming is to form a gel on the substrate to seal the upper crystal, the #π片. The wafer is filled with the underfill. In the foregoing anticline ciiia, Λ月的牙阳片组合方法, the diversion slotting system can be

A continuous or discontinuous I, <&&' is such that the solder resist layer is formed as a solder resist island below the lower wafer. In the aforementioned Zhe #4·3b. In the π-Yan-Yan wafer combination method, the outer edge of the flow-guiding groove may be a mineral tooth-like shape to expose the wire-bonding fingers. In the foregoing, thank you db.

In the π-pair odd-wafer combination method, the flow-guiding grooving system can have a plurality of slots, and each of the s-holes reveals at least one bump pad and at least one adjacent wire-bonding finger. In the above-mentioned back-to-back-welded metal foil wafer bonding method, the bumps may be non-' and the bumps are soldered to the bump pads. 201114008 n #胃上技术方案 It can be seen that the method and structure of the flip chip bonding method of the present invention have the following advantages and effects: β, by first bonding a wire bonding wire to form an underfill glue on the substrate and the underlying crystal As one of the technical means, since the underfill is dense: the bump is filled in the diversion groove to cover the wire bonding finger and partially 'and the sealing wire, the wire bonding point on the substrate can be protected to avoid Fall off. By using a wire bonding wire to form an underfill between the substrate and the lower wafer as a technical means, it is necessary to avoid the problem of the width of the underfill rubber. It is necessary to worry that the wire bonding finger will be covered by the underfill rubber. It is impossible to wire, so it can effectively reduce the package size. Second, the guide layer of the solder resist layer and the anti-welding island block can be used as one of the technical means, since the flow guiding groove is continuous or discontinuous, so that the solder resist layer becomes a square under the lower wafer. The solder mask is advantageous for guiding the flow of the underfill on the periphery of the lower wafer. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in Figure t are not drawn in proportion to the number, shape and size of the actual implementation. Some ratios of scales are exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, a back-to-back sheet roughing method for a flip chip connection is illustrated by a flow block diagram of FIG. 3 and a fourth and fourth G map opening and γ — * < schematic diagram. The flip-chip bonding is back-to-back, and the σ method according to FIG. 3 mainly includes the following steps: step 21 of “providing the substrate”, step 22 of “flip-chip bonding of the lower wafer”, and “back-to-back stacking of the wafer” , $ half _ Γ , ” step 23, “on the wafer connection”

Step 24, Step 25 of "Bottom Filling r ^ X for Brother" and "Forming Sealant"

Procedure Refer to Figures 4A through 4 for the components to be represented at each step, as shown below. First, go to step 21. Referring to FIG. 4, a substrate 21 is provided. The upper surface φ 211 is provided with a plurality of bump pads and a plurality of wire fingers 2 1 3, and is numb with a ρ big name θ, β» — ^ Μ Zinc-proof layer 214 covers the upper surface 211, the solder resist layer 2 14 has a right-track ancient day μ, and a diversion slot 2 1 5, which simultaneously exposes the bump blocks 212 and the difference Souling skills, λ., , j, —α deep contact 213. In this embodiment, the flow guiding slot 215 can be a reciprocating or non-continuous ring of the far wall, the U.S. and the second, so that the solder resist layer 214 is squared under the lower wafer 22〇. The island block 21 6 (as shown in Fig. 6) maintains the gap between the flip chip and the substrate 21G. Therefore, in the subsequent filling process, the flow guiding groove 215 can guide the flow of the underfill on the periphery of the lower wafer 220 and restrict its outward diffusion. In the preferred embodiment, the solder resist layer 214 can partially cover the side of the wire bonding S 213. The "side" refers to the wire finger 213 away from the adjacent bump pad 212. One side. Go to Step 22. First, as in the 220th. Referring to FIG. 4C, as shown in FIG. 4B, the wafer is flip-chip bonded to the lower wafer 220 to 201114008. The lower wafer 220 has a plurality of bumps 221 bonded to the bumps. The pad 212 is electrically connected to the lower wafer 22 and the substrate 210. In the embodiment, the bumps 221 can be non-reflowed metal pillars, for example, gold pillars capable of withstanding high temperature and deformation. A copper post or the like is used to solve the problem of bridging short circuit in which the conventional bump is deformed by reflow and can maintain a fixed underfill gap after stacking and wire-bonding back-to-back. Specifically, the bumps 22 of the lower wafer 220 are connected to the bumps 212 of the substrate 21 by a recording material 270. In a preferred embodiment, as shown in FIG. 4, the bumps 22 of the lower wafer 22 may be attached to the solder 270' and then directly aligned to the substrate 21A. Go to Step 23. Referring to FIG. 4D, an upper wafer 230 is stacked back to back to the lower wafer 220. The upper wafer 23 has a plurality of pads 23 1 » In the embodiment, the size of the upper wafer 23 is not greater than The lower wafer 220 is sized and attached to the back side of the lower wafer 22 by a die attach layer 232. Specifically, the die layer 232 may not completely cover the back surface of the lower wafer 22 . In a preferred embodiment, the die layer 232 is formed on the back side of the upper wafer 230 or the back side of the lower wafer 22 in accordance with process requirements. Go to Step 24. Referring to FIG. 4, before the primer is filled, a plurality of bonding wires 240 are formed, and the bonding pads 231 and the bonding wires 213 are connected to electrically connect the upper wafer 23 and the substrate. 210. In a preferred embodiment, the bumps 221 can be #回焊合合金属柱, with a uniform flip-chip height and sufficient wire bonding 201114008, the building capacity can be in the absence of underfill , the upper wafer 2 3 〇 is wired. Go to Step 25. Referring to FIG. 4F, after the back-to-back «stacking and wire bonding steps described above, an underfill 25 is formed between the substrate 210 and the lower wafer 220. The underfill 250 seals the bumps 221 And filling the guiding groove 215 to cover the wire bonding fingers 213 and partially sealing the bonding wires 240. Preferably, since the flow guiding groove 215 can guide the underfill 250 to flow around the lower wafer _ 220, the underfill rubber 250 can be prevented from overflowing to other places and cause pollution. Finally, please refer to As shown in FIG. 4G, after the underfill 250 is formed, a gel 260 may be formed on the substrate 210 to seal the upper wafer 230, the lower wafer 220, and the underfill 250. In addition, the encapsulant 260 also covers the bonding wires 240 to further reinforce the bonding force of the bonding wires 240. The encapsulant 260 can be formed by a molding process. In the present invention, since the underfill 250 is filled into the flow guiding groove 215 after the bonding wires 240 are formed, the underfill 250 is filled in the lower wafer 220 to seal the holes. The bumps 221 and the bump pads 212 can cover the wire bonding fingers 213 and partially cover the wire bonding wires 24 by the guiding grooves 215. Therefore, by soldering and fixing the bonding wires 240 by the underfill 25 0, the solder joints of the bonding wires 240 can be protected to prevent the solder wires 240 from falling off from the soldering sites in a subsequent process. In addition, since the present invention completes the wire bonding step of the upper wafer 230 first, and then fills the underfill rubber 250, 10 201114008, it is possible to eliminate the need to reserve a glue width space for forming the underfill rubber 250 around the substrate. The structure in which the wire bonding #213 is covered by the underfill 250 does not have the problem of wire failure, and the reliability is reduced and the package size is effectively reduced. The present invention also discloses a back-to-back wafer assembly structure 2, which is formed by the above-described combination method, and is illustrated in Fig. 5. The flip chip bonded back-to-back wafer assembly structure mainly includes a substrate 210, a lower wafer 220, an upper wafer 230, a plurality of bonding wires 24A, and an underfill rubber 250. The upper surface 211 of the substrate 21 is provided with a plurality of bump pads 212 and a plurality of wire bonding fingers 213, and the upper surface 211 is covered by a anti-welding layer 214. The solder resist layer 214 has a flow guiding slot. 215, the bump pads 212 and the wire bonding fingers 213 are simultaneously exposed. In one embodiment, the flow guiding slot 215 can be a continuous or discontinuous ring. As shown in FIG. 6, the flow guiding groove 2丨5 is a discontinuous ring shape, so that the solder resist layer 214 is squared under the lower wafer 220 to form a solder resist island 216, which is advantageous for guiding. The underfill 25 流动 flows around the lower wafer 220 and does not easily spill over to other places to cause contamination. Moreover, the solder resist island 216 can be integrally joined by the solder resist layer 214 at non-continuous corners to avoid detachment. The lower wafer 220 is flip-chip bonded to the substrate 21A. The lower wafer 220 has a plurality of bumps 221 bonded to the bump pads 212 to electrically connect the lower wafer 220 and the substrate 21. . Specifically, the bumps 221 may be non-reflowed metal posts, and the bumps 22 i and the bump pads 212 are connected by solder. Further, 201114008, the upper wafer 230 is stacked back to back to the lower wafer 220. The upper wafer 230 has a plurality of pads 231. The bonding wires 240 are connected to the pads 231 and the bonding fingers 213. The upper wafer 230 and the substrate 210 are electrically connected. The underfill adhesive 25 is formed between the substrate 210 and the lower wafer 220. The underfill adhesive 250 seals the bumps 221 and fills the guiding slits 215 to cover the wire bonding fingers. 213 and partially seal the bonding wires 240. In addition, a glue 260 may be further formed on the substrate 210 to seal the upper wafer 230, the lower wafer 220 and the underfill 250. In a variant embodiment, as shown in FIG. 7, the outer edge 217 of the flow guiding slot 21 5 can be serrated to reveal the wire bonding fingers 213. In detail, the wire bonding fingers 213 can be disposed in the outer edge 217 of the flow guiding groove 2丄5. After the underfill 250 is filled, it naturally flows into the inside of the flow guiding groove 2 15 and fills the bottom of the lower wafer 220. Since the guide groove 2丨5 is serrated, a large adhesion can be generated between the underfill and the underfill 250, and the adhesive diffusion area of the underfill 250 is reduced, so that the bottom can be effectively prevented. Filler 250 produces spillage and contamination. In another variant embodiment, as shown in FIG. 8, the flow guiding slot 2 15 can be a plurality of slots 2 15 A , and each slot 21 5A exposes at least one bump pad 212 and at least A nearby wire is connected to 2 1 3 . The above description is only a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the invention has been disclosed above in the preferred embodiment 12 201114008, it is not intended to limit the invention, Any simple modifications, equivalent changes and modifications made by the skilled artisan will remain within the scope of the invention. [Simplified description of the drawings] Fig. 1 is a schematic view showing the wearable structure of a back-to-back wafer assembly structure of a conventional flip chip connection. Figure 2 is a flow block diagram of a conventional back-to-back wafer assembly method for flip chip bonding. Figure 3 is a block diagram showing the flow of a flip chip bonding method in accordance with an embodiment of the present invention. 4A to 4D are schematic cross-sectional views of elements in the process in accordance with an embodiment of the present invention. Fig. 5 is a schematic cross-sectional view showing a combined structure of a flip chip bonding according to a specific embodiment of the present invention. 6 is a diagram showing a back-to-back wafer assembly structure of a flip chip connection according to an embodiment of the present invention, showing a substrate and a solder resist layer thereon, and a flip chip according to a modified embodiment of the present invention. The back-and-back wafer combination structure of the wire connection shows the substrate and the anti-view view. FIG. 8 is a view showing the substrate and the flip-chip bonding structure according to another embodiment of the present invention. The anti-fresh layer 4 is on the map. 13 201114008 [Description of main component symbols]

Step 11: Providing a flip chip bonding step of the wafer in step 12 of the substrate. Primer filling step 14 Wafer winding on the back-to-back stack 1 5 Wire bonding connection of the upper wafer Step 16 Forming the encapsulant Step 21 Providing the flip chip bonding step of the wafer in the step 22 of the substrate 23 Back-to-back stacking of wafers Step 24 Upper wafer bonding connection step 25 Primer filling step 26 Forming the encapsulant 100 flip-chip bonding back-to-back wafer assembly structure 110 substrate 111 bump pads 112 120 lower wafer 130 upper wafer 140 bonding wires 150 bottom 200 flip-chip connection back pair 210 substrate 211 on 213 wire connection finger 214 anti-215A slot 216 anti-220 lower wafer 221 convex

Wire finger 113 solder mask 121 bump 131 pad pad filler 160 seal back wafer combination structure surface 212 bump pad solder layer 2 1 5 flow guiding slot fresh island block 14 201114008 230 wafer 240 wire bonding 260 seal 231 pad 232 adhesive layer 2 5 0 underfill 270 solder

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Claims (1)

201114008 VII. Patent application scope: 1. A back-to-back wafer combination method for flip chip bonding, comprising: • providing a substrate having a plurality of bump pads and a plurality of wire bonding fingers on the upper surface thereof, and an anti-welding a layer covering the upper surface, the solder resist layer having a flow guiding groove, simultaneously exposing the bump pads and the wire bonding fingers; and flip chip bonding the wafer to the substrate, the lower wafer system having a plurality of a bump is bonded to the bump pads to electrically connect the lower wafer and the substrate; and an upper wafer is stacked back to back to the lower crystal, the upper wafer has a plurality of pads; the wire is formed into a plurality of wires a bonding wire connecting the bonding pads and the bonding wires to electrically connect the upper wafer and the substrate; and after the back-to-back stacking and wire bonding steps, forming an underfill on the substrate and the lower wafer Between the underfills, the bumps are sealed and filled into the flow guiding slots to cover the wire bonding fingers and partially seal the wire bonds. 2. The back-to-back wafer assembly method according to the patent application scope 帛i, after the underfill is formed, the method further comprises: forming a gel on the substrate to seal the upper wafer, Lower the wafer with the underfill. 3. The back-to-back wafer assembly method of flip chip bonding according to claim 1, wherein the flow guiding groove is continuous or discontinuous annular shape such that the P square solder layer is squared under the lower wafer. A 16 201114008 anti-fresh island block. 4. The back-to-back wafer assembly method of the flip-chip bonding according to item 3 of the patent application scope, wherein the outer edge of the current guiding slot is serrated to expose the wire bonding fingers. 5. The back-to-back wafer assembly method of the flip chip bonding according to the scope of the patent application, wherein the flow guiding slot is a plurality of slots, each slot revealing at least one bump pad and at least one adjacent wire bond. Refers to. The method of back-to-back wafer bonding according to the flip-chip bonding of the first application of the patent application, wherein the bumps are non-reflowed metal pillars, and the bumps are between the bump pads and the bump pads Connected with solder. A back-to-back wafer assembly structure comprising a flip chip connection comprising: a substrate having a plurality of bump pads and a plurality of wire bonding fingers on an upper surface thereof, and covering the upper surface with a solder resist layer, the solder resist The layer spring has a flow guiding slot, and simultaneously exposes the bump pads and the wire bonding fingers; the lower wafer is flip-chip bonded to the substrate, and the lower wafer has a plurality of bumps, which are bonded to The bump pads are electrically connected to the lower wafer and the substrate; an upper wafer is stacked back to back to the lower wafer, the upper wafer has a plurality of pads; the plurality of bonding wires formed by the wires are connected The pads are electrically connected to the upper wafer and the substrate; and 17 201 ll 4 〇〇 8 an underfill is formed between the substrate and the lower wafer, the underfill system The bumps are sealed and filled into the flow guiding slots to cover the wire bonding fingers and partially seal the wire bonds. 8. The back-to-back wafer assembly of flip chip bonding according to claim 7 of the patent application, further comprising a gel formed on the substrate to seal the upper wafer, the lower wafer and the underfill. 9. The back-to-back wafer assembly structure of the flip chip connection according to claim 7 of the patent application scope, wherein the flow guiding groove is a continuous or discontinuous ring, such that the solder resist layer forms under the lower wafer. It is an anti-welding island block. 10. The back-to-back wafer assembly structure of the flip chip connection according to the ninth application of the patent application scope wherein the outer edge of the flow guiding groove is in a dentate shape to expose the wire bonding fingers. 11. The back-to-back wafer assembly structure of the flip chip connection according to claim 7 of the patent application scope, wherein the flow guiding slot is a plurality of slots, each of the slots revealing at least one bump pad and at least one adjacent one. Wire-to-wire® 12, a back-to-back wafer twisting structure according to the flip-chip connection of claim 7 wherein the bumps are non-reflowed metal posts, and the bumps and the bumps The pads are connected by fresh materials. 18