CN101656246A - Chip stacking packaging structure of substrate with opening and packaging method thereof - Google Patents

Abstract

The invention is a chip stacking structure, comprising: a substrate having a front surface and a back surface, respectively provided with a circuit layout and having an opening penetrating through the substrate; the first chip is provided with an active surface and a back surface, wherein the active surface of the first chip faces downwards, part of the back surface of the first chip is attached to the back surface of the substrate through the first adhesion layer, and part of the back surface of the first chip which is not covered by the first adhesion layer is exposed; the second chip is provided with an active surface and a back surface, wherein the active surface of the second chip faces upwards, and the back surface of the second chip is fixed on the back surface of the first chip through a second adhesion layer; the first lead is electrically connected with the active surface of the first chip and the back surface of the substrate; the second lead is electrically connected with the active surface of the second chip and the front surface of the substrate; the first packaging body wraps the first chip, the first adhesion layer, the first lead and the back surface of the substrate; the second packaging body wraps the second chip, the second adhesion layer, the second lead, part of the back surface of the first chip and part of the front surface of the substrate; and a conductive element disposed on the front surface of the substrate.

Description

Chip stack packaging structure with substrate with opening and packaging method thereof

technical field

The present invention relates to a package structure and method thereof, in particular to a chip stack package structure with an opening substrate and a package method thereof.

Background technique

The semiconductor packaging structure with an open substrate is a more advanced packaging technology, which is characterized by: at least one opening is formed on the substrate, and allows the chip to be placed and cover the through hole of the substrate, and pass through the through hole. The wires bonded by wires are electrically connected to the substrate. Such an arrangement can effectively shorten the length of wires for wire bonding, thereby forming an electrical connection between the substrate and the chip. A conventional packaging structure of a substrate with openings is shown in FIG. 1 , wherein a substrate 100 has an upper surface and a lower surface and an opening 102 runs through the substrate 100 . Next, a chip 120 is exposed to the opening 102 of the substrate 100 with the active surface (not shown in the figure) facing down and the pads 122 on the active surface are exposed. Then, a plurality of wires 130 are connected to the bonding pads 122 of the chip 120 exposed in the opening 102 through the opening 102 of the substrate 100 by bonding wires, thereby electrically connecting the lower surface of the substrate 100 and the chip 120. active side. Next, a package body 140 is formed on the lower surface of the substrate 100 by printing to cover the wire 130 and seal the opening 102 of the substrate 100 .

However, due to the mismatch of the coefficient of thermal expansion (CTE, coefficient of thermal expansion) between the package body (especially the package body formed by the resin material) 140 and the chip 120 contacting the package body 140, under the condition of high temperature , such as the curing (curing) step of the package body 140 or the subsequent thermal cycle step, especially in the part of the chip 120 due to the thermal stress (thermal stress) from the package body 140, chip cracking (chip-crack) will occur problems, and compared to longer and larger-sized chips, their reliability and yield will be reduced. In addition, during the forming process of the package body 140 , the wires of the wire bonding thereof will contact with the resin material to form the package body by molding, so that there will be a problem of short circuit.

Contents of the invention

In view of the above problems, the main purpose of the present invention is to provide a substrate with openings for chip stacking, thereby reducing the packaging thickness of the entire chip stacking structure.

According to the above purpose, the present invention discloses a chip stacking structure, comprising: a substrate having a front surface and a back surface respectively configured with a circuit layout and having an opening penetrating the substrate; a first chip having an active surface and a back surface , wherein the active surface of the first chip faces downward, and a part of the back surface of the first chip is attached to the back surface of the substrate through a first adhesive layer, and the part of the first chip not covered by the first adhesive layer is exposed. a second chip with an active surface and a back surface, wherein the active surface of the second chip faces upwards, and the back surface of the second chip is fixed on the back surface of the first chip through a second adhesive layer; multiple strips A wire is used to electrically connect the active surface of the first chip and the back surface of the substrate; multiple second wires are used to electrically connect the active surface of the second chip and the front surface of the substrate; the first package is used to cover the The first chip, the first adhesive layer, multiple first wires, and the back surface of the substrate; a second package, used to cover the second chip, the second adhesive layer, multiple second wires, and part of the first chip a back side and a portion of the front side of the substrate; and a plurality of conductive elements disposed on the front side of the substrate.

The present invention also discloses another chip stacking structure, comprising: a substrate having a front surface and a back surface respectively configured with a circuit layout and having an opening penetrating the substrate; a first chip having an active surface and a back surface, wherein the first The active surface of the chip faces downward, and the back surface of the first chip is attached to a part of the back surface of the substrate through an adhesive layer, and the adhesive layer covers a surface of the opening; a second chip has an active surface and a surface, Wherein the active surface of the second chip faces upward, and the back of the second chip is fixed on the back of the first chip through an adhesive layer; a plurality of first wires are used to electrically connect the active surface of the first chip and the back of the substrate; A plurality of second wires are used to electrically connect the active surface of the second chip and the front surface of the substrate; the first package is used to cover the first chip, the adhesive layer, a plurality of first wires and the back surface of the substrate; the second The packaging body is used to cover the second chip, part of the adhesive layer, a plurality of second wires and part of the front surface of the substrate; a plurality of conductive elements are arranged on the front surface of the substrate.

According to the above-mentioned chip stack structure, the present invention discloses a method for forming a chip stack structure, comprising: providing a substrate with a front surface and a back surface, respectively configured with a circuit layout, and having an opening penetrating through the front surface and the back surface of the substrate; Attaching the first chip on a part of the back of the substrate is to place the active surface of the first chip downward, and the back of the first chip is pasted on the part of the back of the substrate through a first adhesive layer and exposes the first chip in the opening. The back side of the first chip not covered by the first adhesive layer of the chip; attaching the second chip on the back side of the first chip is to make the active side of the second chip face up, and a back side of the second chip passes through a The second adhesive layer is attached on the back surface of the first chip not covered by the first adhesive layer; a plurality of first wires are formed to electrically connect the active surface of the first chip and the back surface of the substrate; a plurality of second wires are formed The wire is used to electrically connect the active surface of the second chip and the front surface of the substrate; a first package is formed to cover the first chip, the first adhesive layer, a plurality of first wires and the back surface of the substrate; a first package is formed The second package is used to cover the second chip, the second adhesive layer, part of the back of the first chip, a plurality of second wires and part of the front of the substrate; and form a plurality of conductive elements, which are formed on the front of the substrate superior.

The present invention further discloses a method for forming a chip stack, comprising: providing a substrate having a front surface and a back surface respectively configured with a circuit layout, and having an opening penetrating through the front surface and the back surface of the substrate; attaching a first chip on the On part of the back of the substrate, the active surface of the first chip is facing downward, and a back of the first chip is attached to the back of the substrate through an adhesive layer; a second chip is attached to the back of the first chip, An active surface of the second chip faces upward and a back surface of the second chip is fixed on the back surface of the first chip through an adhesive layer; a plurality of first wires are formed to electrically connect the active surface of the first chip and the substrate form a plurality of second wires to electrically connect the active surface of the second chip and the front side of the substrate; form a first package to cover the first chip, the adhesive layer, a plurality of first wires and the back side of the substrate ; forming a second package to cover the second chip, the adhesive layer, a part of the back of the first chip, a plurality of second wires and a part of the front of the substrate; and forming a plurality of conductive elements, which is a plurality of conductive elements formed on the front side of the substrate.

Description of drawings

For a clearer understanding of the purpose, structure, features, and functions of the present invention, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram showing a package structure of a substrate having openings according to the prior art;

2A to 2F are schematic diagrams showing various steps of forming a chip stack package structure with a substrate having an opening according to the technology of the present invention; and

3A to 3F are schematic diagrams illustrating various steps of forming a chip stack package structure on a substrate with openings according to another embodiment of the present invention.

Detailed ways

The direction that the present invention discusses here is a packaging structure and its packaging method, which is to provide a substrate with an opening so that chips of different sizes can be flip-chip attached to the substrate facing the opening, and then the chips are stacked. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Clearly, the practice of the invention is not limited to specific details of the manner in which chips are packaged that are familiar to those skilled in the art. For the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, but in the following The scope defined by the appended claims of this application shall prevail.

2A to 2B are schematic diagrams showing various steps of forming a chip stack package structure with a substrate having openings. First, with reference to FIG. 2A , a substrate 10 is first provided, which has a front and a back, and a circuit layout (layout) (not shown in the figure) is respectively arranged on the front and the back, here, on the front and the back of the substrate 10 The back side can be configured with the same or different circuit layouts. In this embodiment, it is used to stack chips of different sizes and functions as its main technical feature of the invention. Therefore, it is made of substrates 10 with different circuit layouts. An illustration of an example. However, it should be noted that the formation and structure of the circuit layout of the substrate 10 are not the technical features of the present invention, and only the application of the substrate with the circuit layout is used as an example of the present invention, so further description is omitted.

Next, a patterned photoresist layer (not shown) is formed on the substrate 10 by using a semiconductor process; then developing and etching are performed to remove part of the substrate and form an opening 12 through the substrate. The front and back of the substrate 10. Here, the material of the substrate 10 may be a single-layer or multi-layer circuit board or metal foil.

Next, FIG. 2B is a schematic diagram illustrating attaching a first chip on the back surface of the substrate. In FIG. 2B , the first chip 30 is firstly provided, which has an active surface and a back surface, and has a plurality of bonding pads 32 on the active surface. Next, the active surface of the first chip 30 is facing down, and the back surface of the first chip 30 is aligned with the opening 12 of the substrate 10 through the first adhesive layer 20, and part of the back surface of the first chip 30 is fixed on the substrate 10. on the back side, and part of the back side of the first chip 30 is exposed through the opening 12 of the substrate 10 . In this embodiment, the first adhesive layer 20 may be a two-stage thermosetting adhesive (B-stage).

Next, please refer to FIG. 2C , which is a schematic diagram of stacking the second chip on the first chip. In FIG. 2C , a second chip 50 is provided, which has an active surface and a back surface, and has a plurality of bonding pads 52 on the active surface. Next, the active surface of the second chip 50 faces upward, and the back side of the second chip 50 is attached to the back side of the first chip 30 exposed to the opening 12 of the substrate 10 through a second adhesive layer 40 to form a chip stack. structure. In this embodiment, the second adhesive layer may be die attach film or epoxy. In addition, in this embodiment, the first chip 30 and the second chip 50 are chips with different functions, thereby increasing the application range of the chip stack package structure.

Next, please refer to FIG. 2D , which is a schematic diagram illustrating electrically connecting the first chip and the second chip to the substrate respectively. In FIG. 2D , the first chip 30 and the second chip 50 attached to the substrate 10 are first turned upside down, so that the active surface of the first chip 30 faces upward and the active surface of the second chip 50 faces downward. Then, using a bonding wire method, the two ends of the plurality of first wires 60 are respectively formed on the plurality of solder pads 32 on the active surface of the first chip 30 and the back surface of the substrate 10, and on the substrate A circuit layout is arranged on the back surface of 10 , therefore, the first chip 30 and the substrate 10 can be electrically connected by using a plurality of first wires 60 . Then, the first chip 30 and the second chip 50 are turned upside down, so that the active surface of the first chip 30 faces downward and the active surface of the second chip 50 faces upward. Similarly, two ends of the plurality of second wires 70 are respectively formed on the plurality of solder pads 52 on the active surface of the second chip 50 and the front surface of the substrate 10 by wire bonding. Since a circuit layout is also configured on the front surface of the substrate 10 , the plurality of second wires 70 can be electrically connected to the second chip 50 and the substrate 10 . In addition, it should be noted that, in the embodiment of the present invention, a plurality of second wires 70 may be formed on the second chip 50 first, and then the second chip 50 and the first chip 30 are turned upside down, and then the first A plurality of first wires 60 are formed on the chip 30 .

Next, refer to FIG. 2E , which is a schematic diagram showing the formation of the package on the substrate. In FIG. 2E , first, a polymer material (not shown in the figure) is injected into the periphery of the second chip 50 and the opening 12 of the substrate 10 . Then, a baking process (bake process) is performed on the polymer material, so that the polymer material is cured to form a package 80A to cover the second chip 50, the second adhesive layer 40, the plurality of first wires 60 and Covering the opening 12 of the substrate 10 and part of the front surface of the substrate 10 . Then, the first chip 30 and the second chip 50 are turned upside down so that the active surface of the first chip 30 faces upward. Similarly, another polymer material is injected around the first chip 30 . Next, a baking procedure is performed on the polymer material to soften the polymer material to form another package body 80B to cover the first chip 30 , the plurality of first wires 60 and the back surface of the substrate 10 . In this embodiment, the polymer material may be materials such as silica gel, epoxy resin, acrylic, and benzocyclobutene (BCB).

Next, refer to FIG. 2F , which is a schematic diagram illustrating forming a plurality of conductive elements on the front surface of the substrate. In FIG. 2F , the front surface of the substrate 10 is arranged in an array to form a plurality of conductive elements 90 , such as metal bumps or solder balls, to complete the package structure of chip stacking.

In addition, FIG. 3A to FIG. 3F show another embodiment of the chip stack packaging structure of the present invention. In FIG. 3A, a substrate 10 is first provided, which has a front and a back, and a circuit layout (layout) (not shown in the figure) is respectively provided on the front and the back. Here, the front and the back of the substrate 10 The same or different circuit layouts can be configured on the back, and in this embodiment, it is used to stack chips of different sizes and functions as its main technical feature of the invention. Therefore, the substrate 10 with different circuit layouts is used as the Description of Examples. However, it should be noted that the formation and structure of the circuit layout of the substrate 10 are not the technical features of the present invention, and only the application of the substrate with the circuit layout is used as an example of the present invention, so further description is omitted.

Next, a patterned photoresist layer (not shown) is formed on the substrate 10 by using a semiconductor process; then developing and etching are performed to remove part of the substrate and form an opening 12 through the substrate. The front and back of the substrate 10. Here, the material of the substrate 10 may be a single-layer or multi-layer circuit board or metal foil.

Next, FIG. 3B is a schematic diagram illustrating attaching a first chip on the back surface of the substrate. In FIG. 3B , the first chip 30 is firstly provided, which has an active surface and a back surface, and has a plurality of bonding pads 32 on the active surface. Next, the active surface of the first chip 30 is facing downward, and the back of the first chip 30 is aligned with the opening 12 of the substrate 10 through the adhesive layer 20B, and part of the back of the first chip 30 is fixed on the part of the substrate 10 and cover the opening 12 of the substrate 10 to expose the adhesive layer 20B. In this embodiment, the adhesive layer 20B may be die attach film (DAF; die attach film) or epoxy.

Next, please refer to FIG. 3C , which is a schematic diagram of stacking the second chip on the first chip. In FIG. 3C , a second chip 50 is provided, which has an active surface and a back surface, and has a plurality of bonding pads 52 on the active surface. Next, the active surface of the second chip 50 faces upward, and the back surface of the second chip 50 is fixed on the back surface of the first chip 30 through the adhesive layer 20B to form a chip stack structure. In this embodiment, the first chip 30 and the second chip 50 are chips with different functions, thereby increasing the application range of the chip stack package structure.

Next, please refer to FIG. 3D , which is a schematic diagram illustrating electrically connecting the first chip and the second chip to the substrate respectively. In FIG. 3D , the first chip 30 and the second chip 50 attached to the substrate 10 are turned upside down first, so that the active surface of the first chip 30 faces upward and the active surface of the second chip 50 faces downward. Then, using a bonding wire method, the two ends of the plurality of first wires 60 are respectively formed on the plurality of solder pads 32 on the active surface of the first chip 30 and the back surface of the substrate 10, and on the substrate A circuit layout is arranged on the back surface of 10 , therefore, the first chip 30 and the substrate 10 can be electrically connected by using a plurality of first wires 60 . Then, the first chip 30 and the second chip 50 are turned upside down, so that the active surface of the first chip 30 faces downward and the active surface of the second chip 50 faces upward. Similarly, two ends of the plurality of second wires 70 are respectively formed on the plurality of solder pads 52 on the active surface of the second chip 50 and the front surface of the substrate 10 by wire bonding. Since a circuit layout is also configured on the front surface of the substrate 10 , the plurality of second wires 70 can be electrically connected to the second chip 50 and the substrate 10 . In addition, it should be noted that, in the embodiment of the present invention, a plurality of second wires 70 may be formed on the second chip 50 first, and then the second chip 50 and the first chip 30 are turned upside down, and then the first A plurality of first wires 60 are formed on the chip 30 .

Next, refer to FIG. 3E , which is a schematic diagram showing the formation of the package on the substrate. In FIG. 3E , first, a polymer material (not shown in the figure) is injected into the periphery of the second chip 50 and the opening 12 of the substrate 10 . Then, a baking process (bake process) is performed on the polymer material, so that the polymer material is solidified to form a package body 80A to cover the second chip 50, the adhesive layer 20B exposed to the opening 12, and a plurality of first strips. The conductive wire 60 covers the opening 12 of the substrate 10 and part of the front surface of the substrate 10 . Then, the first chip 30 and the second chip 50 are turned upside down so that the active surface of the first chip 30 faces upward. Similarly, another polymer material is injected around the first chip 30 . Next, a baking process is performed on the polymer material, so that the polymer material is melted to form another package body 80B to cover the first chip 30, part of the adhesive layer 20B, the plurality of first wires 60 and the substrate 10 The back. In this embodiment, the polymer material may be materials such as silica gel, epoxy resin, acrylic, and benzocyclobutene (BCB).

Next, refer to FIG. 3F , which is a schematic view showing forming a plurality of conductive elements on the front surface of the substrate. In FIG. 3F , the front surface of the substrate 10 is arranged in an array to form a plurality of conductive elements 90 , such as metal bumps or solder balls, to complete the package structure of stacked chips.

Although the present invention is disclosed above with the aforementioned preferred embodiments, it is not intended to limit the present invention. Any skilled person who is familiar with this technology can make various equivalent changes or substitutions without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention must be defined by the scope of the claims of the application attached to this specification.

Claims (10)

1. A chip stack structure, comprising: A substrate having a front surface and a back surface respectively configured with a circuit layout and having an opening penetrating the substrate; A first chip has an active surface and a back surface, wherein the active surface of the first chip faces downward, and a part of the back surface of the first chip is attached to the back surface of the substrate through a first adhesive layer and expose the back side of the part of the first chip that is not covered by the first adhesive layer; A second chip has an active surface and a back surface, wherein the active surface of the second chip faces upward, and the back surface of the second chip is fixed on the back surface of the first chip by a second adhesive layer ; A plurality of first wires are used to electrically connect the active surface of the first chip and the back surface of the substrate; a plurality of second wires for electrically connecting the active surface of the second chip and the front surface of the substrate; a first package, used to cover the first chip, the first adhesive layer, the first wires and the back surface of the substrate; a second package, used to cover the second chip, the second adhesive layer, the second wires, part of the back side of the first chip and part of the front side of the substrate; and A plurality of conductive elements are arranged on the front surface of the substrate. 2. The chip stacking structure according to claim 1, wherein the first adhesive layer is a two-stage thermosetting adhesive. 3. The chip stack structure according to claim 1, wherein the second adhesive layer is epoxy resin or die adhesive film. 4. A chip stack structure, comprising: A substrate having a front surface and a back surface respectively configured with a circuit layout and having an opening penetrating the substrate; A first chip has an active surface and a back surface, wherein the active surface of the first chip faces downward, and the back surface of the first chip is attached to a part of the back surface of the substrate through an adhesive layer and the the adhesive layer covers a surface of the opening; A second chip having an active surface and a back surface, wherein the active surface of the second chip faces upward, and the back surface of the second chip is fixed on the back surface of the first chip through the adhesive layer; A plurality of first wires are used to electrically connect the active surface of the first chip and the back surface of the substrate; a plurality of second wires for electrically connecting the active surface of the second chip and the front surface of the substrate; a first package, used to cover the first chip, the adhesive layer, the first wires and the back surface of the substrate; a second package, used to cover the second chip, part of the adhesive layer, the second wires and part of the front surface of the substrate; and A plurality of conductive elements are arranged on the front surface of the substrate. 5. The chip stack structure according to claim 4, wherein the adhesive layer is epoxy resin or a chip adhesive layer. 6. A method of forming a chip stack structure, comprising: providing a substrate having a front side and a back side configured with a circuit layout respectively, and having an opening penetrating through the front side and the back side of the substrate; Affixing a first chip on the back surface of the part of the substrate means that an active surface of the first chip faces downward, and a back surface of the first chip is attached to the part of the substrate through a first adhesive layer the back surface of the first chip not covered by the first adhesive layer is exposed on the back surface through the opening; Attaching a second chip on the back surface of the first chip is to face an active surface of the second chip upward, and a back surface of the second chip is attached to the surface not covered by the first chip through a second adhesive layer. on the back side of the first chip covered by an adhesive layer; forming a plurality of first wires to electrically connect the active surface of the first chip and the back surface of the substrate; forming a plurality of second wires to electrically connect the active surface of the second chip and the front surface of the substrate; forming a first package for covering the first chip, the first adhesive layer, the first wires and the back surface of the substrate; forming a second package to cover the second chip, the second adhesive layer, part of the backside of the first chip, the second leads and part of the front side of the substrate; and A plurality of conductive elements are formed by forming the conductive elements on the front side of the substrate. 7. The method according to claim 6, wherein the first chip and the second chip have different sizes. 8. A method of forming a chip stack structure, comprising: A substrate is provided, which has a front side and a back side and is respectively configured with a circuit layout, and has an opening penetrating through the front side and the back side of the substrate; attaching a first chip on the part of the back of the substrate, with an active surface of the first chip facing down, and attaching a back of the first chip to the back of the substrate through an adhesive layer; Attaching a second chip on the back surface of the first chip is to face an active surface of the second chip upward and fix a back surface of the second chip to the first chip through the adhesive layer. on the back; forming a plurality of first wires to electrically connect the active surface of the first chip and the back surface of the substrate; forming a plurality of second wires to electrically connect the active surface of the second chip and the front surface of the substrate; forming a first package to cover the first chip, the adhesive layer, the first wires and the back surface of the substrate; forming a second package to cover the second chip, the adhesive layer, part of the backside of the first chip, the second leads and part of the front side of the substrate; and A plurality of conductive elements are formed by forming the conductive elements on the front side of the substrate. 9. The method according to claim 8, wherein the first chip and the second chip have different sizes. 10. The method according to claim 8, wherein the adhesive layer is epoxy resin or die attach film.

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