TWI233726B - Charge pump system and clock generator - Google Patents

Abstract

A current produced by a current mirror in a clock generator circuit for a charge pump is controlled by a temperature dependent, current-adjusting MOSFET which has a threshold voltage (Vt) that varies with temperature. As the temperature varies, the current through the a temperature dependent, current-adjusting MOSFET varies, to thereby control a frequency of the clock generator circuit. The MOSFET can be provided with a temperature-independent power supply, so that the current of the temperature dependent, current-adjusting MOSFET can be more closely controlled.

Description

1233726 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a memory device, particularly a charge pump circuit for a non-volatile semiconductor memory device that can be reprogrammed electrically. [Prior art]

A typical electrically reprogrammable non-volatile semiconductor memory device is an electrically erasable and programmable read-only memory (EEPR 0 M). The ninth picture is a traditional clock generator. In this method, the high-voltage power supply causes the channel resistance of the MOSFET to drop, which causes the capacitor to quickly charge, causing its output frequency to rise rapidly. However, high-temperature operation causes the channel resistance of the MOSFET to increase. If it drives a charge pump, it will cause it to operate at low voltage. Insufficient power supply or current supply capability at high temperatures. The ninth figure (a) is an example circuit of the ninth figure. Two PMOS are used to replace the current source I, two NMOS are used to replace the switches S1 and S2, the buffer is replaced by an inverter, and the logic switch control circuit controls S1, S. 2 Replaced by two reverse gates. The tenth graph is a graph showing the relationship between the frequency of a conventional clock generator and the pumping capability and current of a charge pump system using a conventional clock generator. As shown in Figure 11, the traditional clock generator is used in the charge pump system. Due to the difference in charge pumping capability, the difference between the clamping voltage between the high power supply voltage and the low power supply voltage is quite large. The twelfth figure (a) is the frequency generated by the traditional clock generator at the low power supply voltage, and the twelfth figure (b) is the frequency generated by the traditional clock generator at the high power supply voltage Frequency of. This frequency increases as the power supply voltage VDD increases. The entire contents of U.S. Patent No. 5,3,94,3,72 are hereby incorporated by reference, which refers to a part related to the present invention, which discloses a charge pump system used in the above memory, wherein the charge pump System frequency with power supply voltage VDD

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In this circuit structure, although the output frequency of the thunderbolt :: should show a negative correlation, its clock frequency changes to the heart rate and the voltage, which is difficult to control. The frequency also varies with ;:should! : T ΐ Γ.0.64; 2 75 ^ ^ ^ ^ = off part, which reveals that M0SFET has channel resistance which increases with temperature =, so that the current generated by the current mirror of the circuit cannot be optimally controlled [Content of the Invention] According to the invention, the current mirror of a clock generator increases its reference current as the temperature rises, so that the charging time of the capacitor is increased, so that the frequency of the clock generator increases as the temperature rises. Therefore, the period of the clock generator of the present invention is in a proportional relationship with the power supply and the output frequency increases as the temperature rises. The better one is that the clock generator is combined with a charge pump, so that the charge pump system has More stable voltage output. According to another feature of the present invention, the resistance value is a constant, so that the current generated by the current mirror can be controlled, and the resistance value can be independent of temperature. In a specific implementation, the current generated by the current mirror is controlled by a temperature-dependent current adjustment MOSFET, and the MOSFET has a threshold voltage that changes with temperature. When the temperature changes, the current adjusted by the temperature-dependent current M 0 s F E τ also changes, thereby controlling the frequency of the clock generator circuit. The MOSFET can be provided with a reference voltage independent of the temperature and the supply voltage, so that the current of the temperature-dependent current regulation MOSFET can be more closely controlled.

Page 10 1233726 V. Description of Invention (3) System. Various embodiments of the invention may include or indicate one or more of the following objects. One objective is to provide a clock generator whose frequency decreases with increasing power supply voltage and increases with increasing temperature. Using this clock generator to connect a charge pumping system can stabilize the pumping current and improve the clamping voltage. Vclamp varies between high power supply voltage (high VDD) and low power supply voltage (1 ow VDD). The use of a charge pump system on a flash memory can improve programming performance at low supply voltages and high temperatures. In addition, at high VDD programming, the charge pump system can reduce power consumption. Any feature or combination of features described herein is included in the # category of the present invention, provided that the features are included in any such combination without violating the consistency of each other, from the context, this description, and the knowledge of those skilled in the art Department is obvious. Other advantages and perspectives of the present invention will be apparent from the following detailed description and the scope of patent application. [Embodiments] Reference will now be made in more detail to the presently preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. It is only possible that the same or similar drawing numbers are used in the drawings and descriptions to refer to the same or similar parts. It should be noted that the diagram is in a simplified form and not precise in size. When referring to the disclosure, it is only for convenience and clarity. The direction names, such as top, bottom, left, right, up, down, above, above, below, behind, and front, correspond to the following The attached drawings are used. Such directional names should not be used in any way ~

Page 11 1233726 V. Description of the invention (4) is explained to limit the scope of the invention. Although the disclosure herein refers to specific illustrated embodiments, it should be understood that these embodiments are expressed by way of example and not limitation. Although the exemplary embodiments are discussed, the following detailed description is intended to cover modifications, variations, and equivalents of these embodiments, as falling within the spirit and scope of the invention as defined by the scope of the appended patents. It should be understood that the process steps and structures described herein do not cover the entire process of manufacturing the structure. The present invention can be implemented in combination with various integrated circuit manufacturing technologies, which are used in the traditional technical field, and only the general implementation process steps necessary to provide an understanding of the present invention are included here. The first diagram is a block diagram of a charge pump system. A pump circuit receives a signal generated by a clock generator to generate a pump current and a pump voltage. A voltage clamp is used to control the pump voltage value. The second figure shows that the clock generator of the present invention has a frequency that decreases as the power supply voltage VDD increases. The clock generator can improve the difference between the clamping voltage Vc lamp between the high power supply voltage high VDD and the low power supply voltage low VDD, as shown in the third figure. The fourth diagram is a conceptual diagram of the two-phase clock generator of the present invention. The fourth diagram (a) is a conceptual diagram of another clock generator according to another embodiment of the present invention. The fifth graph (a) is the frequency generated by the clock generator at a low power supply voltage. The fifth graph (a) is the waveform of the capacitor charge and discharge in the fourth graph, and the solid line of the capacitor MC 1 The waveform of the voltage node VD1 on the upper voltage node, and the dotted line is the waveform of the voltage node VD2 on the capacitor MC2. The fifth figure (b) is the frequency generated by the clock generator at a high power supply voltage, where the solid line is the capacitor MCI, '

Page 12 1233726 V. Description of the invention (5) _ And the dotted line is the capacitor MC2. This frequency decreases as the high supply voltage high VDD increases. As shown in the fifth figure, the rising slope of VD1 Δν / Δΐ = Ι / (; if the voltage of REDV in the fourth figure is VREF, the value of the horizontal dashed line in the fifth figure is VREF-Vt, where Vt is critical Voltage, in the fourth figure, when the voltage of node VD1 reaches VREF-Vt, MCI is turned off and MC2 is turned on, and the period of the output clock is 2 乂 (¥ 1 ^ [-¥ 1;) / (1 / (: ), If the voltage value of the output VREF of the voltage-dividing step-down circuit is controlled as α X VDD + Vt, where α is a constant, the waveform of the node VD 1 in the fifth figure rises to 0: when X ν DD, the logic is triggered The switch will cause node VD 1 to be pulled back to ground. Therefore, the period of node v D! Is directly proportional to the power supply VDD, which is 2 X (α X VDD) / (I / C). The relationship is tightly controlled. The sixth diagram is a circuit embodiment of the clock generator of the fourth diagram and / or the fourth diagram (a). In addition to CLK, a second phase output is added. According to a feature of the present invention The clock generator of the sixth figure can be interpreted as including a resistor (such as RCLK); —M0SFET (such as MZ0) has a gate, a drain and Source, the M0SFET is connected to the resistor to generate a reference current (for example, through MV0);-connected to the power supply voltage VDD and a stable first reference voltage (for example, AVXRD) to control the M0SFET; And MV2), by mirroring the reference current to generate a first (eg, through MV1) and second (eg, through MV2) mirror current; a first capacitor (eg, MCI), receiving the first mirror current and generating a first A charging voltage (such as VD1); a second capacitor (such as MC2) that receives the second mirror current and generates a second charging voltage (such as VD2); and a logic circuit (such as including a pair of anti-and-gate) to receive the First and second charging voltages and generating a clock signal

Page 13 1233726 V. Description of the invention (6) CLK. According to another feature of the present invention, the circuit may further include a second reference voltage (for example, REDV1) generated from an input supply voltage (for example, VDD) to control the first and second charging voltages. When the power supply voltage VDD rises, the charging time of the capacitors MCI and MC2 increases and the frequency decreases. As the power supply voltage VDD rises, the second reference voltage REPV1 rises accordingly, which causes the charging voltages of the capacitors MCI and MC2 to rise. According to the fifth graphs (a) and (b), when the charging voltages of the capacitors MCI and MC2 rise The period becomes larger and the period is inversely proportional to the frequency, so the frequency becomes smaller. Therefore, when the power supply voltage VDD rises, the frequencies of the capacitors MCI and MC2 decrease. When the temperature rises, the critical voltage Vt of the temperature-dependent current adjustment MOSFET MZO decreases, which makes the RCLK cross-voltage high, and the current through MΥO, MY1, and MY2 rises accordingly, and the frequency rises correspondingly. Therefore, according to a feature of the present invention, the reference current is processed to rise with temperature, so that the charge valleys M C 1 and M C 2 are charged more quickly as the temperature rises. Selecting the appropriate MZO can determine the frequency (for example, frequency reduction) that changes with the clock generator temperature, for example, using theoretical and empirical data. In the next step, an increase in operating temperature will increase the frequency, and the frequency is a desired frequency that can be determined. These decisions can be made for various operating parameters, such as for a range of different supply voltage (VDI) values. example

From a voltage VDDlow to a high power supply voltage VDDhigh), a desired set of frequencies (or a change in frequency ', e.g., a frequency rise) can be determined over a temperature range. This data can also vary depending on the different charge pump and / or clamping voltages V c 1 a m p implemented. For example, this material can be listed and / or

1233726 V. Description of the invention (Ό Figure. According to a feature of the present invention, any parameter can be designed / implemented here to control (eg, change and preferably increase) the charging current to MCj and MC2 'and thus change ( For example, increase the current to M (η and MC2, so that the desired frequency is obtained as the operating temperature changes. When the temperature rises, the critical voltage Vt of MZO is a negative temperature coefficient, so Vt decreases, so that the flow through the resistance The current of RCLK increases, and the current flowing through resistor RCLK is mirrored by a current mirror composed of Mγ0 and MY1 AMY2. Therefore, the charging current of MC 1 and MC2 increases. The sixth figure (a) is an illustration of the sixth figure Circuits. Various forms of control devices / components / arrangements can be implemented to achieve the function of frequency control. The general architecture of this device is shown in the fourth figure (a), as indicated by "I ref (increasing with temperature), However, it should be understood that other devices can be built next to or in addition to a current mirror circuit, where the reference current changes (or is controlled) as the temperature changes. In addition, in the illustrated In other embodiments, the reference current may not change with temperature or actually decrease at a specific temperature in a temperature range under certain conditions. In the illustrated embodiment of the sixth figure, MZO is selected to have a temperature dependent The rising and falling threshold voltage (Vt) causes the desired reference current to be generated as the temperature rises. In a preferred embodiment, a reference voltage AVXRD that is independent of the supply voltage v DD and temperature is used to provide more consistency And predictable results. In other embodiments, the voltage AVXRD is omitted. The seventh diagram is a conceptual diagram of the multi-phase clock generator of the present invention, and the eighth diagram is a multi-phase clock generator shown in the seventh diagram. The circuit embodiment of the device. The eighth figure (a) is an exemplary circuit of the eighth figure. In view of the above, those skilled in the art will understand the method of the present invention.

Page 15 1233726 V. Description of the invention (8) A read-only memory device can be formed in an integrated circuit, especially a read-only memory device with a two-bit memory cell structure. The embodiments described above are presented by way of examples, but the present invention is not limited to these examples. For those skilled in the art, after considering the above, multiple changes and modifications to the embodiments disclosed in the present invention may occur without mutually exclusive extensions. However, such changes and modifications fall within the scope of the invention set by the scope of the following patent applications.

Page 1233726 Brief description of the drawings For those skilled in the art, from the following detailed description and accompanying drawings, the present invention will be more clearly understood, its above and other purposes and advantages will become It is more obvious, in which: the first diagram is a block diagram of a charge pump system; the second diagram is a clock generator according to the present invention which has a frequency that decreases as the power supply voltage increases; the third diagram is a clock generator according to the present invention The difference in clamping voltage can be improved; the fourth diagram is a conceptual diagram of a two-phase clock generator of the present invention; the fourth diagram (a) is a conceptual diagram of another clock generator of another embodiment of the present invention; The fifth figure (a) is the frequency generated by the clock generator at a low power supply voltage; the fifth figure (b) is the frequency generated by the clock generator at a high power supply voltage; the sixth chart is the first A circuit embodiment of the clock generator in the fourth diagram and / or the fourth diagram (a); the sixth diagram (a) is an example circuit of the sixth diagram, and the seventh diagram is a multi-phase clock generator of the present invention. Conceptual diagram; the eighth diagram is a polyphase clock in the seventh diagram The circuit embodiment of the generator; the eighth figure (a) is an example of the eighth figure, the ninth figure is a traditional clock generator; the ninth figure (a) is an example circuit of the ninth figure; the tenth figure Shows the frequency of traditional clock generators and the use of traditional clocks

Page 13123726 The diagram briefly illustrates the relationship between the pump capacity and the pump current of the charge pump system of the generator. Figure 11 shows the clamping voltage of a traditional clock generator in the charge pump system. Figure 12 (a) shows the frequency generated by a conventional clock generator at a low power supply voltage; and Figure 12 (b) shows the frequency generated by a traditional clock generator at a high power supply voltage frequency. _

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Claims (1)

1233726 6. Application patent scope 1. A clock generator includes: a resistor; a MOSFET having a gate, a drain and a source, the source is connected to the resistor to generate a reference current; and A power source voltage and a temperature-independent first reference voltage to control the MOSFET; a current mirror circuit that mirrors the reference current to generate a first and a second mirror current; a first capacitor to receive the first mirror current And generating a first charging voltage; a second capacitor receiving the second mirror current and generating a second charging voltage; a second reference voltage generated from an input supply voltage to control the first and second charging voltages And a logic circuit that receives the first and second charging voltages and generates a clock signal. 2. For example, the clock generator of the first patent application range, wherein the first capacitor, the second capacitor and the resistor determine the period of the clock signal. 3. A clock generator includes: a current mirror circuit that mirrors a reference current to generate a first and a second mirror current, the reference current increasing with temperature; a first capacitor receiving the first Mirror current and generating a first charging voltage; a second capacitor receiving the second mirror current and generating a second charging Page 19 1233726 6. Patent application voltage; and a logic circuit that receives the first and second charging voltages and generates a clock signal. 4. If the clock generator of item 3 of the patent application scope further includes: a resistor; and an M 0 SFET with a gate, a drain, and a source, the MOSFET is connected to the resistor to generate the reference Current. 5. The clock generator of item 4 of the patent application, wherein the MOSFET has a threshold voltage that decreases as the temperature rises. 6. The clock generator of item 5 of the patent application range, wherein the threshold voltage decreases as the temperature rises, so that a current through the MOSFET increases as the temperature rises. 7. For the clock generator of item 6 of the patent application scope, wherein the threshold voltage decreases as the temperature rises, so that the frequency of the clock signal increases as the temperature rises. 8. As the clock generator in the fourth item of the patent application, wherein the first capacitor, the second capacitor and the resistor determine the period of the clock signal. 9. If the clock generator of item 4 of the patent application scope, further includes a first reference voltage independent of a power supply voltage and temperature to control the MOSFET ° 10. If the clock generator of item 7 of the patent application scope, It further includes a second reference voltage generated from an input supply voltage to control the first and second charging voltages. Page 20