CN102664616B - Integrated clock circuit - Google Patents
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- CN102664616B CN102664616B CN201210114007.7A CN201210114007A CN102664616B CN 102664616 B CN102664616 B CN 102664616B CN 201210114007 A CN201210114007 A CN 201210114007A CN 102664616 B CN102664616 B CN 102664616B
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Abstract
The invention provides an integrated clock circuit with tolerance capacity for temperature change, grounding voltage change or power voltage change. The modified integrated clock circuit can tolerate one or various changes including the temperature change, the grounding voltage change and the power voltage change in different embodiments.
Description
The application divides an application, the application number of female case: 200910260481.9, and the applying date: on December 15th, 2009, title: the clock circuit of integrated circuit.
Technical field
The invention relates to the integrated circuit with clock circuit, the variations such as its tolerable such as temperature, ground noise, power supply noise.
Background technology
The running meeting of the clock circuit of integrated circuit has variation with factors such as temperature, ground noise, power supply noises.Because these make a variation, can affect the final sequential of clock signal, the existing multinomial research phase of carrying out can, for this problem, in the situation that above-mentioned variation exists, produce more uniform clock signal.
For example, the United States Patent (USP) of Gaboury the 7th, utilizes for 142, No. 005 to increase to have the initiatively mode of buffer circuit, independent bias circuit system and the bias circuit system of load, carrys out the impact of insulating power supply fluctuation on clock signal.In order to reach the impact of insulating power supply fluctuation on clock signal, the buffer circuit of these relative complex causes the significantly increase of chip area and cost.
Therefore cause the demand, hope can solve these variation problems, but adopts more uncomplicated structure and less cost.
Summary of the invention
The present invention is to provide a kind of technology with the device of integrated circuit of clock.
This integrated circuit of clock has a bolt lock device, produces a clock signal output of this integrated circuit of clock.This bolt lock device comprises the gate coupling alternately, and so the input of the output of this gate coupling alternately in this bolt lock device and this Different Logic door coupling alternately in this bolt lock device couples.
The output that this integrated circuit of clock also has a sequence circuit and this bolt lock device couples, one output of this sequence circuit is switched between one first reference signal and one second reference signal, and a speed of this switching is to decide with the time constant of temperature correlation by one.This output of this sequence circuit determines the sequential of this clock signal output.
This integrated circuit of clock also has a negative circuit, relatively one of this sequence circuit output and a temperature-compensating reference value, so this sequential of this clock signal output of this integrated circuit of clock can be kept out temperature change, and an output and an input of this bolt lock device of this negative circuit couple.
In certain embodiments, this time constant is an exponential signal.
In certain embodiments, this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage and from this second reference voltage, is discharged between the state of this first reference voltage at this first reference voltage certainly and switches.
In certain embodiments, this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit, response is to this negative circuit, charges to the state of this second reference voltage and from this second reference voltage, is discharged between the state of this first reference voltage switch at this first reference voltage certainly.Wherein this temperature-compensating trigger point of this negative circuit is one the 3rd reference voltage, and it is along with temperature increases and reduces.In one embodiment, this temperature-compensating trigger point of this negative circuit is produced by a temperature-compensating power supply.
Another object of the present invention, for a kind of device with integrated circuit of clock is provided, replaces inverter with Schmidt trigger circuit.
Another object of the present invention, for a kind of device with integrated circuit of clock is provided, replaces inverter with operation amplifier circuit, and adds the reference circuit of a current generator type, produces this temperature-compensating reference value.
In many different embodiment, the reference circuit of this current generator type is a current generator and a resistance characteristic device, comprise a resistance, diode and a metal-oxide semiconductor transistorized any; And some other device has CTAT (with temperature inverse ratio) characteristic and PTAT (with temperature direct ratio) characteristic device one of at least as one.
A further object of the present invention, for a kind of device with integrated circuit of clock is provided, comprises the clock signal output that a bolt lock device produces this integrated circuit of clock.This bolt lock device comprises one first gate and one second gate couples each other alternately.One output of this first gate couples with one first input of this second gate.One output of this second gate couples with one first input of this first gate.One second input of this output of this second gate and this first gate couples via at least one the first sequence circuit and one first inverter.One second input of this output of this first gate and this second gate couples via at least one the second sequence circuit and one second inverter.
This first sequence circuit has an output and with a first rate, switches between one first reference signal and one second reference signal, and this first rate is to decide with the very first time constant of temperature correlation by one.
This second sequence circuit has an output and with one second speed, switches between this first reference signal and this second reference signal, and this second speed is to decide with one second time constant of temperature correlation by one.
The described output of this first sequence circuit and this second sequence circuit determines the sequential of this clock signal output.
This first inverter is an output and one first temperature-compensating reference value of this first sequence circuit relatively, and it is one first temperature-compensating trigger point of this first inverter.
This second inverter is an output and one second temperature-compensating reference value of this second sequence circuit relatively, and it is one second temperature-compensating trigger point of this second inverter.
In one embodiment, this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and from this second reference voltage, are discharged between the state of this first reference voltage at this first reference voltage certainly and switch.In one embodiment, described temperature-compensating reference value is one the 3rd reference voltage, and it is along with temperature increases and reduces.
In one embodiment, this first and second time constant is an exponential signal.
In one embodiment, this first and second temperature-compensating reference value is to produce from a common reference circuit.
In one embodiment, this first and second temperature-compensating reference value is to produce from different reference circuits.
Another object of the present invention, for a kind of device with integrated circuit of clock is provided, replaces array inverter with array Schmidt trigger circuit.
Another object of the present invention, for a kind of device with integrated circuit of clock is provided, replaces array inverter with array operation amplifier circuit, and adds the reference circuit of a current generator type, produces this temperature-compensating reference value.
Accompanying drawing explanation
The present invention is defined by claim.These and other objects, feature, and embodiment, the accompanying drawing of can arranging in pairs or groups in the chapters and sections of following execution mode is described, wherein:
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that is for example temperature, earthed voltage or power supply voltage variation ability to bear.
Fig. 2 A and Fig. 2 B show a circuit diagram having the integrated circuit clock circuit of temperature change ability to bear, it comprises a negative circuit with the output of assessment sequence circuit, wherein Fig. 2 A have capacitive character sequence circuit with couple and Fig. 2 B has capacitive character sequence circuit and supply coupling.
Fig. 2 C shows to have the circuit diagram to the integrated circuit clock circuit of temperature change ability to bear, its and Fig. 2 category-A seemingly, but from a PTAT power supply reception power supply rather than from CTAT power supply.
Fig. 2 D shows a circuit diagram having the integrated circuit clock circuit of temperature change ability to bear, and it comprises a Schmidt trigger circuit to assess the output of this sequence circuit.
Fig. 2 E shows the schematic diagram of a Schmidt trigger circuit, for example, in Fig. 2 D.
Fig. 3 A and Fig. 3 B show a circuit diagram having the integrated circuit clock circuit of temperature change ability to bear, it comprises an operation amplifier circuit to be detected with the level that a reference value is carried out sequence circuit output by output relatively, wherein Fig. 3 A have capacitive character sequence circuit with couple and Fig. 3 B has capacitive character sequence circuit and supply coupling.
Fig. 4 A shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature.
Fig. 4 B shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the CTAT current source that increases electric current output along with the increase of temperature.
Fig. 4 C shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature, and it is in parallel with the load resistance of a current mirror to have more a capacitor.
Fig. 4 D is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from PMOS device.
Fig. 4 E is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from NMOS device.
Fig. 4 F is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from PMOS device.
Fig. 4 G is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from NMOS device.
Fig. 5 A shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output reducing along with the increase of temperature.
Fig. 5 B shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the current source that increases electric current output along with the increase of temperature, and the output increasing along with the increase of temperature.
Fig. 5 C shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output increasing along with the increase of temperature.
Fig. 5 D shows the circuit diagram as the reference signal of the level circuit for detecting of Fig. 5 C, but comprise one, has the current source that increases electric current output along with the increase of temperature.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES 524.
Fig. 6 A shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 6 B shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 7 A shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 7 B shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram to the integrated circuit clock circuit of ground noise change ability to bear, it comprises a transistor and optionally couples with ground noise, a part of usining as the reference signal of the level detecting of this sequence circuit output, wherein Fig. 8 A have capacitive character sequence circuit with couple and Fig. 8 B has capacitive character sequence circuit and supply coupling.
Fig. 9 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise change, and it produces clock sequential and can change significantly the ground noise changing along with the time.
Figure 10 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise change, and it can produce metastable clock sequential because of the circuit in Fig. 8 in to the ground noise changing along with the time.
Figure 11 A and Figure 11 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detecting of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output, wherein Figure 11 A have capacitive character sequence circuit with couple and Figure 11 B has capacitive character sequence circuit and supply coupling.
Figure 12 shows the circuit diagram of a power circuit, and it shares identical noise phase with the power supply noise of the reference signal of the power supply noise of sequence circuit power supply and the level detecting of sequence circuit output.
Figure 13 is one group of voltage and the graph of a relation of time, and it shows because as the circuit relationships in Figure 11 or Figure 12 to have identical noise phase between the reference signal how to detect with the level that is used in sequence circuit output at sequence circuit power supply.
Figure 14 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having power supply noise change, and it can produce clock sequential in to the power supply noise significantly changing along with the time.
Figure 15 is one group of voltage and the graph of a relation of time, it shows that this clock circuit is the ability to bear how having power supply noise change, and it can produce metastable clock sequential because of the circuit in Figure 11 and Figure 12 in to the power supply noise significantly changing along with the time.
Figure 16 A and Figure 16 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detecting of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output, similar with Figure 11, and increased commutation circuit, for example, when electric power starting, optionally to walk around this noise, tolerated circuit.
Figure 17 can apply the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, and also comprises commutation circuit between with reference to generator and operational amplifier.
Embodiment
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that is for example temperature, earthed voltage or power supply voltage variation ability to bear.
This integrated circuit clock circuit is a loop structure normally, has sequence circuit 102, level commutation circuit 104 and latch circuit latch circuit 106.These latch circuit latch circuit 106 generations one are the feedback signal to sequence circuit 102 from latch circuit latch circuit 106, and a clock output signal 110.This sequence circuit 102 switches between two reference signals according to a time constant.Therefore this time constant has determined the sequential of this integrated circuit clock circuit.A typical time constant example is an exponential time constant, and it is by a RC circuit or the rising of RL circuit and characterization fall time.The output of this level commutation circuit monitoring sequence circuit 102, and change its output according to this sequence circuit 102 is whether enough high or low.The example of latch circuit 106 is SR bolt lock device, SR NAND bolt lock device, JK bolt lock device, gate-type SR bolt lock device, gate-type D bolt lock device, gate-type triggering bolt lock device etc.This latch circuit circuit 106 has two stable states and switches to produce a clock output signal 110 between these two stable states.
Two reference signals that sequence circuit 102 relies on are produced by circuit 116, and it also can produce the level switching reference signal that level commutation circuit 104 relies on.By simultaneously, for sequence circuit 102 produces the reference signal relying on and switches reference signal for level commutation circuit 104 produces the level relying on, circuit 116 can be reduced to the noise phase of the reference signal that sequence circuit 102 relies on and the shared noise signal of the level switching reference signal relying on for level commutation circuit 104.Because any noise phase is very little, the peak value of this sequence circuit 102 noise signal in reference signal that relies on and valley are that the peak value and the valley that switch the noise signal in reference signal with level commutation circuit 104 level that relies on are synchronizeed.
The level that level commutation circuit 104 relies on is switched reference signal 112, by circuit 118, is chosen itself and level commutation circuit 104 are coupled.In certain embodiments, this can maintain ground noise as a sampling, so identical ground noise can be maintained by sequence circuit 102, and the level that can be relied on by level commutation circuit 104 is switched reference circuit and maintained.
Although calcspar shown here can solve the change problem of temperature, earthed voltage or supply voltage, but one in different embodiments of the invention improvement clock circuit only solve these variable parameters one of them only (for example: only for temperature noise, only for earthed voltage noise or only for supply voltage noise), or these variable parameters wherein two only (for example: only for temperature and supply voltage noise, only for temperature and earthed voltage noise or only for supply voltage and earthed voltage noise).
Fig. 2 A and Fig. 2 B show a circuit diagram having the integrated circuit clock circuit of temperature change ability to bear, and it comprises a negative circuit with the output of assessment sequence circuit.
The sequence circuit 202A and the 202B that in accompanying drawing, show parallel placement, the negative circuit 204A of parallel placement and 204B, and a latch circuit 206.This sequence circuit 202A and 202B be an inverter with resistance R X or RY normally, and self-capacitance CX or CY carry out charge or discharge, to change the output voltage of OX or OY.
Fig. 2 A shows an embodiment, and wherein capacitor C X or CY couple with Shu common ground.Although do not express all possible variation in accompanying drawing, technology of the present invention comprises the sequence circuit in all embodiment with capacitor C X or CY, wherein sequence circuit can be revised as capacitor C X or CY are coupled with a common ground.
In one embodiment, capacitor C X or CY are actually common ground end that a PMOS transistor has contrary end points and inverter and remove and to couple.
Fig. 2 B shows an embodiment, and wherein capacitor C X or CY are and the common supply coupling of Shu.Although do not express all possible variation in accompanying drawing, technology of the present invention comprises the sequence circuit in all embodiment with capacitor C X or CY, wherein sequence circuit can be revised as and by capacitor C X or CY be and a common supply coupling.
In one embodiment, capacitor C X or CY are actually common power end that a PMOS transistor has contrary end points and inverter and remove and couple.
This negative circuit 204A and 204B are by a CTAT power supply or one and the power supply that is inversely proportional to of temperature, and it can reduce along with the increase of temperature, drives.
This inverter is very different from operational amplifier version.In operational amplifier version, the output of a Vref and sequence circuit (as the rise/fall of RC circuit) compares.Therefore and in inverter version, the power supply of this inverter is controlled, to change the stroke of this inverter and to detect the output (as the rise/fall of RC circuit) of sequence circuit.In this inverter version, an extra temperature relation about power supply and inverter stroke comes into one's own.
This inverter has advantages of following compared to operational amplifier version: the operating voltage VDD that (1) is lower; (2) less circuit size (inverter only has two metal-oxide semiconductor transistors and operational amplifier has five or above metal-oxide semiconductor transistor); (3) better simply design; (4) lower active electric current (inverter has a current path, and operational amplifier has two or three current paths and comprise an extra current mirror); And (5) higher operating rate (inverter has the delay in a stage, and operational amplifier has the delay in two or three stages).
This latch circuit 206 couples alternately, and the output of a gate like this and the input of another gate couple.One input of one gate is directly to couple with the output of another gate, another input of this gate be directly and the output of another gate pass through sequence circuit and level circuit for detecting and couple.
Another embodiment of Fig. 2 C display timing generator circuit.Although major part and Fig. 2 category-A are seemingly, the sequence circuit 202A of parallel placement in Fig. 2 C and 202B are by a PTAT power supply or a power supply being directly proportional to temperature, and it can increase along with the increase of temperature, drives.Although do not express all possible variation in accompanying drawing, technology of the present invention comprises the sequence circuit in all embodiment with CTAT power supply, wherein CTAT power supply can be replaced by PTAT power supply.
Similarly, although do not express all possible variation in accompanying drawing, technology of the present invention comprises the sequence circuit in all embodiment with PTAT power supply, and wherein PTAT power supply can be replaced by CTAT power supply.
Fig. 2 D shows a circuit diagram having the integrated circuit clock circuit of temperature change ability to bear, and it comprises a Schmidt trigger circuit to assess the output of this sequence circuit.
Although Fig. 2 category-B seemingly, the level commutation circuit 210A in Fig. 2 D and the Schmidt trigger circuit of 210B are to be driven by a CTAT power supply, and comprise the operational amplifier having by the loop positive feedback of resistance.
Fig. 2 E shows the schematic diagram of a Schmidt trigger circuit.
Fig. 3 shows that one has the circuit diagram to the integrated circuit clock circuit of temperature change ability to bear, and it comprises an operation amplifier circuit to be detected with the level that a reference value is carried out sequence circuit output by output relatively.
The sequence circuit 302A and the 302B that in accompanying drawing, show parallel placement, level commutation circuit 304A and the 304B of parallel placement, and a latch circuit 306.This level commutation circuit 304A and 304B are that an operation amplifier comparator has a reference voltage CTAT_REF.Except this, this clock circuit roughly with Fig. 2 category-A seemingly.
Fig. 4 A shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the current source that increases electric current output along with the increase of temperature.
How the CTAT power supply signal that Fig. 4 A demonstrates dependence level circuit for detecting produces, and is shown as CTAT_REF 428 in this figure.A PTAT_I current source 426 of quantitatively exporting, can produce the electric current that be directly proportional to temperature through resistance R ES 424 from power regulator 422, along with the increase of temperature, increases.This power regulator 422 can be exported the temperature independent voltage of determining.This regulates power supply that certain power supply and can be along with VDD and temperature change is provided.For example, the output of this adjuster has one and can be with reference value.This Output rusults and temperature are inversely proportional to, and be also to increase, and the skew of the exit point of this pressure drop lower end are to reduce because temperature is crossed over the pressure drop of this resistance while increasing.An example of this current source is shown in Fig. 4 E.
Fig. 4 B is a variation of Fig. 4 A circuit, wherein PTAT_I constant current source 426 is replaced by CTAT_I constant current source 430, and the CTAT_REF428 of the CTAT power supply signal of dependence level circuit for detecting is replaced by the PTAT_REF 432 that relies on the PTAT power supply signal of level circuit for detecting.An example of this current source is shown in Fig. 4 G.
Fig. 4 C is a variation of Fig. 4 A circuit, has a by-pass capacitor 434 in parallel with resistance R ES 424, to reduce noise.In addition, this current source comprises a current mirror.An example of this current source is shown in Fig. 4 D.
Fig. 4 D is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from PMOS device.
Fig. 4 E is the schematic diagram of a current feedback circuit, and it provides PTAT electric current according to reference circuit from NMOS device.
In Fig. 4 D and Fig. 4 E, this circuit is used between two delta_Vg with the same current nmos pass transistor of the temperature of being proportional to.So delta_Vg/ resistance=PTAT_I.In Fig. 4 D and Fig. 4 E, two transistors with circle are identical.
Fig. 4 F is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from PMOS device.
Fig. 4 G is the schematic diagram of a current feedback circuit, and it provides CTAT electric current according to reference circuit from NMOS device.
A current feedback circuit according to reference circuit described herein is preferably, because in many examples, singlely can be controlled with parameter temperature correlation, rather than two material relevant parameters with temperature correlation, it has different temperature associations.
Fig. 5 A shows the circuit diagram of the reference signal of level circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature.
How the CTAT power supply signal that Fig. 5 A demonstrates dependence level circuit for detecting produces, and is shown as CTAT_REF 528 in this figure.A PTAT_I current source 526 of quantitatively exporting, can produce through resistance R ES 524 electric current being inversely proportional to temperature from power regulator 522, along with the increase of temperature, reduces.This Output rusults and temperature are inversely proportional to, and be also to reduce, and the skew of the exit point of this pressure drop upper end are also to reduce because temperature is crossed over the pressure drop of this resistance while increasing.
Shown in of current source be illustrated as one and repeatedly connect current source.
Fig. 5 B, Fig. 5 C, Fig. 5 D and Fig. 5 E are other examples that produces reference voltage signal.
Fig. 5 B is a variation of Fig. 5 A circuit, wherein CTAT_I constant current source 526 is replaced by PTAT_I constant current source 530, and the CTAT_REF528 of the CTAT power supply signal of dependence level circuit for detecting is replaced by the PTAT_REF 532 that relies on the PTAT power supply signal of level circuit for detecting.
Fig. 5 C is a variation of Fig. 5 A circuit, and wherein resistance R ES 524 is replaced by diode DI0530.An example of this current source is shown in Fig. 4 F.
Fig. 5 D is a variation of Fig. 5 A circuit, and wherein CTAT_I constant current source 526 is replaced by PTAT_I constant current source 530, and the skew of exit point moves to the pressure drop of crossing over this constant current source lower end from the pressure drop of crossing over this constant current source upper end.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES 524.
Fig. 6 A shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, and it produces clock sequential and can change significantly along with the change of temperature.
Fig. 6 A shows between the track region of a high temperature, a low temperature and a moderate temperature.Temperature is lower, and this sequence circuit becomes faster, and temperature is higher, and this sequence circuit becomes slower.Because the common reference signal of sequence circuit, this sequence circuit can arrive at sooner reference value when low temperature when high temperature.Therefore, the sequential of this clock circuit can be faster when high temperature when low temperature.
Fig. 6 B shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces clock sequential and substantially along with the change of temperature, does not change.
Fig. 6 B shows between the track region of a high temperature, a low temperature and a moderate temperature.As shown in Figure 6A, temperature is lower, and this sequence circuit becomes faster, and temperature is higher, and this sequence circuit becomes slower.Yet, because use different sequence circuits in Fig. 6 B, be different from the sequence circuit using in Fig. 6 A.Although sequence circuit can arrive at sooner reference value when low temperature when high temperature, the reference value of this sequence circuit is also relative higher.Therefore, the sequential of this clock circuit demonstrates very little temperature change, but causes the speed fluctuation of this clock circuit.
Fig. 7 A and Fig. 7 B are other embodiment, and it shows the rising signals in dropping signal rather than Fig. 6 A and Fig. 6 B, but still show identical time constant.
One clock signal is rising signals in dependency graph 6A and Fig. 6 B or the dropping signal in Fig. 7 A and Fig. 7 B, be according to capacitor C X or CY be with Fig. 2 A in ground couple or determine with the supply coupling in Fig. 2 B.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram to the integrated circuit clock circuit of ground noise change ability to bear, it comprises a transistor and optionally couples with ground noise, a part of usining as the reference signal of the level detecting of this sequence circuit output.
The sequence circuit 802A and the 802B that in accompanying drawing, show parallel placement, level commutation circuit 804A and the 804B of parallel placement, and a latch circuit 806.This level commutation circuit 804A and 804B optionally couple with the ground noise that switches reference circuit 816A and 816B from level, and be stored in capacitive node REF X or REF is Y, according to the switching behavior of the switching transistor 818A being opened by signal ENX and the switching transistor 818B that opened by signal ENY, determined separately.This can maintain ground noise as a sampling, so identical ground noise can be maintained by sequence circuit 802A or 802B, and node R EF X or the REF Y of the level that can be relied on by level commutation circuit 104 switching reference circuit are maintained.
In one embodiment, capacitor C X or CY are actually a PMOS transistor to be had contrary end points and removes and couple with common power end, and this common power supply is connected with RX or RY.
When ENX is high levle, OX keeps ground connection.Afterwards, ENX becomes low level and closes NMOS; Ground noise is maintained at OX at this moment.If it is very fast that noise is precharge speed of high levle; If it is very slow that noise is precharge speed of low level.This circuit makes REFX or REFY keep identical ground noise at same time.
In Fig. 8 A, this switches reference circuit reference node REFX or REFY, comprise condenser network with couple.In Fig. 8 B, this switches reference circuit reference node REFX or REFY, comprises condenser network and supply coupling.
In different embodiment, it can be two groups of different circuit or sequence circuit and the multiple level commutation circuit 804A by parallel placement shared with 804B with set of circuits that level is switched reference circuit 816A and 816B.
Fig. 9 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise change, and it produces clock sequential and can change significantly the ground noise changing along with the time.
Fig. 9 shows that locus O X and OY are how by ground noise, affect for REF_LO signal in this figure.When ground noise has a peak value, this sequence circuit can start to charge to from REF_LO the program of REF_HI, causes sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Therefore, this clock signal output 910 has a wider change in this clock cycle.
When ENX is high levle, OX keeps ground connection and voltage to change along with ground noise.When ENX is low level, and close NMOS, ground noise is maintained at OX.But still along with ground noise, change with reference to level.The worst situation be OX keep the ground noise of a high levle and between charge period this reference circuit bear a negative ground connection level; This reference value can be low far beyond being contemplated to.Therefore the similar sampling of Shu and maintenance structure keep identical ground noise at REFX or REFY.
Figure 10 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having ground noise change, and it can produce metastable clock sequential because of the circuit in Fig. 8 in to the ground noise changing along with the time.
Figure 10 shows that locus O X and OY are how by ground noise, affect for REF_LO signal in this figure.When ground noise has a peak value or other change, this peak value or other change can be stored in the capacitive node REF X in Fig. 8 or REF is Y.Because ground noise is followed the trail of by sampling rear maintenance reference circuit the impact of REF_LO signal, this level circuit for detecting is from the level detecting reference circuit ground noise more identical with sequence circuit.In ground noise, with this, sampled after the mode of rear maintenance, ground noise, it can continue to change, and removes and couples since then in sample circuit.Therefore, this sequence circuit from REF_LO charge in the program of REF_HI not one in advance, although there is ground noise, this sequence circuit still needs the identical time to charge to REF_HI from REF_LO.Therefore, cause this clock signal output 910 still to there is the identical clock cycle under a ground noise extensively changing.
In another embodiment, be after ground noise sampling, when discharging, this ground noise and sample circuit releasing to be coupled again, rather than when charging, this ground noise and sample circuit releasing are coupled as shown in Fig. 9 and Figure 10.This embodiment can cause extra problem because must solve the power supply noise problem that self noise power regulator produces.
(similar Fig. 2 C) in another embodiment, this sampling and holding circuit can keep power supply noise rather than ground noise.
Figure 11 A and Figure 11 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, the noise phase of the power supply noise shared in common of the reference signal of the level detecting of the power supply noise that it comprises a transistor AND gate sequence circuit power supply and sequence circuit output.
The sequence circuit 1102A and the 1102B that in accompanying drawing, show parallel placement, level commutation circuit 1104A and the 1104B of parallel placement, and a latch circuit 1106.Also comprise as shown in the figure sequential power supply and level and switch reference value generator 1116A and 1116B, it can produce the identical noise phase of power supply noise of the reference signal of detecting with the power supply noise of sequence circuit power supply and the level of sequence circuit output.
In Figure 11 A, this condenser network CX or CY and couple.In Figure 11 B, this condenser network CX or CY and power supply 1116A or 1116B couple.
Figure 12 shows the circuit diagram of a power circuit, and it shares identical noise phase with the power supply noise of the reference signal of the power supply noise of sequence circuit power supply and the level detecting of sequence circuit output.
Figure 12 shows that a power supply 1236 drives an operational amplifier 1232.This operational amplifier has a reference signal REF_OP 1234 in its noninverting input.One of this REF_OP 1234 is illustrated as an energy-gap reference circuit in 1.3V.The output that one metal oxide semiconductor field effect answers transistor 1238 to have a gate and operational amplifier 1232 couples, and a drain and power supply 1236 couple, and one source pole and sequential power supply output 1246 couples.The output 1246 of sequential power supply is separated by resistance R 11240 with level switching reference value 1248.Level switching reference value 1248 is separated by resistance R 21242 with the negative feedback point of operational amplifier 1232.Finally, resistance R 3 by this negative feedback point with couple.
Another embodiment is used the capacitive coupling of suspension joint node to switch noise phase identical between reference value 1248 to maintain the output 1246 of sequential power supply with level, and wherein the output 1246 of sequential power supply is suspension joint with one of level switching reference value 1248.
Although the above embodiments are especially designed in order to maintain noise phase identical between the output 1246 of sequential power supply and level switching reference value 1248, are not like this in other design.In other design, sequential power supply output 1246 and level are switched between reference value 1248 for one of following reason or many persons and are had different noise phase: (1) is because the configuration of crystal grain makes the close sequence circuit of reference circuit; (2) to have compared with VDD power supply be good power supply supply refusal ratio (PSRR) to the reference circuit in adjuster; And (3) even RC power supply has power regulator, because different output loadings and transformation, a noise phase difference still can maintain, and this power regulator must support larger electric current and larger output to change.
Figure 13 is one group of voltage and the graph of a relation of time, and it shows because as the circuit relationships in Figure 11 or Figure 12 to have identical noise phase between the reference signal how to detect with the level that is used in sequence circuit output at sequence circuit power supply.
The sequence circuit power supply 1301 that Figure 13 shows and be used in both power supply noises between the reference signal of level detecting of sequence circuit output 1302 and there is identical noise phase.By track 1303 be positioned over track 1301 and 1302 on can show this situation, although the size of power supply noise changes, and the peak value of the power supply noise of track 1301 and 1302 is synchronizeed with valley.
Figure 14 is one group of voltage and the graph of a relation of time, and it shows that this clock circuit is the ability to bear how having power supply noise change, and it can produce clock sequential in to the power supply noise significantly changing along with the time.
Figure 14 shows how locus O X and OY are affected by power supply noise 1401.When power supply noise has one to decline to a great extent, this sequence circuit can start to charge to from REF_LO the program of REF_HI, causes sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Similarly, when power supply noise has a peak value, the program that this sequence circuit charges to REF_HI from REF_LO can become slower, causes the more time of sequence circuit needs just can charge to REF_HI from REF_LO.These changes are to occur after the level of stable (definite value) is switched reference value.Therefore, this clock signal output 1410 has a wider change in this clock cycle.
Figure 15 is one group of voltage and the graph of a relation of time, it shows that this clock circuit is the ability to bear how having power supply noise change, and it can produce metastable clock sequential because of the circuit in Figure 11 and Figure 12 in to the power supply noise significantly changing along with the time.
Figure 15 shows how locus O X and OY are affected by ground noise 1401.Different from the 14th figure, when power supply noise 1501 has a peak value or other change, level is switched reference value and is had a synchronous peak value or other change.Although this peak value or other change are switched reference value and power supply noise in this level, compare and have a less size, between the synchronizing characteristics of sequence circuit power supply 1501 and level switching reference value, reduced significantly the change of clock signal.Therefore, the output 1510 of this clock signal has and still has a common clock cycle moving compared with extent in the situation that at ground noise.
Figure 16 A and Figure 16 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, to switch the power supply of this clock.When electric power starting, if not yet reach stabilized power supply and need this VDD power supply to produce the clock to logical circuit.Logical circuit can be waited for the setup times of stabilized power supply.After reaching stabilized power supply, this clock switches to a stabilizing clock.
The sequence circuit 1602A and the 1602B that in accompanying drawing, show parallel placement, level commutation circuit 1604A and the 1604B of parallel placement, and a latch circuit 1606.Also comprise as shown in the figure sequential power supply and level and switch reference value generator 1616A and 1616B, it can produce the identical noise phase of power supply noise of the reference signal of detecting with the power supply noise of sequence circuit power supply and the level of sequence circuit output.In icon, also comprise the diverter switch 1620A between VDD and sequential power supply and level switching reference value generator 1616A, diverter switch 1620B between VDD and sequential power supply and level switching reference value generator 1616B, diverter switch 1620C between level commutation circuit 1604A and latch circuit 1606, and the diverter switch 1620D between level commutation circuit 1604B and latch circuit 1606.
In Figure 16 A, this condenser network CX or CY and couple.In Figure 16 B, this condenser network CX or CY and power supply 1616A or 1616B couple.
Figure 17 can apply the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 17 is the concise and to the point block schematic diagram of the integrated circuit 1700 that comprises a memory array 1712.One character line/block chooses decoder and driver 1714 is to be coupled to, and has electrical communication with it, and many character lines 1716 and character string are selected line, is therebetween to arrange along the column direction of memory cell array 1712.One bit line (OK) decoder 1718 is to be coupled to many bit lines 1720 of arranging along the row of memory array 1712, and has electrical communication with it, and with from reading out data, or data writing extremely, in the memory cell of memory cell array 1712.Address is to provide to character line and block selection decoder 1714 and bit line decoder 1718 by bus 1722.Induction amplifier in square 1724 and data input structure, comprise as reading, the current source of sequencing and erasing mode, is to be coupled to bit line decoder 1718 by bus 1726.Data is by the input/output end port on integrated circuit 1710, by data input line 1728, to be sent to the data input structure of square 1724.In this illustrative embodiment, other circuit 1730 is also included within this integrated circuit 1710, for example general object processor or special purpose circuit, or the composite module that storage array is supported is thus to provide system-on-a-chip function.Data is the induction amplifier in square 1724, by data output line 1732, is sent to input/output end port or the inner or outer data destination of other integrated circuit 1700 on integrated circuit 1700.State machine and improvement clock circuit (as discussed here) are in circuit 1734.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, and also comprises commutation circuit between with reference to generator and operational amplifier.As shown in Figure 8, switching transistor 818A is opened by signal ENX and switching transistor 818B is opened by signal ENY.Be similar to Fig. 8, the ground noise that switches generator 1616A and 1616B from sequential power supply and level is to be stored among capacitive node REFX or REFY.
Although the present invention is described with reference to embodiment, so the present invention's creation is not limited to its detailed description.Substitute mode and to revise pattern be to advise in previous description, and other substitute mode and modification pattern is thought the personage by haveing the knack of technique and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result in fact with the present invention, neither depart from spiritual category of the present invention.Therefore, all these substitute modes and to revise pattern be to be intended to drop among the category that the present invention defines in enclose claim scope and equipollent thereof.
Claims (15)
1. an integrated circuit (IC) apparatus, is characterized in that, comprises:
One integrated circuit of clock, comprises:
One sequence circuit, it has an output of switching between one first reference signal and one second reference signal, the time constant that the sequential that one speed of this switching is exported by a clock signal of this integrated circuit of clock determines decides, and this second reference signal comprises a mobility noise;
Sequential power supply and reference circuit, it has this mobility noise, this sequential power supply and reference circuit produce this second reference signal that contains this mobility noise of the first, this sequential power supply and reference circuit produce a level that contains this mobility noise of the second and switch reference signal, this the first mobility noise and this second mobility Noise Synchronization, so the change of this first mobility noise is synchronizeed with the change of this second mobility noise; And
One level commutation circuit, relatively one of this sequence circuit output is switched reference signal with this level, and an output of this level commutation circuit decides this clock signal output of this integrated circuit of clock.
2. device as claimed in claim 1, it is characterized in that, this sequential power supply and reference circuit have one first and export to this second reference signal, and have one second and export to this level and switch reference signal, and this mobility noise is coupled to a resistance between this first output and this second output via one and second exports and synchronize with this first output and this.
3. device as claimed in claim 1, it is characterized in that, this sequential power supply and reference circuit have one first and export to this second reference signal, and have one second and export to this level and switch reference signal, and this mobility noise is coupled to an electric capacity between this first output and this second output via one and second exports and synchronize with this first output and this.
4. device as claimed in claim 1, is characterized in that, also comprises: a plurality of diverter switches, and during for electric power starting, this level commutation circuit is removed and coupled.
5. device as claimed in claim 1, it is characterized in that, this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switch between this second reference voltage is discharged to the state of this first reference voltage.
6. device as claimed in claim 1, is characterized in that, this time constant is an exponential signal.
7. device as claimed in claim 1, is characterized in that, this integrated circuit of clock also comprises:
One latch circuit, this clock signal output that produces this integrated circuit of clock in response to this output of this level commutation circuit.
8. device as claimed in claim 1, is characterized in that, this integrated circuit of clock also comprises:
One level is switched reference circuit, in order to produce this level, switches reference signal, comprising:
One output, produces this level and switches reference signal;
One with temperature direct ratio current feedback circuit, to produce for the electric current that should export; And
One resistance, in abutting connection with this output.
9. device as claimed in claim 1, is characterized in that, this integrated circuit of clock also comprises:
One level is switched reference circuit, produces this level and switches reference signal, comprising:
One output, produces this level and switches reference signal;
One with temperature inverse ratio current feedback circuit, to produce for the electric current that should export; And
One resistance, in abutting connection with this output.
10. a method for clocking, is characterized in that, comprises:
Determine the sequential of an integrated circuit of clock, by a sequence circuit output is switched between one first reference signal and one second reference signal, a speed of this switching is that the time constant that this sequential by this integrated circuit of clock determines decides;
Produce the level switching reference signal that second reference signal and with the first mobility noise has the second mobility noise, this the first mobility noise and this second mobility Noise Synchronization, so the change of this first mobility noise is synchronizeed with the change of this second mobility noise; And
Relatively this sequence circuit output is switched reference signal with this level, to determine a clock signal output of this integrated circuit of clock.
11. methods as claimed in claim 10, is characterized in that, also comprise:
When electric power starting, this this synchronous mobility noise signal is removed and coupled, so this decision and this comparison step can't rely on this this synchronous mobility noise signal when electric power starting.
12. methods as claimed in claim 10, it is characterized in that, this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage and from this second reference voltage, is discharged between the state of this first reference voltage at this first reference voltage certainly and switches.
13. methods as claimed in claim 10, is characterized in that, this time constant is an exponential signal.
14. methods as claimed in claim 10, is characterized in that, also comprise:
In this relatively after, use a latch circuit to produce a clock signal output of this integrated circuit of clock.
15. 1 kinds of methods of manufacturing an integrated circuit (IC) apparatus, is characterized in that, comprise:
One integrated circuit of clock is provided, comprises:
One sequence circuit is provided, it has an output of switching between one first reference signal and one second reference signal, one speed of this switching is that the time constant that the sequential by a clock signal output of this integrated circuit of clock determines decides, and this second reference signal comprises a mobility noise signal;
Sequential power supply and reference circuit are provided, it has this mobility noise signal, this sequential power supply and reference circuit produce this second reference signal with the first mobility noise, this sequential power supply and reference circuit produce a level switching reference signal with the second mobility noise, this the first mobility noise and this second mobility Noise Synchronization, so the change of this first mobility noise is synchronizeed with the change of this second mobility noise; And
One level commutation circuit is provided, and relatively one of this sequence circuit reference circuit output is switched reference signal with this level, and an output of this level commutation circuit decides this clock signal output of this integrated circuit of clock.
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| CN201210114007.7A CN102664616B (en) | 2009-12-15 | 2009-12-15 | Integrated clock circuit |
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| CN201210114007.7A CN102664616B (en) | 2009-12-15 | 2009-12-15 | Integrated clock circuit |
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| CN200910260481A Division CN102098037B (en) | 2009-12-15 | 2009-12-15 | Clock circuit of integrated circuit |
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| CN102664616B true CN102664616B (en) | 2014-08-06 |
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| CN1482620A (en) * | 2002-07-12 | 2004-03-17 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
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| US7236061B2 (en) * | 2005-05-03 | 2007-06-26 | Macronix International Co., Ltd. | Temperature compensated refresh clock circuit for memory circuits |
| JP2007110495A (en) * | 2005-10-14 | 2007-04-26 | Matsushita Electric Ind Co Ltd | Clock signal generating circuit |
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