CN102098037B - Clock circuit of integrated circuit - Google Patents
Clock circuit of integrated circuit Download PDFInfo
- Publication number
- CN102098037B CN102098037B CN200910260481A CN200910260481A CN102098037B CN 102098037 B CN102098037 B CN 102098037B CN 200910260481 A CN200910260481 A CN 200910260481A CN 200910260481 A CN200910260481 A CN 200910260481A CN 102098037 B CN102098037 B CN 102098037B
- Authority
- CN
- China
- Prior art keywords
- circuit
- reference signal
- output
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The invention provides a clock circuit of an integrated circuit with temperature, grounding voltage or power supply voltage change bearing capacity. The improved clock integrated circuit can solve one or more changes of temperature, grounding voltage and power supply voltage changes in different embodiments.
Description
Technical field
The invention relates to integrated circuit, variations such as its tolerable such as temperature, ground noise, power supply noise with clock circuit.
Background technology
The running meeting of the clock circuit of integrated circuit has variation with factors such as temperature, ground noise, power supply noises.Because these variations can influence the final sequential of clock signal, the existing multinomial research phase of carrying out can be directed against this problem, under the situation that above-mentioned variation exists, produces clock signal uniformly.
For example, the United States Patent (USP) of Gaboury utilizes for the 7th, 142, No. 005 to increase has the initiatively mode of buffer circuit, independent bias circuit system and the bias circuit system of load, comes the influence of insulating power supply fluctuation to clock signal.In order to reach the influence of insulating power supply fluctuation to clock signal, the buffer circuit of these relative complex causes the significantly increase of chip area and cost.
Therefore cause the demand, hope can solve these variation problems, but adopts more uncomplicated structure and less cost.
Summary of the invention
The present invention provides a kind of technology with device of integrated circuit of clock.
This clock integrated circuit has a bolt lock device, produces the clock signal output of this integrated circuit of clock.This bolt lock device comprises the gate that couples alternately, and so the input of the output of this gate that couples alternately in this bolt lock device and this Different Logic door that couples alternately in this bolt lock device couples.
The output that this clock integrated circuit also has a sequential circuit and this bolt lock device couples; One output of this sequence circuit is switched between one first reference signal and one second reference signal, a speed of this switching be by one and the time constant of temperature correlation decide.The sequential of this this clock signal output of output decision of this sequence circuit.
This clock integrated circuit also has a negative circuit; Relatively one of this a sequence circuit output and a temperature-compensating reference value; So this sequential of this clock signal output of this integrated circuit of clock can be kept out temperature change, and an output of this negative circuit couples with an input of this bolt lock device.
In certain embodiments, this time constant is an exponential signal.
In certain embodiments; This first reference signal is one first reference voltage; This second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage and is discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switches.
In certain embodiments; This first reference signal is one first reference voltage; This second reference signal is one second reference voltage; And this sequence circuit, response be to this negative circuit, charges to the state of this second reference voltage and be discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch.Wherein this temperature-compensating trigger point of this negative circuit is one the 3rd reference voltage, and it increases and reduce along with temperature.In one embodiment, this temperature-compensating trigger point of this negative circuit is to be produced by a temperature-compensating power supply.
Another object of the present invention is that a kind of device with integrated circuit of clock is provided, and inverter is replaced with Schmidt trigger circuit.
Another purpose of the present invention is that a kind of device with integrated circuit of clock is provided, and inverter is replaced with operation amplifier circuit, and add the reference circuit of a current generator type, produces this temperature-compensating reference value.
In many various embodiment, the reference circuit of this current generator type is a current generator and a resistance characteristic device, comprise a resistance, diode and a metal-oxide semiconductor transistorized any; And some other device has CTAT (with the temperature inverse ratio) characteristic and PTAT (with the temperature direct ratio) characteristic device one of at least as one.
A purpose more of the present invention is that a kind of device with integrated circuit of clock is provided, and comprises the clock signal output that a bolt lock device produces this integrated circuit of clock.This bolt lock device comprises one first gate and one second gate couples each other alternately.One output of this first gate couples with one first input of this second gate.One output of this second gate couples with one first input of this first gate.One second input of this output of this second gate and this first gate couples via at least one first sequence circuit and one first inverter.One second input of this output of this first gate and this second gate couples via at least one second sequence circuit and one second inverter.
This first sequence circuit has an output and between one first reference signal and one second reference signal, switches with a first rate, this first rate be by one and the very first time constant of temperature correlation decide.
This second sequence circuit has an output and between this first reference signal and this second reference signal, switches with one second speed, this second speed be by one and one second time constant of temperature correlation decide.
The sequential of said this clock signal output of output decision of this first sequence circuit and this second sequence circuit.
This first inverter is an output and one first temperature-compensating reference value of this first sequence circuit relatively, and it is one first temperature-compensating trigger point of this first inverter.
This second inverter is an output and one second temperature-compensating reference value of this second sequence circuit relatively, and it is one second temperature-compensating trigger point of this second inverter.
In one embodiment; This first reference signal is one first reference voltage; This second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and are discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch.In one embodiment, said temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.
In one embodiment, this first and second time constant is an exponential signal.
In one embodiment, this first and second temperature-compensating reference value is to produce from a common reference circuit.
In one embodiment, this first and second temperature-compensating reference value is to produce from different reference circuits.
Another object of the present invention is that a kind of device with integrated circuit of clock is provided, and the array inverter is replaced with the array Schmidt trigger circuit.
Another object of the present invention is that a kind of device with integrated circuit of clock is provided, and the array inverter is replaced with the array operation amplifier circuit, and add the reference circuit of a current generator type, produces this temperature-compensating reference value.
Description of drawings
The present invention is defined by claim.These and other purpose, characteristic, and embodiment can be described by the collocation accompanying drawing in the chapters and sections of following execution mode, wherein:
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that for example is temperature, earthed voltage or power supply voltage variation ability to bear.
The circuit diagram that Fig. 2 A and Fig. 2 B demonstration one have the integrated circuit clock circuit of temperature change ability to bear; It comprises the output of a negative circuit with the assessment sequence circuit, wherein Fig. 2 A have the capacitive character sequence circuit with couple and Fig. 2 B has capacitive character sequence circuit and supply coupling.
Fig. 2 C shows to have the circuit diagram to the integrated circuit clock circuit of temperature change ability to bear, its and Fig. 2 category-A seemingly, but from PTAT power supply reception power supply rather than from the CTAT power supply.
The circuit diagram that Fig. 2 D demonstration one has the integrated circuit clock circuit of temperature change ability to bear, it comprises a Schmidt trigger circuit to assess the output of this sequential circuit.
Fig. 2 E shows the sketch map of a Schmidt trigger circuit, for example in Fig. 2 D.
The circuit diagram that Fig. 3 A and Fig. 3 B demonstration one have the integrated circuit clock circuit of temperature change ability to bear; It comprises an operation amplifier circuit to be carried out the accurate position detecting of sequence circuit output by an output relatively and a reference value, wherein Fig. 3 A have the capacitive character sequence circuit with couple and Fig. 3 B has capacitive character sequence circuit and supply coupling.
Fig. 4 A shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature.
Fig. 4 B shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the CTAT current source that increases electric current output along with the increase of temperature.
Fig. 4 C shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the PTAT current source that reduces electric current output along with the increase of temperature, and it is parallelly connected with the load resistance of a current mirror to have more a capacitor.
Fig. 4 D is the sketch map of a current feedback circuit, and it provides PTAT electric current according to reference circuit from the PMOS device.
Fig. 4 E is the sketch map of a current feedback circuit, and it provides PTAT electric current according to reference circuit from the NMOS device.
Fig. 4 F is the sketch map of a current feedback circuit, and it provides CTAT electric current according to reference circuit from the PMOS device.
Fig. 4 G is the sketch map of a current feedback circuit, and it provides CTAT electric current according to reference circuit from the NMOS device.
Fig. 5 A shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output that reduces along with the increase of temperature.
Fig. 5 B shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the current source that increases electric current output along with the increase of temperature, and the output that increases along with the increase of temperature.
Fig. 5 C shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature, and the output that increases along with the increase of temperature.
Fig. 5 D shows as the circuit diagram of the reference signal of the accurate position circuit for detecting of Fig. 5 C to have the current source that increases electric current output along with the increase of temperature but comprise one.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES524.
Fig. 6 A shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, and it produces the clock sequential and can change significantly along with the change of temperature.
Fig. 6 B shows the geometric locus of one group of time and rising magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces the clock sequential and does not change along with the change of temperature basically.
Fig. 7 A shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, and it produces the clock sequential and can change significantly along with the change of temperature.
Fig. 7 B shows the geometric locus of one group of time and decline magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces the clock sequential and does not change along with the change of temperature basically.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram to the integrated circuit clock circuit of ground noise change ability to bear; It comprises a transistor and optionally couples with ground noise; With a part as the reference signal of the accurate position detecting of this sequential circuit output, wherein Fig. 8 A have the capacitive character sequence circuit with couple and Fig. 8 B has capacitive character sequence circuit and supply coupling.
Fig. 9 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the ground noise change, and it produces the clock sequential can be to changing along with the ground noise of time change significantly.
Figure 10 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the ground noise change, and it can produce metastable clock sequential because of the circuit among Fig. 8 in to the ground noise that changes along with the time.
Figure 11 A and Figure 11 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear; It comprises the noise phase of power supply noise shared in common of reference signal of accurate position detecting of power supply noise and the sequential circuit output of a transistor AND gate sequence circuit power supply, wherein Figure 11 A have the capacitive character sequence circuit with couple and Figure 11 B has capacitive character sequence circuit and supply coupling.
Figure 12 shows the circuit diagram of a power circuit, and its power supply noise with the reference signal that the accurate position that the power supply noise and the sequential circuit of sequence circuit power supply are exported is detected is shared identical noise phase.
Figure 13 is one group of voltage and time relation figure, and it shows because like the circuit relationships among Figure 11 or Figure 12, how between sequence circuit power supply and accurate the reference signal of detecting that is used in sequence circuit output, has identical noise phase.
Figure 14 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the power supply noise change, and it can produce the clock sequential in to the power supply noise that significantly changes along with the time.
Figure 15 is one group of voltage and time relation figure; It shows that this clock circuit is the ability to bear that how to have the power supply noise change, and it can produce metastable clock sequential because of the circuit among Figure 11 and Figure 12 in to the power supply noise that significantly changes along with the time.
Figure 16 A and Figure 16 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear; It comprises the noise phase of the power supply noise shared in common of the power supply noise of a transistor AND gate sequence circuit power supply and accurate the reference signal of detecting that the sequential circuit is exported; Similar with Figure 11; And increased commutation circuit, for example when electric power starting, tolerated circuit optionally to walk around this noise.
Figure 17 can use the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, and also comprises commutation circuit between with reference to generator and operational amplifier.
Embodiment
Fig. 1 shows that one has the block schematic diagram of the integrated circuit clock circuit that for example is temperature, earthed voltage or power supply voltage variation ability to bear.
This integrated circuit clock circuit is a loop structure normally, has sequence circuit 102, accurate position commutation circuit 104 and latch circuit latch circuit 106.This latch circuit latch circuit 106 produces a feedback signal from latch circuit latch circuit 106 to sequence circuit 102, and a clock output signal 110.This sequential circuit 102 switches between two reference signals according to a time constant.Therefore this time constant has determined the sequential of this integrated circuit clock circuit.A typical time constant example is an exponential time constant, and it is with a RC circuit or the rising of RL circuit and characterization fall time.The output of this accurate position commutation circuit monitoring sequence circuit 102, and change its output according to this sequential circuit 102 is whether enough high or low.The example of latch circuit 106 is SR bolt lock device, SR NAND bolt lock device, JK bolt lock device, gate-type SR bolt lock device, gate-type D bolt lock device, gate-type triggering bolt lock device etc.This latch circuit circuit 106 has two stable states and between these two stable states, switches to produce a clock output signal 110.
Two reference signals that sequence circuit 102 is relied on are by 116 generations of circuit, and it also can produce the accurate position switching reference signal that accurate position commutation circuit 104 is relied on.By producing the reference signal that is relied on for sequence circuit 102 simultaneously and the commutation circuit 104 that is as the criterion produces the accurate position that is relied on and switches reference signal, circuit 116 can be reduced to the noise phase that the noise signal that reference signal shares is switched in accurate position that the reference signal that sequence circuit 102 relied on and the commutation circuit 104 that is as the criterion relied on.Because any noise phase is very little, peak value and the valley that this sequential circuit 102 relies on the noise signal in the reference signal is that to rely on the peak value and the valley of the noise signal in the accurate position switching reference signal synchronous with accurate position commutation circuit 104.
Though calcspar shown here can solve the change problem of temperature, earthed voltage or supply voltage; But one in different embodiments of the invention improvement clock circuit only solve these variable parameters one of them that is all (for example: only to temperature noise, only to the earthed voltage noise or only to the supply voltage noise), or these variable parameters wherein two that is all (for example: only to temperature and supply voltage noise, only to temperature and earthed voltage noise or only be directed against supply voltage and earthed voltage noise).
The circuit diagram that Fig. 2 A and Fig. 2 B demonstration one have the integrated circuit clock circuit of temperature change ability to bear, it comprises the output of a negative circuit with the assessment sequence circuit.
The sequence circuit 202A and the 202B that show parallel placement in the accompanying drawing, the negative circuit 204A of parallel placement and 204B, and a latch circuit 206.This sequential circuit 202A and 202B normally one have resistance R X or a RY inverter, self-capacitance CX or CY carry out charge or discharge, to change the output voltage of OX or OY.
Figure 2A shows an embodiment wherein the capacitance CX or CY is coupled with Shu common ground.Though do not show all possible variation in the accompanying drawing clearly, technology of the present invention comprises the sequence circuit that has capacitor C X or CY among all embodiment, wherein sequence circuit can be revised as capacitor C X or CY are coupled with a common ground connection.
In one embodiment, capacitor C X or CY are actually common ground end that a PMOS transistor has opposite end points and inverter and remove and to couple.
Figure 2B shows an embodiment wherein the capacitance CX or CY Shu together with the power coupled thereto.Though do not show all possible variation in the accompanying drawing clearly, technology of the present invention comprises the sequence circuit that has capacitor C X or CY among all embodiment, wherein sequence circuit can be revised as and with capacitor C X or CY be and a common supply coupling.
In one embodiment, capacitor C X or CY are actually common power source end that a PMOS transistor has opposite end points and inverter and remove and to couple.
This negative circuit 204A and 204B are by a CTAT power supply or one and the power supply that is inversely proportional to of temperature, and it can reduce along with the increase of temperature, drives.
This inverter is very different with the operational amplifier version.In the operational amplifier version, the output of a Vref and sequence circuit (like the rising/decline of RC circuit) compares.And in the inverter version, the power supply of this inverter is a Be Controlled, with stroke that changes this inverter and the output (like the rising/decline of RC circuit) of therefore detecting sequence circuit.In this inverter version, an extra temperature relation about power supply and inverter stroke comes into one's own.
This inverter has following advantage compared to the operational amplifier version: the operating voltage VDD that (1) is lower; (2) less circuit size (two metal-oxide semiconductor transistors are only arranged inverter and operational amplifier has five or above metal-oxide semiconductor transistor); (3) better simply design; (4) lower active electric current (inverter has a current path, and operational amplifier has two or three current paths and comprises an extra current mirror); And (5) higher operating rate (inverter has the delay in a stage, and operational amplifier has the delay of two or three phases).
This latch circuit 206 couples alternately, and the output of a gate like this and the input of another gate couple.One input of one gate is that the output of direct and another gate couples, and another input of this gate is that the output of direct and another gate couples with an accurate circuit for detecting through sequence circuit.
Another embodiment of Fig. 2 C display timing generator circuit.Though major part and Fig. 2 category-A are seemingly, the sequence circuit 202A of parallel placement in Fig. 2 C and 202B are the power supplys that is directly proportional with temperature by a PTAT power supply or, and it can increase along with the increase of temperature, drives.Though do not show all possible variation in the accompanying drawing clearly, technology of the present invention comprises the sequence circuit that has the CTAT power supply among all embodiment, wherein the CTAT power supply can be replaced by the PTAT power supply.
Similarly, though do not show all possible variation in the accompanying drawing clearly, technology of the present invention comprises the sequence circuit that has the PTAT power supply among all embodiment, and wherein the PTAT power supply can be replaced by the CTAT power supply.
The circuit diagram that Fig. 2 D demonstration one has the integrated circuit clock circuit of temperature change ability to bear, it comprises a Schmidt trigger circuit to assess the output of this sequential circuit.
Though Fig. 2 category-B seemingly, accurate position commutation circuit 210A in Fig. 2 D and the Schmidt trigger circuit of 210B are to be driven by a CTAT power supply, and comprise the operational amplifier that has through the loop positive feedback of resistance.
Fig. 2 E shows the sketch map of a Schmidt trigger circuit.
Fig. 3 shows that one has the circuit diagram to the integrated circuit clock circuit of temperature change ability to bear, and it comprises an operation amplifier circuit to be carried out the accurate position detecting of sequence circuit output by an output relatively and a reference value.
The sequence circuit 302A and the 302B that show parallel placement in the accompanying drawing, the accurate position commutation circuit 304A and the 304B of parallel placement, and a latch circuit 306.This accurate position commutation circuit 304A and 304B are that a computing amplifier comparator has a reference voltage CTAT_REF.Except that this, this clock circuit roughly with Fig. 2 category-A seemingly.
Fig. 4 A shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the current source that increases electric current output along with the increase of temperature.
Fig. 4 A demonstrates the CTAT power supply signal that relies on accurate position circuit for detecting and how to produce, and in this figure, is shown as CTAT_REF 428.A PTAT_I current source 426 of quantitatively exporting can increase along with the increase of temperature from power regulator 422 electric current that 424 generations are directly proportional with temperature through resistance R ES.This power regulator 422 can be exported the temperature independent voltage of deciding.This regulates power supply certain power supply and can be along with VDD and temperature change is provided.For example, the output of this adjuster has one and can be with reference value.This output result and temperature are inversely proportional to, and also be to increase because temperature is crossed over the pressure drop of this resistance when increasing, and the skew of the exit point of this pressure drop lower end then are minimizings.An example of this current source is shown in Fig. 4 E.
Fig. 4 B is a variation of Fig. 4 A circuit; Wherein PTAT_I constant current source 426 is by 430 replacements of CTAT_I constant current source, and the CTAT_REF428 of CTAT power supply signal that relies on accurate position circuit for detecting is by 432 replacements of PTAT_REF of the PTAT power supply signal that relies on accurate position circuit for detecting.An example of this current source is shown in Fig. 4 G.
Fig. 4 C is a variation of Fig. 4 A circuit, and it is parallelly connected with resistance R ES 424 to have a bypass capacitor 434, to reduce noise.In addition, this current source comprises a current mirror.An example of this current source is shown in Fig. 4 D.
Fig. 4 D is the sketch map of a current feedback circuit, and it provides PTAT electric current according to reference circuit from the PMOS device.
Fig. 4 E is the sketch map of a current feedback circuit, and it provides PTAT electric current according to reference circuit from the NMOS device.
In Fig. 4 D and Fig. 4 E, this circuit uses between two delta_Vg with same current nmos pass transistor of the temperature of being proportional to.So delta_Vg/ resistance=PTAT_I.In Fig. 4 D and Fig. 4 E, two transistors with circle are identical.
Fig. 4 F is the sketch map of a current feedback circuit, and it provides CTAT electric current according to reference circuit from the PMOS device.
Fig. 4 G is the sketch map of a current feedback circuit, and it provides CTAT electric current according to reference circuit from the NMOS device.
Current feedback circuit according to reference circuit described herein is preferably, because in many examples, the parameter of single and temperature correlation can Be Controlled, rather than two material relevant parameters with temperature correlation, and it has the different temperature relevance.
Fig. 5 A shows the circuit diagram of the reference signal of accurate position circuit for detecting, and it comprises one and has the current source that reduces electric current output along with the increase of temperature.
Fig. 5 A demonstrates the CTAT power supply signal that relies on accurate position circuit for detecting and how to produce, and in this figure, is shown as CTAT_REF 528.The quantitative PTAT_I current source 526 of output can reduce along with the increase of temperature from power regulator 522 through the electric current that resistance R ES 524 generations and temperature are inversely proportional to.This output result and temperature are inversely proportional to, and also be to reduce because temperature is crossed over the pressure drop of this resistance when increasing, and the skew of the exit point of this pressure drop upper end also are minimizings.
Shown in of current source be illustrated as one and repeatedly connect current source.
Fig. 5 B, Fig. 5 C, Fig. 5 D and Fig. 5 E are other examples that produces reference voltage signal.
Fig. 5 B is a variation of Fig. 5 A circuit; Wherein CTAT_I constant current source 526 is by 530 replacements of PTAT_I constant current source, and the CTAT_REF528 of CTAT power supply signal that relies on accurate position circuit for detecting is by 532 replacements of PTAT_REF of the PTAT power supply signal that relies on accurate position circuit for detecting.
Fig. 5 C is a variation of Fig. 5 A circuit, and wherein resistance R ES 524 is by 530 replacements of diode DIO.An example of this current source is shown in Fig. 4 F.
Fig. 5 D is a variation of Fig. 5 A circuit, and wherein CTAT_I constant current source 526 is by 530 replacements of PTAT_I constant current source, and the skew of exit point moves to the pressure drop of crossing over this constant current source lower end from the pressure drop of crossing over this constant current source upper end.
Fig. 5 E is a variation of Fig. 5 C circuit, and wherein CTAT_I constant current source 526 is replaced by resistance R ES524.
Fig. 6 A shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, and it produces the clock sequential and can change significantly along with the change of temperature.
Fig. 6 A shows between the track region of a high temperature, a low temperature and a moderate temperature.Temperature is low more, and then this sequential circuit becomes fast more, and temperature is high more, and then this sequential circuit becomes slow more.Because the common reference signal of sequence circuit, this sequential circuit can arrive at reference value sooner when high temperature when low temperature.Therefore, the sequential of this clock circuit can be faster when high temperature when low temperature.
Fig. 6 B shows the geometric locus of one group of time and magnitude relationship, and it shows this clock circuit is how to have the temperature change ability to bear, because use Fig. 2 to the circuit shown in Fig. 5, it produces the clock sequential and does not change along with the change of temperature basically.
Fig. 6 B shows between the track region of a high temperature, a low temperature and a moderate temperature.Shown in Fig. 6 A, temperature is low more, and then this sequential circuit becomes fast more, and temperature is high more, and then this sequential circuit becomes slow more.Yet, because use different sequence circuits among Fig. 6 B, be with Fig. 6 A in employed sequence circuit different.Though sequence circuit can arrive at reference value sooner when high temperature when low temperature, also relative higher of the reference value of this sequential circuit.Therefore, the sequential of this clock circuit demonstrates very little temperature change, but causes the speed fluctuation of this clock circuit.
Fig. 7 A and Fig. 7 B are other embodiment, and it shows the rising signals among dropping signal rather than Fig. 6 A and Fig. 6 B, but still show identical time constant.
One clock signal is rising signals or the dropping signal among Fig. 7 A and Fig. 7 B among dependency graph 6A and Fig. 6 B, be according to capacitor C X or CY be with Fig. 2 A in ground couple or decide with the supply coupling among Fig. 2 B.
Fig. 8 A and Fig. 8 B show that one has the circuit diagram to the integrated circuit clock circuit of ground noise change ability to bear; It comprises a transistor and optionally couples with ground noise, with the part as the reference signal of the accurate position detecting of this sequential circuit output.
The sequence circuit 802A and the 802B that show parallel placement in the accompanying drawing, the accurate position commutation circuit 804A and the 804B of parallel placement, and a latch circuit 806.This accurate position commutation circuit 804A and 804B optionally couple with the ground noise that comes the autocollimatic position to switch reference circuit 816A and 816B; And being stored in capacitive node REF X or REF is Y, is that the switching behavior of the switching transistor 818B that opened according to the switching transistor 818A that is opened by signal ENX and by signal ENY separately determines.This can maintain ground noise as a sampling, so identical ground noise can be maintained by sequence circuit 802A or 802B, and the node R EF X or the REF Y of the accurate position switching reference circuit that can be relied on by accurate position commutation circuit 104 maintain.
In one embodiment, capacitor C X or CY are actually a PMOS transistor to have opposite end points and removes with common power end and couple, and this common power source is connected with RX or RY.
OX keeps ground connection when ENX is high levle.Afterwards, ENX becomes low level and then closes NMOS; Ground noise is maintained at OX at this moment.If it is very fast that noise is a then precharge speed of high levle; If it is very slow that noise is a then precharge speed of low level.This circuit makes REFX or REFY keep identical ground noise in the identical time.
In Fig. 8 A, this switches reference circuit reference node REFX or REFY, comprise condenser network with couple.In Fig. 8 B, this switches reference circuit reference node REFX or REFY, comprises condenser network and supply coupling.
In various embodiment, reference circuit 816A and 816B are switched in accurate position, and can be two groups of different circuits or same group of circuit be shared with 804B by the sequence circuit and multiple accurate the commutation circuit 804A of parallel placement.
Fig. 9 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the ground noise change, and it produces the clock sequential can be to changing along with the ground noise of time change significantly.
Fig. 9 shows that locus O X and OY are how by ground noise, are influenced for the REF_LO signal in this figure.When ground noise had a peak value, then this sequential circuit can begin to charge to from REF_LO the program of REF_HI, caused sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Therefore, the output 910 of this clock signal has a wider change in this clock in the cycle.
When ENX was high levle, OX kept ground connection and voltage to change along with ground noise.When ENX is a low level, and close NMOS, then ground noise is maintained at OX.But still change along with ground noise with reference to accurate position.The worst situation be OX keep the ground noise of a high levle and between charge period this reference circuit bear the accurate position of a negative ground connection; Then this reference value can be low far beyond being contemplated to.So Shu similar sampling and holding structure in REFX or REFY keep the same ground noise.
Figure 10 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the ground noise change, and it can produce metastable clock sequential because of the circuit among Fig. 8 in to the ground noise that changes along with the time.
Figure 10 shows that locus O X and OY are how by ground noise, are influenced for the REF_LO signal in this figure.When ground noise had a peak value or other change, then this peak value or other change can be stored in the capacitive node REF X among Fig. 8 or REF is Y.Because ground noise keeps reference circuit to follow the trail of the influence of REF_LO signal by the sampling back, this accurate position circuit for detecting is the autocollimatic position detecting reference circuit ground noise more identical with sequence circuit.After the mode that ground noise is kept by the back of taking a sample with this, ground noise, it can continue to change, and removes coupling since then in the sample circuit.Therefore, this sequential circuit charges in the program of REF_HI not one from REF_LO to begin in advance, though ground noise is arranged, this sequential circuit still needs the identical time charge to REF_HI from REF_LO.Therefore, cause this clock signal output 910 under an extensive ground noise that changes, still to have the identical clock cycle.
In another embodiment, be when discharge, this ground noise and sample circuit releasing to be coupled again after ground noise is taken a sample, rather than when charging, this ground noise and sample circuit releasing are coupled shown in Fig. 9 and Figure 10.This embodiment can cause additional problems because must solve the power supply noise problem that the self noise power regulator is produced.
(similar Fig. 2 C) in another embodiment, this sampling and holding circuit can keep power supply noise rather than ground noise.
Figure 11 A and Figure 11 B demonstration one have the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, and it comprises the noise phase of the power supply noise shared in common of the power supply noise of a transistor AND gate sequence circuit power supply and accurate the reference signal of detecting that the sequential circuit is exported.
The sequence circuit 1102A and the 1102B that show parallel placement in the accompanying drawing, the accurate position commutation circuit 1104A and the 1104B of parallel placement, and a latch circuit 1106.Sequential power supply and accurate position switching reference value generator 1116A and the 1116B of also comprising as shown in the figure, it can produce the identical noise phase of power supply noise of the reference signal of the accurate position detecting of exporting with the power supply noise and the sequential circuit of sequence circuit power supply.
In Figure 11 A, this condenser network CX or CY and couple.In Figure 11 B, this condenser network CX or CY and power supply 1116A or 1116B couple.
Figure 12 shows the circuit diagram of a power circuit, and its power supply noise with the reference signal that the accurate position that the power supply noise and the sequential circuit of sequence circuit power supply are exported is detected is shared identical noise phase.
Figure 12 shows that a power supply 1236 drives an operational amplifier 1232.This operational amplifier has a reference signal REF_OP 1234 in its noninverting input.One of this REF_OP 1234 is illustrated as an energy gap reference circuit in 1.3V.The output that one metal oxide semiconductor field effect answers transistor 1238 to have a gate and operational amplifier 1232 couples, and a drain and power supply 1236 couple, and reaches one source pole and sequential power supply output 1246 and couples.Sequential power supply output 1246 is separated by resistance R 1 1240 with accurate position switching reference value 1248.The negative feedback point of reference value 1248 and operational amplifier 1232 is switched by resistance R 2 1242 separations in accurate position.At last, resistance R 3 with this negative feedback point with couple.
The capacitive coupling that another embodiment then uses the suspension joint node is switched identical noise phase between the reference value 1248 to keep sequential power supply output 1246 with accurate position, and wherein sequential power supply output 1246 is suspension joint with one of accurate position switching reference value 1248.
Though the above embodiments are that especially identical noise phase designs between sequential power supply output 1246 and the accurate position switching reference value 1248 in order to keep, and then are not like this in other the design.Sequential power supply output 1246 and accurate position are switched between the reference value 1248 for one of following reason or many persons and had different noise phase in other the design: (1) makes reference circuit and keeps clear of sequence circuit because of the configuration of crystal grain; (2) to have than the VDD power supply be good power supply supply refusal ratio (PSRR) to the reference circuit in the adjuster; Reach (3) even the RC power supply has power regulator, because different output loadings and transformation, a noise phase difference still can be kept, and this power regulator must support big electric current and bigger output to change.
Figure 13 is one group of voltage and time relation figure, and it shows because like the circuit relationships among Figure 11 or Figure 12, how between sequence circuit power supply and accurate the reference signal of detecting that is used in sequence circuit output, has identical noise phase.
The sequence circuit power supply 1301 that Figure 13 shows and be used in that both power supply noises have identical noise phase between the reference signal of accurate position detecting of sequence circuit output 1302.With track 1303 be positioned over track 1301 and 1302 on can show this situation, though the size of power supply noise changes, and the peak value of the power supply noise of track 1301 and 1302 and valley are synchronous.
Figure 14 is one group of voltage and time relation figure, and it shows that this clock circuit is the ability to bear that how to have the power supply noise change, and it can produce the clock sequential in to the power supply noise that significantly changes along with the time.
Figure 14 shows how locus O X and OY are influenced by power supply noise 1401.When power supply noise had one to decline to a great extent, then this sequential circuit can begin to charge to from REF_LO the program of REF_HI, caused sequence circuit only to need the less time just can charge to REF_HI from REF_LO.Similarly, when power supply noise had a peak value, then this sequential circuit can become slower from the program that REF_LO charges to REF_HI, caused sequence circuit to need more time just can charge to REF_HI from REF_LO.These changes are after reference value is switched in the accurate position of one stable (definite value), to take place.Therefore, the output 1410 of this clock signal has a wider change in this clock in the cycle.
Figure 15 is one group of voltage and time relation figure; It shows that this clock circuit is the ability to bear that how to have the power supply noise change, and it can produce metastable clock sequential because of the circuit among Figure 11 and Figure 12 in to the power supply noise that significantly changes along with the time.
Figure 15 shows how locus O X and OY are influenced by ground noise 1401.With the 14th figure is different is, when power supply noise 1501 had a peak value or other change, then accurate position was switched reference value and is had a synchronous peak value or other change.Compare with power supply noise and have a less size though reference value is switched in this peak value or other change in this accurate position, reduced the change of clock signal between the sequence circuit power supply 1501 and the synchronizing characteristics of accurate switching reference value significantly.Therefore, the output 1510 of this clock signal has at ground noise and still has under the situation moving than extent common clock cycle.
Figure 16 A and Figure 16 B show that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, to switch the power supply of this clock.When electric power starting, if do not reach stabilized power supply as yet and need this VDD power supply to produce the clock of giving logical circuit.Logical circuit can be waited for the time that is provided with of stabilized power supply.After reaching stabilized power supply, then this clock switches to a stabilizing clock.
The sequence circuit 1602A and the 1602B that show parallel placement in the accompanying drawing, the accurate position commutation circuit 1604A and the 1604B of parallel placement, and a latch circuit 1606.Sequential power supply and accurate position switching reference value generator 1616A and the 1616B of also comprising as shown in the figure, it can produce the identical noise phase of power supply noise of the reference signal of the accurate position detecting of exporting with the power supply noise and the sequential circuit of sequence circuit power supply.Also comprise the diverter switch 1620A between VDD and sequential power supply and accurate position switching reference value generator 1616A in the icon; Diverter switch 1620B between VDD and sequential power supply and accurate position switching reference value generator 1616B; Diverter switch 1620C between accurate position commutation circuit 1604A and latch circuit 1606, and the diverter switch 1620D between accurate position commutation circuit 1604B and latch circuit 1606.
In Figure 16 A, this condenser network CX or CY and couple.In Figure 16 B, this condenser network CX or CY and power supply 1616A or 1616B couple.
Figure 17 can use the block schematic diagram that the present invention has a memory circuit of improvement integrated circuit clock circuit.
Figure 17 is the concise and to the point block schematic diagram that comprises the integrated circuit 1700 of a memory array 1712.One character line/block chooses decoder and driver 1714 is to be coupled to, and with it electrical communication is arranged, and many character lines 1716 and character string selection wire are to arrange along the column direction of memory cell array 1712 therebetween.One bit line (OK) decoder 1718 is to be coupled to many bit lines of arranging along the row of memory array 1,712 1720, and with it electrical communication is arranged, and with from reading of data, or writes data extremely, in the memory cell of memory cell array 1712.The address is to provide to character line and block selection decoder 1714 and bit line decoder 1718 through bus 1722.Induction amplifier in the square 1724 and data input structure, comprise as read, the current source of sequencing and erasing mode, be to be coupled to bit line decoder 1718 through bus 1726.Data is the data input structure that is sent to square 1724 by the input/output end port on the integrated circuit 1710 through data input line 1728.In this illustrative embodiment, other circuit 1730 is also included within this integrated circuit 1710, for example general purpose processor or special purpose circuit, or the composite module supported of storage array is to provide the system-on-a-chip function thus.Data is by the induction amplifier in the square 1724, through data output line 1732, is sent to input/output end port or other integrated circuit 1700 interior or outer data destinations on the integrated circuit 1700.State machine and improvement clock circuit (so discuss in the place) are in circuit 1734.
Figure 18 is a circuit diagram, and it is similar to Figure 16, shows that one has the circuit diagram to the integrated circuit clock circuit of power supply noise change ability to bear, and also comprises commutation circuit between with reference to generator and operational amplifier.As shown in Figure 8, switching transistor 818A is opened by signal ENX and switching transistor 818B is opened by signal ENY.Being similar to Fig. 8, is to be stored among capacitive node REFX or the REFY from the ground noise of sequential power supply and accurate position switching generator 1616A and 1616B.
Though the present invention describes with reference to embodiment, right the present invention's creation is not subject to its detailed description.Substitute mode and to revise pattern be in previous description, advise, and other substitute mode and modification pattern will be thought by the personage who has the knack of this technology to reach.Particularly, all have and are same as member of the present invention in fact and combine and reach the identical result in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and to revise pattern be to be intended to drop on the present invention among enclose claim scope and category that equipollent defined thereof.
Claims (14)
1. IC apparatus comprises:
One clock integrated circuit comprises:
One first reference signal, it comprises a mobility noise;
One sequential circuit; It has an output of between this first reference signal and one second reference signal, switching; One speed of this switching is to determine the time constant of a clock signal output timing of this integrated circuit of clock to decide by one; Wherein this output of this sequence circuit changes when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly in the output of this sequence circuit, can store the value of contained this mobility noise in this first reference signal;
One reference circuit; It has an output; This mobility noise optionally is coupled; Make this output of this reference circuit, change when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly, store the value of this mobility noise in this output of this sequence circuit; And
Surely position commutation circuit, in order to this output of this reference circuit relatively and this output of this sequence circuit, so should standard position commutation circuit one export and decide this clock signal of this integrated circuit of clock to export.
2. IC apparatus as claimed in claim 1; Wherein this sequence circuit optionally receives this mobility noise that is contained in this first reference signal, be this output according to this sequence circuit be (1) certainly this second reference signal drop to this first reference signal state or (2) certainly this first reference signal rise to the state of this second reference signal.
3. IC apparatus as claimed in claim 1; Wherein the output of this reference circuit under coupling with this mobility noise be corresponding to this sequence circuit when this second reference signal drops to this first reference signal, and this reference circuit in this mobility noise remove output under coupling be corresponding to this sequence circuit when this first reference signal rises to this second reference signal.
4. IC apparatus as claimed in claim 1, wherein this time constant is an exponential signal.
5. IC apparatus as claimed in claim 1; Wherein this standard position commutation circuit relatively this reference circuit in the output that comprises under this stored mobility noise level; With this sequence circuit in the output that comprises under this stored mobility noise level, to determine this clock signal output of this integrated circuit of clock.
6. IC apparatus as claimed in claim 1; Wherein this sequence circuit is configured to couple this first reference signal to this sequence circuit; And with this second reference signal this sequence circuit that dissociates; Wherein this first reference signal has this mobility noise, so makes this sequence circuit be discharged to this first reference signal from this second reference signal;
Wherein this sequence circuit is configured to this first reference signal this sequence circuit that dissociates; And this second reference signal is coupled to this sequence circuit; Wherein this first reference signal has this mobility noise, so makes this sequence circuit charge to this second reference signal from this first reference signal; And
Wherein this sequence circuit is configured in this output of this sequence circuit when (1) this second reference signal drops to this first reference signal and changes to (2) this first reference signal rises to this second reference signal certainly certainly, store the value of this mobility noise.
7. IC apparatus as claimed in claim 1, wherein this integrated circuit of clock also comprises:
One latch circuit, in order to responding the output of this standard position commutation circuit, and this clock signal output that produces this integrated circuit of clock.
8. the method for a clocking comprises:
Determine the sequential of a clock integrated circuit; This decision process is to realize through an output of a sequential circuit is switched between one first reference signal and one second reference signal; One speed of this switching is that the time constant that this sequential determined by this integrated circuit of clock decides; Wherein one of this sequence circuit output changes when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly in the output of this sequence circuit, can store the value of a mobility noise contained in this first reference signal;
This mobility noise optionally is coupled; Make an output of a reference circuit; Change when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly in this output of this sequence circuit, store the value of this mobility noise; And
Relatively this reference circuit output and this sequence circuit output is to determine the clock signal output of this integrated circuit of clock.
9. the method for clocking as claimed in claim 8, wherein this time constant is an exponential signal.
10. the method for clocking as claimed in claim 8, wherein this comparison step comprises:
Relatively this reference circuit is in the output that comprises under this stored mobility noise level, with this sequence circuit in the output that comprises under this stored mobility noise level, to determine this clock signal output of this integrated circuit of clock.
11. the method for clocking as claimed in claim 8, wherein the step of this this sequential of decision comprises:
Couple this first reference signal to this sequence circuit, and this sequence circuit and this second reference signal are dissociated certainly, wherein this first reference signal has this mobility noise signal, makes this sequence circuit drop to this first reference signal from this second reference signal; And
Dissociate from this first reference signal, and this sequence circuit and this second reference signal are coupled, wherein this first reference signal has this mobility noise signal, makes this sequence circuit rise to this second reference signal from this first reference signal.
12. the method for clocking as claimed in claim 8, wherein this step that optionally is coupled comprises:
For respond this (1) certainly this second reference signal drop to this first reference signal, the output of this reference circuit is coupled with this mobility noise signal; And
For respond these (2) certainly this first reference signal rise to this second reference signal, and this mobility noise signal is dissociated from the output of this reference circuit certainly, comprising:
When this output of this sequence circuit change from (1) certainly this second reference voltage drop to this first reference voltage to (2) certainly this first reference voltage rise to this second reference voltage, the value that stores this mobility noise signal is in this sequence circuit.
13. the method for clocking as claimed in claim 8, wherein this comparison step comprises:
Relatively after the output of this reference circuit and this sequence circuit output, use this clock signal output that produces this integrated circuit of clock with latch circuit in this.
14. a method of making each said IC apparatus in the claim 1 to 7 comprises:
One clock integrated circuit is provided, comprises:
One first reference signal is provided, and it comprises a mobility noise signal;
One sequential circuit is provided; It has an output of between this first reference signal and one second reference signal, switching; One speed of this switching is to determine the time constant of a clock signal output timing of this integrated circuit of clock to decide by one; Wherein this output of this sequence circuit changes when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly in the output of this sequence circuit, can store the value of contained this mobility noise in this first reference signal;
One reference circuit is provided; It has an output; This mobility noise optionally is coupled; Make this output of this reference circuit, change when (1) this second reference signal drops to this first reference signal and (2) this first reference signal rises between this second reference signal certainly certainly, store the value of this mobility noise in this output of this sequence circuit; And
Surely position commutation circuit is provided, and in order to relatively this output of this reference circuit and this output of this sequence circuit, so an output of this standard position commutation circuit decides this clock signal of this integrated circuit of clock to export.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910260481A CN102098037B (en) | 2009-12-15 | 2009-12-15 | Clock circuit of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910260481A CN102098037B (en) | 2009-12-15 | 2009-12-15 | Clock circuit of integrated circuit |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210113997.2A Division CN102664615B (en) | 2009-12-15 | 2009-12-15 | Clock circuit of integrated circuit |
| CN201210114007.7A Division CN102664616B (en) | 2009-12-15 | 2009-12-15 | Integrated clock circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102098037A CN102098037A (en) | 2011-06-15 |
| CN102098037B true CN102098037B (en) | 2012-09-05 |
Family
ID=44130929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910260481A Active CN102098037B (en) | 2009-12-15 | 2009-12-15 | Clock circuit of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102098037B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078607B (en) * | 2011-10-25 | 2015-02-18 | 旺宏电子股份有限公司 | Clock integrated circuit |
| CN104916309B (en) * | 2014-03-13 | 2019-04-23 | 中国科学院微电子研究所 | Sub-threshold SRAM memory cell |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1127447A (en) * | 1994-09-15 | 1996-07-24 | Lg情报通信株式会社 | A method and circuit for controlling digital processing piiase-locked loop for network synchronization |
| TW364077B (en) * | 1996-09-30 | 1999-07-11 | Intel Corp | An oscillator based tamperproof precision timing circuit |
| CN1482620A (en) * | 2002-07-12 | 2004-03-17 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
| US7459952B2 (en) * | 2005-10-14 | 2008-12-02 | Panasonic Corporation | Clock signal generating device, generating method, and signal processing device |
-
2009
- 2009-12-15 CN CN200910260481A patent/CN102098037B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1127447A (en) * | 1994-09-15 | 1996-07-24 | Lg情报通信株式会社 | A method and circuit for controlling digital processing piiase-locked loop for network synchronization |
| TW364077B (en) * | 1996-09-30 | 1999-07-11 | Intel Corp | An oscillator based tamperproof precision timing circuit |
| CN1482620A (en) * | 2002-07-12 | 2004-03-17 | 旺宏电子股份有限公司 | Clock generator for memory apparatus |
| US7459952B2 (en) * | 2005-10-14 | 2008-12-02 | Panasonic Corporation | Clock signal generating device, generating method, and signal processing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102098037A (en) | 2011-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100293637B1 (en) | Drain Voltage Pumping Circuit | |
| US8217698B2 (en) | Clock integrated circuit | |
| US6107836A (en) | Semiconductor integrated circuit device having power reduction mechanism | |
| JP2004133800A (en) | Semiconductor integrated circuit device | |
| US10637476B2 (en) | Clock integrated circuit | |
| TWI400884B (en) | Clock integrated circuit | |
| CN105871335A (en) | Crystal oscillation device and semiconductor device | |
| KR102304755B1 (en) | 1t1d dram cell and access method and associated device for dram | |
| JPH0620482A (en) | Semiconductor device | |
| CN102098037B (en) | Clock circuit of integrated circuit | |
| CN102118151A (en) | Clock circuit for integrated circuit | |
| CN102664616B (en) | Integrated clock circuit | |
| US8245074B2 (en) | Clock integrated circuit | |
| CN102664615B (en) | Clock circuit of integrated circuit | |
| CN102111140A (en) | Clock circuit of integrated circuit | |
| US6870433B2 (en) | Oscillator circuit | |
| Karahaliloglu et al. | Bio-inspired compact cell circuit for reaction-diffusion systems | |
| CN102315836B (en) | Clock integrated circuit | |
| CN109074115A (en) | The system and method for reference voltage or electric current are provided | |
| TWI506395B (en) | Clock integrated circuit | |
| TWI393348B (en) | Clock integrated circuit | |
| JP3068450B2 (en) | Substrate voltage generation circuit | |
| Zhou et al. | A high-performance wordline voltage-generating system for low-power low-voltage flash memory | |
| CN107086050A (en) | A kind of pump body structure and electronic installation for many time-program(me) memories | |
| CN109283966A (en) | A kind of clock circuit and terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |