1380*417 ，六、發明說明： 【發明所屬之技術領域】 本發明係有關於多晶片堆疊之半導體裝置，特別係有 關於一種薄型多晶片封裝構造。 【先前技術】 多晶片封裝（multi-chip package，MCP)技術普遍運用 於半導體封裝領域’基於半導體封裝實用需求，如將多 _ 個相同電性功能晶片封裝一體成具有更多記憶體容量之 多晶片模組，或者將多個電性功能不同晶片封裝一體成 具有系統運算功能之系統封裝（system in package)，並且 可依照晶片之型態不同須個別呈打線（wire_b〇nding)或 覆晶（flip-chip)加#封裝。 目前半導體產業中，由於覆晶（flip_chip)技術具有較 佳的可靠度與性能，逐漸有取代打線（wire_b〇nding)技術 成為主流之趨勢。但因為打線技術仍較為普及且能達到 鲁冑低差之電性連接已發展出覆晶與打線技術並存的 多晶片堆疊技術。請參閱第1圖所示，揭示一種習知的 覆晶加打線技術且晶片尺寸不同之多晶片封裝構造 100’主要包含-基板120、一底部填充膠13〇、一母晶 片140、一子晶片150以及一封膠體190，其中該母晶片 140與該子晶片15G係為背對背堆疊，並且該子晶片15〇 的晶片尺寸小於該母晶片並承載於該母晶片140上。該 母晶月140之主動面141係且古菇把加* 保具有複數個銲球143，作為 覆晶接合之凸塊元件。在霜B垃人卩主 牡復日日接合時，可藉由該些銲球 3 1380417 • 143接合至該基板120之凸塊接墊121»該底部填充膠 130係設置於該母晶片140之底部，以包覆該些鲜球 143。該子晶片150之背面係設置於該母晶片14〇的背 面，可在該母晶片140與該子晶片150之間係設有一黏 晶層180，以達到晶片黏合。其中，該子晶片i 5〇係具 有複數個銲墊151’並以複數個銲線16〇電性連接該此 銲墊151至該基板12〇之打線接墊122。該封膠體19〇 φ 係為模封形成，以密封該母晶片140、該底部填充膠 130、該子晶片150與該些銲線16〇，但為了避免該些銲 線160外露，會在該子晶片15〇上方產生一定的封膠厚 度。 因此，目前已知的覆晶與打線技術並存的下大上小 片堆疊技術中，還需要帛封形成之封勝體19〇，以包 該子日日>! 150與該些銲線16〇，並提供保護之作用。 了設置該封膠冑19G ’除了需要提供額外的封膠設備 更會增加封膠材料的費肖，使得製造成本提高。並且 在設置該封膠體19〇時，必須要考慮到該母晶片14〇 厚度與該些銲、線16G之打線弧高，使得整體的封裝結 因該封膠體19〇右一如$眉办 有一相备厚度而無法有效縮小，大大 限制了整體的封裝 赢…首 肖裝尺寸。此外，在習知下大上小晶片: 疊所必須之模封费〜 Μ師 冑程中也相备谷易造成該些銲線160 j 落或受知之情況。 【發明内容】 本發8月> + 要目的係在於提供一種薄型多晶月封^ 4 1380417 構造，以母晶 晶晶片組，能 模封製程，除 省製造成本。 片主動面承載子晶片 夠省略習知的下大上 了能夠大幅縮小封裝 的架構先行構成一覆 小晶片堆疊所必須之 尺寸與厚度外，更節 種薄型多晶片封裝 ，.以防止發生接合 本發明之次一目的^^在於提供一 構造，可同時保護周邊金屬柱與銲線 點脫落之問題》 • 本發明之再一目的係在於提供-種薄型多晶片封裝 構造’可有效控制母晶片塌陷高度，以避免銲線受損。 本發明的㈣及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種薄型多晶片封裝構造主 要包含-覆晶晶片組、-基板以及—底部填充膠。該覆 晶晶片組係包含一母晶片係具有一主動面、複數個設置 於該主動面上之打線墊以及複數個設置於該主動面上之 周邊金屬柱。一子晶片係貼設於該母晶片之該主動面。 • 複數個銲線係電性連接該子晶片至該些打線墊。複數個 銲料係結合在該些周邊金屬柱之上並超過該些銲線之弧 咼。該基板係具有複數個凸塊接墊，其中當該覆晶晶片 組係接合至該基板，該些銲料係焊接至該些凸塊接墊， 並且該些銲線不碰觸到該基板。該底部填充膠係形成於 該覆晶晶片組與該基板之間，以密封該子晶片、該些銲 線、該些周邊金屬柱與該些銲料。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 5 1380417 在前述之薄型多晶片封裝構造中，在該基板上係可形 成有一防銲層’該防銲層係具有一中央開口，以顯露該 些凸塊接墊。 前述之薄型多晶片封裝構造中，該中央開口係可小於 該母晶片之該主動面，以致使該防銲層局部覆蓋該些凸 塊接墊。 前述之薄型多晶片封裝構造中，該基板在該中央開口 内未有顯露線路。 前述之薄型多晶片：封裝構造中，在該基板上係可設有 一絕緣墊’對應於該子晶片’以避免該些銲線碰觸到該 基板。 前述之薄型多晶片封裝構造中’在該基板上係可設有 一絕緣墊，對應於該子晶片，以避免該些銲線碰觸到該 基板’該絕緣墊係位於該中央開口内且薄於該防銲層。 前述之薄型多晶片封裝構造中，該基板之底面積尺寸 Φ 係可不大於該母晶片之主動面之1.5倍，以構成晶片尺 寸封裝。 前述之薄型多晶片封裝構造中，該些周邊金屬柱係可 具有一致之高度且大於該子晶片之厚度。 前述之薄型多晶片封裝構造中，在該子晶片與該母晶 片之間係可設有一黏晶層，該些周邊金屬柱之高度仍大 於該子晶片與該黏晶層之厚度總和。 前述之薄型多晶片封裝構造中，該些周邊金屬柱係可 為銅柱。 6 1380417 由以上技術方案可以看出，本發明之薄型多晶片封裝 構造，有以下優點與功效·· 、 可藉由覆晶晶片組與底部填充膠之特定組合關係作 為其中一技術手段，由於底部填充膠能完全密封封 裝構造的内部元件’包含子晶片、銲線、周邊金屬 柱，銲科等，故能省略以往的模封形成之封穋體， 由習知下大上小晶片堆疊架構變更為以母晶片主動 面承載子曰曰片之覆晶晶片組以省略習知的下大上 小晶片堆疊所必須之模封製程，除了能夠大幅縮小 封裝尺寸與厚度外’更節省製造成本。 °藉由覆B曰曰曰片組、基板與底部填充膠之特定組合 關係作為其中-4+ Λΐζζ. ，技術手奴，由於底部填充膠係形成 於覆晶晶片組與基板之間，可同時密封周邊金屬 柱、子晶片與銲線，以防止發生接合點脫落之問題。 可藉由母晶片、周邊金屬柱與銲料之特定組合關係 、t #術手段，由於銲料係結合在周邊金屬 柱之上且超過銲線之弧高， π»丹以銲枓焊接周邊金屬 柱至基板’使得銲㈣會碰觸至基板，除了能以周 邊金屬枉有效控制母晶片之塌陷高度外，更可避免 銲線受損。 【實施方式】 以下將配合所附圖示詳細說明 不發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法 a 貝也万去’故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 邊置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種薄型多晶片封裝構 造舉例說明於第2圖之截面示意圖與第3八與38圖之元 件截面示意圖。該薄形多晶片封裝構造200係主要包含 〆覆晶晶片組210、一基板22〇以及一底部填充膠23〇。 其中，如第3A圖所示，該覆晶晶片組21〇係構成在覆 曰曰接合之刖，而非在該基板22〇上逐一進行晶片堆疊。 請參閱第2及3A圖所示，該覆晶晶片組21〇係包含 有一母晶片240、一子晶片25〇、複數個銲線26〇以及複 數個銲料270。該母晶片24〇係具有一主動面241、複數 個置於該主動面241上之打線墊242以及複數個設置 於該主動面241上之周邊金屬柱243。詳細而言，該些 周邊金屬柱243係可為銅柱且突出於該主動面241。在 本實施例中，該些周邊金屬柱243係可具有一致之高度 且大於該子晶片250之厚度，故能有效地控制並維持該 母晶片240之塌陷高度。 該子晶片250係以其背面貼設於該母晶片240之該主 動面241 ’並且具有複數個銲墊251在其主動面。詳細 而言’該子晶片250係設置於該母晶片240之主動面241 的中央部位’而不覆蓋至該些打線墊242，使得該些打 1380417 • 線墊242能顯露於該子晶片25〇與該些周邊金屬枉243 之間。在本實施例中，該子晶片250與該母晶片24〇之 間係可設有一黏晶層280 ’並且該些周邊金屬柱243之 高度仍大於該子晶片250與該黏晶層28〇之厚度總和。 該些銲線260係電性連接該子晶片250至該些打線塾 242。更具體地，該些銲線260係接合該子晶片25〇之該 些銲墊251與該母晶片240之該些打線墊242，以導通 φ 該子晶片250與該母晶片240 ’並作為訊號傳遞的媒介。 該些銲料270係結合在該些周邊金屬柱243之上並超 過該些銲線260之弧高。該些銲料270係可為無鉛銲料， 例如：錫-銀-銅或錫-鉍。具體而言，再如第2圖所示， 該些周邊金屬柱243與該些銲料270之高度總和H1係 大於該些銲線260之弧高H2，包含覆晶接合之前和覆晶 接合之後的狀態，故能使該些銲線260的弧高至該基板 220尚留有一段間距’以避免該些銲線26〇被碰觸變形 φ 或受損。 該基板220係具有複數個凸塊接墊221，其中當該覆 晶晶片組210係接合至該基板220，該些銲料27〇係焊 接至該些凸塊接墊221，並且該些銲線26〇不碰觸到該 基板220。詳細而§，該基板220之底面積尺寸係可不 大於該母晶片240之主動面241之1.5倍，w接々„ u構成晶片 尺寸封裝（Chip Scale Package，CSP)，為以往下大上丨曰 白白 片堆疊架構所不能及。在本實施例中，如第2圖所示， 並請參酌第3B圖，在該基板220上係可形成有—防鲜 9 1380417 • 層222，該防銲層222係具有一中央開口 222A ’以顯露 該些凸塊接墊221。更進一步地，該中央開口 222A係可 小於該母晶片240之該主動面24卜以致使該防銲層222 局部覆蓋該些凸塊接墊22卜具體而言’如第3B®所示’ 該防銲層222係僅部分覆蓋住該些凸塊接墊221遠離該 子晶片250之一端。較佳地，該基板220在該中央開口 222 A内未有顯露線路，有利於該底部填充膠23 0的填 φ 充。此外，在該基板220上係可設有一絕緣墊223，位 置對應於該子晶片250，以避免該些銲線260碰觸到該 基板220。尤佳地，該絕緣墊223係位於該中央開口 222A 内且薄於該防銲層222，故能在該基板220與該子晶片 250之間提供更充足的空間，使得該些銲線260不會壓 觸至該絕緣墊223而造成變形。在另一變化實施例中， 該基板220係可不具有該防銲層222，但在該基板220 上設有該絕緣墊223，對應於該子晶片250，以避免該些 鲁 鲜線260碰觸到該基板220之其它部位，而產生短路或 是脫落之問題。 該底部填充膠23 0係形成於該覆晶晶片組2丨〇與該基 板220之間’以密封該子晶片25〇、該些銲線26〇、該些 周邊金屬柱243與該些銲料27(^該底部填充膠23〇係 為一種塗施時具有高流動性之絕緣膠體，可藉由毛細現 象填滿該覆晶晶片組2 1 0底部的高低起伏之覆晶間隙。 因此，可以同時保護該些周邊金屬枉243與該些鲜線 260,除了該些周邊金屬柱243與該些銲線26〇本身所具 10 1380.417 有的結合力之外，該底部填充膠230更提供了多一層的 包覆力，補強了整體的結合強度，更能避免發生該些周 邊金屬柱243與該些銲線260從接合點脫落之情況》 在本發明中，藉由覆晶晶片組與底部填充膠之特定組 合關係作為其中一技術手段，故能省略以往的模封形成 之封膠體，進而能省略習知的下大上小晶片堆疊所必須 之模封製程。此外’除了能夠大幅縮小封裝尺寸與厚度 外’更節省製造成本。這是因為本發明利用了該底部填 充膠230密封在該母晶片240下的所有内部元件，以省 略習知的模封膠體’在製程中毋須提供額外的模封冷具 與設備，更免除了封膠材料的成本支出，也因省去了習 知的封膠體，而能有效地薄化整體的封裝高度，以縮小 封裝尺寸與厚度。請參酌第丨與2圖所示，在本發明與 習知選用相同尺寸大小的母晶片與子晶片之情況下本 發明之薄型多晶片封裝構造200之封‘裝尺寸與厚度明顯 地小於習知的多晶片封裝構造1〇〇之封裝尺寸與厚度。 此外，本發明使用該些周邊金屬柱243沾著該些銲料 270’以接合該母晶片24〇與該基板22〇,可有效控制該 母晶片240之水平度與該母晶片240至該基板22〇之高 度，以避免塌陷或歪斜，進而避免該些銲線260受損？ 本發明還揭示該薄形多晶片封裝構ϋ 200之組合方 法舉例說明於第3 Α與3Β圖夕；从井^ ° 興^圖之tl件截面示意圖，詳細 驟說明如下所示》 首先’請參閱第3Α圖所示，提供一覆晶晶片組21〇。 11 1380417 在本實施例中’該覆晶晶片組2i〇係由一母晶片24〇、 一子晶片250、複數個銲線26〇以及複數個銲料27〇所 構成。該母晶片240係具有一主動面241、複數個設置 於該主動面24 1上之打線墊242以及複數個設置於該主 動面241上之周邊金屬柱243 ^該子晶片25〇係貼設於 該母晶片240之該主動面241。該些銲線26〇係電性連 接該子晶片250至該些打線墊242 ^該些銲料27〇係結 φ 合在該些周邊金屬柱243之上並超過該些銲線26〇之弧 高。此外，在該子晶片250與該母晶片24〇之間係可設 有一黏晶層280，該些周邊金屬柱243之高度係大於該 子晶片250與該黏晶層280之厚度總和。該子晶片25〇 與該母晶片240之組合與電性連接可在晶圓等級實施。 接著’請參閲第3B圖所示，提供一基板220，係具 有複數個凸塊接墊221，其中當該覆晶晶片組2丨〇係接 合至該基板220，該些銲料270係焊接至該些凸塊接墊 φ 221 ’並且該些銲線260不碰觸到該基板220。此外，該 基板220在該中央開口 222A内可未有顯露線路，有利 於後續填膠之製程進行。更進一步地，在該基板220上 係可設有一絕緣墊2 2 3，係對應於該子晶片2 5 0，以避免 該銲線260碰觸到該基板220，該絕緣墊223係位於該 中央開口 222A.内且薄於該防銲層222。當該覆晶晶片組 2 1 0翻轉之後，使該母晶片240之主動面241朝向該基 板220形成有該些凸塊接墊221之表面，再以該些周邊 金屬柱243對準並接合至該些凸塊接墊22 1，經迴焊即 12 1380417 達成該覆晶晶片組210與該基板22〇之電性連接關係。 最後’如第2圖所示，填入一底部填充膠23〇於該覆晶 晶片組210與該基板220之間，同時密封並保護該子晶 片250、該些銲線260、該些周邊金屬柱243與該些銲料 270’即可完成本發明之薄形多晶片封裝構造2⑽而省 略以往的下大上小晶片堆疊所必須之模封製程除了能 節省製造成本之外，更大幅地縮小了封裝尺寸與厚度。 以上所述，僅是本發明的較佳實施例而已並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限玄太益^ ηΒ 业开用W限疋本發明，任何熟悉本項技 術者，在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾’均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖：為習知的多晶片封裝構造之截面示意圖。 第2圖：依據本發明之一具體實施例的一種薄型多晶片 封裝構造之截面示意圖。 第3Α與3Β圖：依據本發明之一具體實施例的薄型多晶 片封裝構造之組合方法之元件截面示意圖。 【主要元件符號說明】 Η1周邊金屬柱與銲料之高度總和 Η2 銲線之弧高 100多晶片封裂構造 122打線接墊 120基板 121凸塊接墊 13 1380417 130 底 部 填 充 膠 140 母 晶 片 141 主 動面 143 銲 球 150 子 晶 片 151 銲 墊 160 銲 線 180 黏 晶層 190 封 膠體 200 薄 型 多 晶 片 封裝構造 210 覆 晶 晶 片 組 220 基板 221 凸 塊接墊 222 防 銲 層 222A ' 中央開口 223 絕 緣墊 230 底 部 填 充 膠 240 母 晶 片 241 主 動面 242 打 線塾 243 周 邊 金 屬 柱 250 子 晶 片 251 銲 墊 260 銲 線 270 銲 料 280 黏 晶層1380*417, VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device for multi-wafer stacking, and more particularly to a thin multi-chip package structure. [Prior Art] Multi-chip package (MCP) technology is widely used in the field of semiconductor packaging. Based on the practical needs of semiconductor packaging, such as packaging more than one same electrical functional chip into more memory capacity. The chip module or a plurality of electronically functionally different chip packages are integrated into a system in package having a system operation function, and may be individually wired or flipped according to the type of the wafer (wire_b〇nding or flip chip) Flip-chip) plus # package. At present, in the semiconductor industry, due to the high reliability and performance of flip-chip technology, there is a trend to replace the wire_b〇nding technology. However, multi-wafer stacking technology has been developed because of the popularization of wire bonding technology and the ability to achieve a reckless electrical connection. Referring to FIG. 1 , a multi-chip package structure 100 ′ of a conventional flip chip bonding technique and having different wafer sizes is mainly included—a substrate 120 , an underfill 13 , a mother wafer 140 , and a sub-wafer . 150 and a colloid 190, wherein the mother wafer 140 and the sub-wafer 15G are stacked back to back, and the wafer size of the sub-wafer 15 is smaller than the mother wafer and carried on the mother wafer 140. The active surface 141 of the mother crystal 140 is provided with a plurality of solder balls 143 as a bump element for flip chip bonding. When the bonding is performed, the bonding pads may be bonded to the substrate 120 by the solder balls 3 1380417 • 143. The underfill 130 is disposed on the mother wafer 140. The bottom is to cover the fresh balls 143. The back surface of the sub-wafer 150 is disposed on the back surface of the mother wafer 14A. An adhesive layer 180 may be disposed between the mother wafer 140 and the sub-wafer 150 to achieve wafer bonding. The sub-wafer has a plurality of pads 151' and electrically connects the pads 151 to the bonding pads 122 of the substrate 12 by a plurality of bonding wires 16A. The sealing body 19〇φ is formed by sealing to seal the mother wafer 140, the underfill 130, the sub-wafer 150 and the bonding wires 16〇, but in order to prevent the bonding wires 160 from being exposed, A certain seal thickness is produced above the sub-wafer 15 . Therefore, in the next large stacking technology in which the flip chip and the wire bonding technology are coexisting, the seal body formed by the seal is required to cover the sub-day >! 150 and the weld lines 16〇 And provide protection. In addition to the need to provide an additional sealing device, the installation of the sealing tape 19G ′ will increase the cost of the sealing material, resulting in an increase in manufacturing cost. Moreover, when the encapsulant 19 is disposed, it is necessary to take into account that the thickness of the mother wafer 14 is higher than the arc of the solder and the line 16G, so that the overall package is formed by the seal body 19, such as the eyebrow. The thickness of the film can not be effectively reduced, which greatly limits the overall package win... In addition, in the conventional small and small wafers: the necessary mold seal fee ~ Μ 胄 胄 胄 也 也 也 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 谷 。 。 。 。 。 。 。 SUMMARY OF THE INVENTION The present invention is directed to providing a thin polycrystalline moon seal ^ 4 1380417 structure, which is capable of molding a process, in addition to a manufacturing cost. The active surface carrying sub-wafer can omit the conventional structure that can greatly reduce the size of the package. The size and thickness of the small wafer stack are formed first, and the thin multi-chip package is further reduced to prevent the occurrence of the bonding. A second object of the invention is to provide a structure that simultaneously protects the peripheral metal pillars from the problem of the solder wire dots falling off. " A further object of the present invention is to provide a thin multi-chip package structure that can effectively control the collapse of the mother wafer. Height to avoid damage to the wire. The fourth aspect of the present invention and solving the technical problems are achieved by the following technical solutions. The present invention discloses a thin multi-wafer package construction that primarily includes a flip chip package, a substrate, and an underfill. The flip chip package includes a master wafer having an active surface, a plurality of wire pads disposed on the active surface, and a plurality of peripheral metal posts disposed on the active surface. A sub-wafer is attached to the active surface of the mother wafer. • A plurality of bonding wires are electrically connected to the sub-wafer to the wire pads. A plurality of solder bonds are bonded over the perimeter metal posts and beyond the arcs of the bond wires. The substrate has a plurality of bump pads, wherein when the flip chip is bonded to the substrate, the solder is soldered to the bump pads, and the solder lines do not touch the substrate. The underfill is formed between the flip chip group and the substrate to seal the sub-wafer, the bonding wires, the peripheral metal pillars and the solder. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. 5 1380417 In the aforementioned thin multi-chip package construction, a solder resist layer is formed on the substrate. The solder resist layer has a central opening to expose the bump pads. In the aforementioned thin multi-chip package construction, the central opening may be smaller than the active surface of the mother wafer such that the solder resist partially covers the bump pads. In the aforementioned thin multi-chip package construction, the substrate has no exposed lines in the central opening. In the above-described thin multi-wafer: package structure, an insulating pad ′ corresponding to the sub-wafer may be disposed on the substrate to prevent the bonding wires from contacting the substrate. In the above thin multi-chip package structure, an insulating pad may be disposed on the substrate corresponding to the sub-wafer to prevent the bonding wires from contacting the substrate. The insulating pad is located in the central opening and is thinner than The solder mask. In the above thin multi-chip package structure, the substrate has a bottom area dimension Φ of not more than 1.5 times the active surface of the mother wafer to constitute a wafer size package. In the aforementioned thin multi-chip package construction, the peripheral metal pillars may have a uniform height and be greater than the thickness of the sub-wafer. In the above thin multi-chip package structure, a die bond layer may be disposed between the daughter chip and the mother wafer, and the height of the peripheral metal pillars is still greater than the sum of the thicknesses of the daughter wafer and the die bond layer. In the aforementioned thin multi-chip package structure, the peripheral metal pillars may be copper pillars. 6 1380417 It can be seen from the above technical solution that the thin multi-chip package structure of the present invention has the following advantages and effects. The specific combination relationship between the flip chip group and the underfill can be used as one of the technical means, due to the bottom. The filling glue can completely seal the internal components of the package structure, including the sub-wafer, the bonding wire, the surrounding metal column, the welding, etc., so that the sealing body formed by the conventional molding can be omitted, and the stacking structure of the large and small wafers is changed by the conventional method. In order to omit the flip chip wafer set of the active wafer surface of the mother wafer to omit the molding process necessary for the conventional stacking of the upper and lower wafers, in addition to being able to greatly reduce the package size and thickness, the manufacturing cost is saved. ° By the specific combination of the B-plate group, the substrate and the underfill, as the -4+ Λΐζζ., the technical slave, since the underfill is formed between the flip chip and the substrate, The surrounding metal posts, sub-wafers and bonding wires are sealed to prevent the occurrence of joint breakage. By the specific combination relationship between the mother wafer, the peripheral metal pillar and the solder, and the t# method, since the solder is bonded on the peripheral metal pillar and exceeds the arc height of the bonding wire, the π»丹 is welded to the surrounding metal pillar to The substrate 'makes the solder (4) to touch the substrate, in addition to effectively controlling the collapse height of the mother wafer with the surrounding metal iridium, and avoiding damage to the bonding wire. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Bei Ye Wan went to 'therefore only showed the components and combinations related to this case. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated. Or simplify the process to provide a clearer description. The actual number, shape and size ratio of the implementation is a kind of edge design, and the detailed component layout may be more complicated. In accordance with an embodiment of the present invention, a thin multi-wafer package construction is illustrated in cross-sectional view in FIG. 2 and cross-sectional views of elements in FIGS. 8 and 38. The thin multi-chip package structure 200 is mainly composed of a flip chip wafer set 210, a substrate 22, and an underfill 23A. Here, as shown in Fig. 3A, the flip chip group 21 is formed after the overlying bonding, and the wafer stacking is not performed one by one on the substrate 22. Referring to Figures 2 and 3A, the flip chip package 21 includes a mother wafer 240, a daughter wafer 25A, a plurality of bonding wires 26A, and a plurality of solders 270. The mother chip 24 has an active surface 241, a plurality of wire pads 242 disposed on the active surface 241, and a plurality of peripheral metal posts 243 disposed on the active surface 241. In detail, the peripheral metal pillars 243 may be copper pillars and protrude from the active surface 241. In this embodiment, the perimeter metal pillars 243 can have a uniform height and greater than the thickness of the sub-wafer 250, so that the collapse height of the mother wafer 240 can be effectively controlled and maintained. The sub-wafer 250 has its back surface attached to the active surface 241' of the mother wafer 240 and has a plurality of pads 251 on its active surface. In detail, the sub-wafer 250 is disposed at a central portion of the active surface 241 of the mother wafer 240 without covering the wire pads 242, so that the 1380417 • wire pads 242 can be exposed on the sub-wafer 25〇. Between the peripheral metal crucibles 243. In this embodiment, a bonding layer 280 ′ may be disposed between the sub-wafer 250 and the mother wafer 24 并且 and the height of the peripheral metal pillars 243 is still greater than the sub-wafer 250 and the bonding layer 28 . The sum of the thicknesses. The bonding wires 260 are electrically connected to the sub-wafer 250 to the wire bonding wires 242. More specifically, the bonding wires 260 are bonded to the pads 251 of the sub-wafer 25 and the bonding pads 242 of the mother wafer 240 to turn on the sub-wafer 250 and the mother wafer 240' as signals. The medium of transmission. The solders 270 are bonded over the perimeter metal posts 243 and above the arc height of the bond wires 260. The solders 270 can be lead-free solders such as tin-silver-copper or tin-bismuth. Specifically, as shown in FIG. 2, the height sum H1 of the peripheral metal pillars 243 and the solders 270 is greater than the arc height H2 of the soldering wires 260, including before the flip chip bonding and after the flip chip bonding. The state can be such that the arc of the bonding wires 260 is high enough to leave a gap between the substrates 220 to prevent the bonding wires 26 from being touched and deformed or damaged. The substrate 220 has a plurality of bump pads 221, wherein when the flip chip set 210 is bonded to the substrate 220, the solders 27 are soldered to the bump pads 221, and the solder wires 26 are soldered. The substrate 220 is not touched. In detail, the bottom surface area of the substrate 220 may be no more than 1.5 times that of the active surface 241 of the mother wafer 240. The connection of the substrate 220 is a chip scale package (CSP). In the present embodiment, as shown in FIG. 2, and referring to FIG. 3B, a heat-resistant 9 1380417 layer 222 may be formed on the substrate 220, and the solder resist layer may be formed. The 222 has a central opening 222A' to expose the bump pads 221. Further, the central opening 222A can be smaller than the active surface 24 of the mother wafer 240 to partially cover the solder resist layer 222. The bump pads 22 are specifically as shown in FIG. 3B®. The solder resist layer 222 only partially covers the bump pads 221 away from one end of the sub-wafer 250. Preferably, the substrate 220 is There is no exposed line in the central opening 222 A, which is beneficial to the filling of the underfill 23 0. Further, an insulating pad 223 may be disposed on the substrate 220 at a position corresponding to the sub-wafer 250 to avoid the The bonding wires 260 touch the substrate 220. More preferably, the insulating pad 2 The 23 series is located in the central opening 222A and thinner than the solder resist layer 222, so that a sufficient space can be provided between the substrate 220 and the sub-wafer 250, so that the bonding wires 260 do not press the insulating pad. In another variation, the substrate 220 may not have the solder resist layer 222, but the insulating pad 223 is disposed on the substrate 220 corresponding to the sub-wafer 250 to avoid the The fresh wire 260 touches the other portion of the substrate 220 to cause a short circuit or a problem of falling off. The underfill film 30 is formed between the flip chip group 2 and the substrate 220 to seal the sub-ring. The wafer 25〇, the bonding wires 26〇, the peripheral metal pillars 243 and the solders 27 (the underfill rubber 23) are an insulating colloid having high fluidity when applied, and can be filled by capillary phenomenon. The high and low undulating flip-chip gaps at the bottom of the flip chip group 210 are filled. Therefore, the peripheral metal ruins 243 and the fresh lines 260 can be simultaneously protected, except for the peripheral metal pillars 243 and the bonding wires 26 The underfill is in addition to the bonding strength of 10 1380.417. 230 further provides a layer of coating force, which reinforces the overall bonding strength, and can avoid the occurrence of the peripheral metal pillars 243 and the bonding wires 260 falling off from the joint. In the present invention, by flip chip The specific combination relationship between the wafer set and the underfill is one of the technical means, so that the conventional seal-formed encapsulant can be omitted, and the molding process necessary for the conventional stacking of the upper and lower wafers can be omitted. The ability to significantly reduce package size and thickness 'more manufacturing costs. This is because the present invention utilizes the underfill 230 to seal all internal components under the mother wafer 240, omitting the conventional molding compound's process without providing additional molding colds and equipment during the process, and exempting The cost of the sealing material is also reduced by the conventional encapsulant, which can effectively thin the overall package height to reduce the package size and thickness. Referring to Figures 2 and 2, the thin multi-chip package structure 200 of the present invention has a package size and thickness that is significantly smaller than in the case where the present invention and the conventional size and size of the mother wafer and the sub-wafer are selected. The multi-chip package construction has a package size and thickness. In addition, the present invention uses the peripheral metal pillars 243 to adhere to the solder 270' to bond the mother wafer 24 and the substrate 22, and can effectively control the level of the mother wafer 240 and the mother wafer 240 to the substrate 22. The height of the crucible is to avoid collapse or skew, thereby avoiding damage to the weld lines 260? The present invention also discloses that the combination method of the thin multi-chip package structure 200 is exemplified in the third and third Β ;; the cross-section of the tl piece from the well ^ ° ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Referring to Figure 3, a flip chip set 21A is provided. 11 1380417 In the present embodiment, the flip chip group 2i is composed of a mother wafer 24A, a sub-wafer 250, a plurality of bonding wires 26A, and a plurality of solders 27A. The mother wafer 240 has an active surface 241, a plurality of wire pads 242 disposed on the active surface 24 1 , and a plurality of peripheral metal posts 243 disposed on the active surface 241 . The active surface 241 of the mother wafer 240. The bonding wires 26 are electrically connected to the sub-wafer 250 to the bonding pads 242. The solders 27 are tied to the peripheral metal pillars 243 and exceed the arc heights of the bonding wires 26 . In addition, a bonding layer 280 may be disposed between the sub-wafer 250 and the mother wafer 24A. The height of the peripheral metal pillars 243 is greater than the sum of the thicknesses of the sub-wafer 250 and the bonding layer 280. The combination and electrical connection of the sub-wafer 25A and the mother wafer 240 can be performed at the wafer level. Next, as shown in FIG. 3B, a substrate 220 is provided having a plurality of bump pads 221, wherein when the flip chip package 2 is bonded to the substrate 220, the solders 270 are soldered to The bump pads φ 221 ′ and the bonding wires 260 do not touch the substrate 220 . In addition, the substrate 220 may have no exposed lines in the central opening 222A, which facilitates the subsequent filling process. Further, an insulating pad 2 2 3 may be disposed on the substrate 220 corresponding to the sub-wafer 250 to prevent the bonding wire 260 from contacting the substrate 220. The insulating pad 223 is located at the center. The opening 222A. is inside and thinner than the solder resist layer 222. After the flip-chip wafer set 210 is turned over, the active surface 241 of the mother wafer 240 is formed with the surface of the bump pads 221 facing the substrate 220, and then aligned and bonded to the peripheral metal pillars 243. The bump pads 22 1 are electrically reflowed by the reflow, ie 12 1380417, to the flip chip group 210 and the substrate 22 . Finally, as shown in FIG. 2, an underfill 23 is filled between the flip chip set 210 and the substrate 220, and the sub-wafer 250, the bonding wires 260, and the peripheral metal are sealed and protected. The pillar 243 and the solder 270' can complete the thin multi-chip package structure 2 (10) of the present invention, and the molding process necessary for omitting the conventional stacking of the upper and lower wafers can be greatly reduced in addition to the manufacturing cost. Package size and thickness. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the use of the limit. In the present invention, any simple modifications, equivalent changes, and modifications made by those skilled in the art without departing from the scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-chip package structure. Figure 2 is a schematic cross-sectional view of a thin multi-wafer package construction in accordance with an embodiment of the present invention. 3D and 3D are schematic cross-sectional views of elements of a combination method of a thin polycrystalline wafer package structure in accordance with an embodiment of the present invention. [Main component symbol description] Η1 The sum of the heights of the surrounding metal pillars and the solder Η2 The arc height of the bonding wire 100 more wafers Folding structure 122 Wire bonding pads 120 Substrate 121 bump pads 13 1380417 130 Underfill rubber 140 Mother wafer 141 Active surface 143 solder balls 150 sub-chips 151 pads 160 bonding wires 180 bonding layer 190 encapsulant 200 thin multi-chip package structure 210 flip chip group 220 substrate 221 bump pads 222 solder mask 222A ' central opening 223 insulating pad bottom Filler 240 Mother wafer 241 Active surface 242 Wire 塾 243 Peripheral metal post 250 Sub-wafer 251 Pad 260 Bond wire 270 Solder 280 Bonding layer