SU1647870A1 - Pulse loss detector - Google Patents

Abstract

The invention can be used both in data reception and processing systems for detecting the loss of pulses in a sequence, as well as for restoring a pulse when it is lost in a controlled sequence. The purpose of the invention is to expand the functionality by enabling recognition of single and multi-pulse input series, as well as improving the reliability of detecting the loss of a pulse by providing the possibility of detecting loss and recovery. The invention relates to a pulse technique and can be used in data reception and processing systems. detecting the loss of pulses in a sequence, as well as for restoring a pulse when it is lost in a controlled sequence. The purpose of the invention is to expand the functionality by enabling the recognition of single and multi-input input series, as well as a pulse, starting with the second pulse of the monitored sequence. The goal is achieved by introducing into the device an additional reversible counter 2 pulses, a decoder 3, a third 7 and a fourth 8 And elements, as well as an inverter 9. In addition, the device contains a delay element 1, an asynchronous trigger 4, the first 5 and the second 6 elements And, a driver 10 pulses, the element OR 11 and the input bus 12. As the driver 10, the device uses the delayed pulse duration driver. The device generates at the output of the element OR 11 recovered input pulse sequence, at the output of the element And 7 - impulses of replacement of the missing pulse of the input sequence, at the output of the element And 5 - input unrestored multipulse sequence, and at the output of the element And 6 - single-pulse input series. The delay time of delay element 1 and driver 10 (delayed pulse duration) is selected from the mathematical expressions given in the description of the invention. 2 Il. increasing the reliability of detecting the loss of a pulse by enabling the detection and recovery of a pulse, starting with the second pulse of the monitored sequence. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagrams that show his work. The device contains a delay element 1, a counter 2 pulses, a decoder 3, asynON J VI CO V O

Description

crown trigger 4, the first 5, the second 6, the third 7 and the fourth 8 elements And, the inverter 9, shaper 10 pulses, the element OR 11 and the input bus 12.

The input of the delay element 1 is connected to the input bus 12 of the device and the summing input of the pulse counter 2, the subtractive input of which is combined with the output of the delay element 1, the first input of the first element And 5, the second input of the second element And 6, the first input of the fourth element And 8 and the input of the inverter 9. The outputs of the first 5, second 6 and third 7 elements And connected to the corresponding inputs of the element ILM 11. The first input of the third element And 7 is connected to the output of the inverter 9, and the second input through the pulse shaper 10 - with the output of the fourth element and And 8, connected by its second input to the first output of the decoder 3, the first and second inputs of which are connected to the corresponding outputs of the counter 2 pulses. The second and fourth outputs of the decoder 3 (the third output is not used) are connected respectively to the single and zero inputs of the asynchronous trigger 4, the direct output of which is connected to the second input of the first element L 5, and the inverse output to the first input of the second element And b.

The delay time of the delay element 1 is selected from the condition 2T g ST, where T is the pulse period of the input sequence.

As a pulse shaper 10, a delay pulse pulse shaper is applied in the device, the formation delay of which is selected from the condition T + .Te. and the thun duration is from the condition of Tyu + 10 and T + t - Te, where is the pulse duration of the input sequence; TD is the delay time of operation of the inverter 9.

A device for detecting the loss of a pulse operates as follows.

In the initial state, the reversible counter 2 pulses is zero (the zero bus in Fig. 1 is not shown) and, therefore, at the fourth output of the decoder 3 there is a zero voltage level that holds the asynchronous trigger 4 in the initial zero state.

The input positive pulses (Fig. 2a) arrive at the input of the addition of the reversible counter 2 and change its state on the trailing edge (Fig. 2c, d). After time r, positive pulses also appear at the output of the delay element.

(FIG. 2 b), acting on the subtracting input of the counter 2 pulses and changing its state (FIG. 2 c, d) in its rear

front. The result of the operation of the counter 2 pulses at each time point is recorded at the corresponding output of the decoder 3 (Fig. 2 d, e, g).

Consider the operation of the device when a single pulse arrives at its input.

0 (impulse of a single impulse series) and a series of several impulses with the loss of any impulse, except the first and the last in the packet (series).

When entering the input bus 12

5 of the impulse device of the series of the same name (Fig. 2 b), a counter 2 pulses is triggered by the summing input, at the output of the first discharge of which a single potential is formed (fig 2 b). As a result on

0, the first output of the decoder 2 appears a zero voltage level (Fig. 2 d), prohibiting the passage of pulses through the fourth element And 8 (Fig. 2 h). The state of the asynchronous trigger 4 (FIG. 2 m) while

5 does not change, i.e. the passage of pulses through the second element And 6 is forbidden and forbidden through the first element 5. After a time r, an output of delay element 1 appears (Fig. 2b), which passes through the output of the second element 6 (Fig. 2n) and the output of the element OR 11 (Fig. 2 p). The output of the element OR 11 is used as the output bus of the device, and the output of the second element And 6 as the indication bus

5 arrivals at the device input of the series, consisting of single pulses. At the end of the pulse at the output of the delay element 1, the counter 2 is triggered by the subtractive input (Fig. 2c) the device returns to the initial state.

When a multipulse pulse train arrives at the input bus 12, a reversible counter 2 by the time the pulses appear from the output of the delay element 1

5 will fix two (in case of loss of the second or third pulse of the input series) or three pulses received at its summing input. At the end of the second pulse received at the input of the addition of the reversible counter 3, the second output of the decoder 3 leads to a zero potential (Fig. 2 e), which converts the asynchronous trigger 4 to a single state (Fig. 2 m). The potentials C of the outputs of the asynchronous trigger 4 prepares 5 to the first element And 5 and the prohibition of the passage of pulses through the second element 6. Therefore, the pulse from the output of the delay element 1 will go to the output of the first element 5 and (FIG 2 n) and through the element OR 11 to the output bus of the device (Fig. 2 p), whereby the output of the element AND 5 is used in the device as the third output bus, the appearance of which pulses indicate the arrival at the input of the device of a multi-pulse series, and the number of pulses received at the output of the element 5 and corresponds to the number of pulses on input bus 12.

In addition, the pulses from the output of the delay element 1 through the open fourth element And 8 (Fig. 2 h) are fed to the input of the generator 10 delayed pulses, at the output of which pulses are formed (Fig. 2 p) coinciding in time with each successive pulse in the undistorted pulse sequences. The pulses from the output of the pulse driver 10 are fed to the second input of the element 7, at the first input of which there is an inverse sequence of pulses (Fig. 2k) from the output of the delay element 1. If at the time of formation of the pulse at the output of the generator 10, the output of the delay element 1, there is no next pulse (there is no corresponding pulse of the input series), then the potential of the inverter b is high (Fig. 2k), allowing the output of the And 7 element pulses from the output of the driver 10 pulses (Fig. 2 l), i.e. . at the output of the element And 7, pulses for replacing the missing pulses in the input pulse sequence are formed. The replacement pulses from the output of the element And 7 are combined with the element OR 11 with pulses of a multi-pulse series from the output of the element 5 and form the recovered pulse sequence at the output of the element OR 11 (Fig. 2 p).

At the end of the penultimate impulse of the input series from the output of the delay element 1, a low potential will be formed at the first output of the decoder 3 (Fig. 2 d). which closes the fourth element And 8, thereby prohibiting the arrival of the last pulse at the input of the generator 10. On the falling edge of the last pulse coming from the output of the delay element 1, the reversible counter 2 is set to the initial zero state, at which the fourth output of the decoder 3 forms a zero the potential returning the asynchronous trigger 4 to the initial zero state, i.e. The device is prepared for the arrival of new sequences of pulses.

Thus, the device for detecting loss of pulses forms on its output tires, i.e. at the output of the element OR 11. - the restored input pulse sequence, at the output of the third element And 7 - replacement pulses

5 missing pulse input sequence, at the output of the first element And 5 - input unrestored multipulse sequence, and at the output of the second element And 6 - single-pulse

0 input series. The device is able to restore the missing pulse sequences, starting with the second and, moreover, the last pulse of the sequence does not pass to the input of the imaging unit 10

5 pulses and, therefore, at the output of the device, false information about the loss of the pulse is not generated.

Claims (1)

Invention Formula 0 A device for detecting a loss of a pulse, comprising a pulse shaper, a delay element combined by an output with a first input of the first element And, the second input of which is connected to a direct 5 output asynchronous trigger, and the output is connected to the first output bus and the first input of the OR element, the second input connected to the output of the second element AND, and the output from the second output bus, which is characterized by the fact that, in order to extend the functionality and increase the reliability of detection loss of momentum, it is additionally equipped with the third and fourth elements AND, 5 by an inverter, a two-input decoder and a reversible pulse counter, the summing input of which is connected to the input bus of the device, and through a delay element to the subtractive input of the counter 0 and the input of the inverter, the output of the third element I, combined with the first input, the output of which is connected to the third output bus and the third input of the OR element, and the second input through the pulse shaper 5 with the output of the fourth element And, the first input associated with the output of the delay element, and the second input - with the first output of the decoder, the second and fourth outputs of which are connected respectively 0 to the single and zero inputs of the asynchronous trigger, the inverse output of which is connected to the first input of the second element And connected by the second input to the output of the delay element, and the output connected to the fourth output bus, the first and second inputs of the decoder are connected to the corresponding outputs of the pulse counter . .