SU1372326A1 - Device for majority sampling of asynchronous signals - Google Patents

Abstract

The invention relates to automation and computing and can be used in highly reliable control systems. The purpose of the invention is to increase the accuracy and increase the depth of control of the device by fixing the arrival of information on only one of the channels and resetting false information on this channel. The device contains triggers 1-4, elements AND 5-8, element AND-NOT 9, element OR-NOT 10, counter 11, shaper 12 single pulses, de-multiplexer 13, input buses 14-16, reset bus 17, bus 18 clock pulses, 19 serial bus, output control tires 20-27. When information is received through only one channel, the number of this channel is recorded and false information on this channel is reset. 3 il. (L

Description

with

The invention relates to a pulsed and computing technique and can be used in interference-resistant automation and computing devices.

The purpose of the invention is to improve the accuracy and increase the depth of control of the device by recording information on only one of the channels and resetting false information on this channel,

Ya figure 1 shows the functional diagram of the device; figure 2 - times

fishing during the time .max lack of signal on two channels over time., v,

When a signal arrives at one of the information inputs 14-16 of the device, the corresponding trigger 1-3 is set to one state, and a negative impulse is generated at the output of the And 7 element, which, at the first input of the IS – NO element 9, holds the signal of the logical unit at its output thereby keeping the counter 11 in the zero state. By windows

charts explaining the operation of the pulse at the output of an element of the device; in FIG. 3, a table of values 7 arriving at the C input of the trigger 4,

output control DIHH.

The device contains the first

finally, it is set to the zero state. At the same time, at both inputs of the NAND 9 element there will be a signal of Logyra 2, the third 3 and the fourth 4 triggers, the first 5, the second 6, the third 7 and 20 ces, and at its output the fourth 8 elements AND, the NAND

the logical zero signal, which is fed to the fault input of the counter I1, allows the clock pulse counting from the bus 18. At the same time, each bus is 14-lb, reset fault 17, home bus 25 pulse for information inputs 9, SHIII-HE element 10 , counter 11 pulses, shaper 12 single pulses, demultiplexer 13, input 18-pulse pulses, output bus

19 and the control iin 20-27.

Figure 2 shows: the signals at the outputs of the corresponding elements 1-13

pulse spacing no more

devices (in brackets indicate the corresponding-30 inputs 14-16 are received compactly with output pshny), signals on input buses 14-16 devices, signals on the bus 18 clock pulses of the device, the maximum possible

 max.max

 Fig. 2, POS. 14, 15, 16), then the triggers 1-3 are set to one (Fig. 2, POS. 1-3).

for this system, the time t.j, is 1 at all the inputs of the AND 5

there will be a signal of a logical unit, which from its output goes to the first input of the element OR-NOT, 10, at the output of which a losynchronization signal is formed between the input signals.

The device works as follows.

The signal on the reset bus 17 of the trigger 40, which arrives at the controllers 1-4, sets the initial input of the generator of 12 single pulses to the initial field (Fig. 2, pos. 10). On the arrival of the front of the next

clock pulse on the I8 bus on laying out: triggers 1-3 into zero, and trigger 4 into one. The AND-HE9 element, having received the logical zero signal from the zero output of the tri-45 ° D driver 12 single imiger 4 at the second input, forms negative pulses at its output.

pulse (Fig. 2, pos. 12), which returns trigger 4 to the initial (single) state and goes to C50

The unit that keeps the pulse counter I1 in the zero state does not allow it to produce the counting of the clock pulses received from the bus 18. The input signals to the information inputs 14-16 are asynchronous, so for example, the reception and processing of pulses are shown in The following characteristic cases: the appearance of signals on the inputs 14-16 is compact with an interval between pulses of no more than Gy, the absence of a signal along one of the channels of the triggers 1–3, and a strobe input of the demultiplexer 13, whose address inputs are present The signal of the logical unit from the outputs of the triggers 1-3. In this case, a 55 signal is generated at the fourth output of the demultiplexer 13 (Fig. 2, pos. 23), which is fed to the control bus 23, signaling the presence of information on all three channels (Fig. 3), and through

the latter is set to the zero state. At the same time, at both inputs of the NANDI element 9 there will be a signal from logids 14-16 a reset-start of the counter 11 takes place. The capacity of the counter corresponds to the time sTd; “Oka

If the signals are informational

interval between pulses not more than

inputs 14-16 do compactly with

inputs 14-16 do compactly with

 max.max

 Fig. 2, POS. 14, 15, 16), then the triggers 1-3 are set to one (Fig. 2, POS. 1-3).

1 on this at all inputs of the element 5

there will be a signal of a logical unit, which from its output goes to the first input of the element OR NOT, 10, at the output of which a signal of a lot of pulse is generated across the I8 bus to the generator 12 of single pulses is formed negative

inputs of triggers 1-3 and the gate input of the demultiplexer 13, on the address inputs of which there is a signal of a logical unit from the outputs of triggers 1-3. In this case, a signal is generated at the fourth output of the demultiplexer 13 (Fig. 2, pos. 23), which is fed to the control bus 23, signaling the presence of information on all three channels (Fig. 3), and through

element And 8 on the output bus 19 (figure 2, pos. 8). But when the pulse ends at the exit of the former 12, the triggers 1–3 return to their initial (zero) state.

Thus, for the case when signals to inputs 14–16 of the device arrive non-simultaneously with the time of desynchronization between pulses, you do not exceed the Tpd signal on the output bus 19 of the device is generated by the arrival of the first clock pulse from the bus 18 after the arrival of the last input signal. t5

If the signals to the inputs 15 and 16 do not arrive simultaneously with the desynchronization time, we do not have a smaller input signal 14 (figure 2, pos. 15 and 16), then 20 similarly, the input 16 is reset. starting counter 11, which counts pulses from bus 18. Through .MOkc the output of counter 1 1, a logical unit signal appears, 25 arriving at the second input of LI-NO 10, forming a logical zero signal at its output (FIG. 2, pos. 10) arriving at the control input of the forirovator 12, and upon the arrival of the anterior ZO front of the next clock imul ca bus 18 at its output foriruets negative pulse (Figure 2, Pos. 12). This impulse

the trigger 4 rotates into the initial (single) state, thereby swatting the counter 11, and also enters the C-inputs of triggers 1-3 and the strobe-input of demultiplexer 13, the signal of the logical unit from the outputs of the trigger 2 and on the second and third address inputs 3 (figure 2, pos. 2, C). In this case, a signal is generated at the second output of the demultiplexer 13 (Fig. 2, pos. 21), which is fed to the control bus 21, signaling the absence of information on the first channel (Fig. 3), and through the And 8 element to the output bus 19 ( figure 2, pos. 8). At the end of this pulse, the triggers 2 and 3 return to the initial (zero) state and the device is ready to receive the next asynchronous signals.

If the signal is received only on one of the inputs of the device, and on the other two inputs is absent for a time (FIG. 2,

pos. 14), then, similarly} 1O, a reset-start of the counter 11 is outputted, the output of which is through the time Gy s, the lax an impulse is formed, which through the element OR-NOT 10 (figure 2, position 10) goes to the control input of the imager 12, and a negative pulse is generated at its output (Fig. 2, pos. 12). In this case, only at the first address input of the demultiplexer 13 there is a signal of a logical unit (Fig. 2, pos. 1), the investigator; however, the signal is generated at the seventh output of the demultiplexer 13 (Fig. 2, pos. 26) and goes to the test station 26 , signaling the availability of information only on the first channel (Fig. 3). At the end of the pulse from the output of the forcer I2, the trigger 1 returns to the initial state, and the device is ready to receive the next asynchronous signals.

Thus, for the case when the signals to the inputs 14-16 of the device do not arrive simultaneously with the time of desynchronization between pulses.

BOLRHIM G

paradise, make

waiting happens

missing signal during the time

The output bus 19 is formed only in case of input signals coming through two (2/3) channels with fixation of the channel number on which there is no information. If the signal comes through only one of the channels, then the number of that channel is fixed, and no signal is generated on the output bus 19.

The device provides for its latching, for example, when a short pulse (interference) pulse arrives at one of the inputs 14-16, from which trigger 4 is triggered, but triggers 1-3 do not trigger, or false triggering 4 triggers to the formation of an output pulse at the output of the shaper (FIG. 2, pos. 10, 12). In this case, at all address inputs of the demultiplexer 1 3 there will be a signal of logical zero, and, therefore, a signal is generated at the fifth output of the demultiplexer (FIG. 2, pos. 24), i.e., on the control bus 24, fixing the device failure (fig.Z).

The positive effect of the invention is that the proposed

Compared to the known device, the device has a higher accuracy of selecting asynchronous signals and a greater depth of control, since it allows controlling the availability of information only on one of the channels. Moreover, when a signal arrives through only one of the channels, the number of this channel is fixed and the device returns to the initial state, i.e. false information is reset on this channel.

Claims (1)

Invention Formula The device for the majority selection of asynchronous signals, containing three flip-flops, the S-inputs of which are connected to the corresponding information inputs of the device, the D-inputs to the common bus, the R-inputs to the reset dump, and the single outputs to the corresponding inputs of the first element I, the output which is connected to the first input of the W-NE element, the second input of which is connected to the pulse counter overflow output, and the output - to the control input of the single pulse former, the clock input of which is connected to the clock pulse bus and with counter counting input  iJrLJlJl.Jl n n JUriJlJlJlJlJlJl.  -uifT fj-5fl s (m five 0 5 0 and the output - with the C-inputs of all triggers, characterized in that, in order to increase the accuracy of the device and increase the depth of control, a fourth trigger is introduced into the device, from the second to the fourth AND elements, the I-HF element: and the demultiplexer, from the first to the eighth the outputs of which are connected to the corresponding control devices of the device, the address inputs to the single outputs of the flip-flops, and the gate input to the output of the single-pulse former and to the first input of the second element I, the second input of which is connected to the reset bus, and the output to S-input of the fourth trigger, the D-input of which is connected to the common bus, C-input - to the output of the third element I and to the first input of the element NAND, the second input of which is connected to the zero output of the fourth trigger, and the output to the reset input of the counter pulses, the inputs of the third element And are connected to the corresponding information inputs of the device, the inputs of the fourth element And are connected respectively to the second, third, fourth and eighth outputs of the demultiplexer, and the output to the output bus of the device.